<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21672">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] asus/p2b-ls: Add ACPI tables<br><br>Add ACPI tables support that will be needed for soft-off and S3 resume.<br>Right now only have DSDT and what was done for asus/p2b.<br><br>This has not yet been boot tested and so is not for merging yet.<br><br>All feedbacks appreciated.<br><br>Change-Id: I28b559406bd53efc555dcbb8282dfe2bd6d1af87<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>---<br>M src/mainboard/asus/p2b-ls/Kconfig<br>A src/mainboard/asus/p2b-ls/acpi_tables.c<br>A src/mainboard/asus/p2b-ls/dsdt.asl<br>3 files changed, 208 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21672/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/asus/p2b-ls/Kconfig b/src/mainboard/asus/p2b-ls/Kconfig<br>index 967ebd9..2bb9369 100644<br>--- a/src/mainboard/asus/p2b-ls/Kconfig<br>+++ b/src/mainboard/asus/p2b-ls/Kconfig<br>@@ -23,6 +23,7 @@<br> select HAVE_PIRQ_TABLE<br> select BOARD_ROMSIZE_KB_256<br> select SDRAMPWR_4DIMM<br>+ select HAVE_ACPI_TABLES<br> <br> config MAINBOARD_DIR<br> string<br>diff --git a/src/mainboard/asus/p2b-ls/acpi_tables.c b/src/mainboard/asus/p2b-ls/acpi_tables.c<br>new file mode 100644<br>index 0000000..d740ee1<br>--- /dev/null<br>+++ b/src/mainboard/asus/p2b-ls/acpi_tables.c<br>@@ -0,0 +1,22 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/acpi.h><br>+<br>+unsigned long acpi_fill_madt(unsigned long current)<br>+{<br>+ /* mainboard has no ioapic */<br>+ return current;<br>+}<br>diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl<br>new file mode 100644<br>index 0000000..7f0d40b<br>--- /dev/null<br>+++ b/src/mainboard/asus/p2b-ls/dsdt.asl<br>@@ -0,0 +1,185 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Keith Hui <buurin@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+/*<br>+ * Mapping of factory BIOS and coreboot ACPI names<br>+ * Factory coreboot<br>+ * DBG1 P80<br>+ *<br>+ * PX40 LPCB<br>+ * PIRx PRTx (x=A|B|C|D)<br>+ * PIRQ PCIC<br>+ * SYSR MBRS (Hardcoded in acpi_tables.c)<br>+ *<br>+ * PS2K KBD<br>+ * PS2M MOU<br>+ * ENFG ENCM (ENTER_CONFIG_MODE)<br>+ * EXFG EXCM (EXIT_CONFIG_MODE)<br>+ * NIDX ADDR<br>+ * NDAT DATA<br>+ * LDNM LDN (PNP_LOGICAL_DEVICE)<br>+ *<br>+ */<br>+#define SUPERIO_PNP_BASE 0x3F0<br>+#define SUPERIO_DEV W977<br>+#define WINBOND_SHOW_UARTA<br>+#define WINBOND_SHOW_UARTB<br>+#define WINBOND_SHOW_FDC<br>+#define WINBOND_SHOW_LPT<br>+<br>+DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1)<br>+{<br>+ OperationRegion(X80, SystemIO, 0x80, 1)<br>+ Field(X80, ByteAcc, NoLock, Preserve)<br>+ {<br>+ P80, 8<br>+ }<br>+ /* Define the main processor. */<br>+ Scope (\_PR)<br>+ {<br>+ /* Looks like the P_CNT field can't be a method or name<br>+ * and has to be hardcoded to 0xe410 or generated in SSDT */<br>+ Processor (CPU0, 0x01, 0xe410, 0x06) {}<br>+ }<br>+<br>+ /* For now only define 2 power states:<br>+ * - S0 which is fully on<br>+ * - S5 which is soft off<br>+ * Any others would involve declaring the wake up methods.<br>+ */<br>+<br>+ /* intel i82371eb (piix4e) datasheet, section 7.2.3, page 142 */<br>+ /*<br>+ 000b / 0x0: soft off/suspend to disk (soff/std) s5<br>+ 001b / 0x1: suspend to ram (str) s3<br>+ 010b / 0x2: powered on suspend, context lost (poscl) s1<br>+ 011b / 0x3: powered on suspend, cpu context lost (posccl) s2<br>+ 100b / 0x4: powered on suspend, context maintained (pos) s4<br>+ 101b / 0x5: working (clock control) s0<br>+ 110b / 0x6: reserved<br>+ 111b / 0x7: reserved<br>+ */<br>+ Name (\_S0, Package () { 0x05, 0x05, 0x00, 0x00 })<br>+ /*Name (\_S1, Package () { 0x04, 0x07, 0x00, 0x00 })*/<br>+ Name (\_S5, Package () { 0x00, 0x06, 0x00, 0x00 })<br>+<br>+ /* Root of the bus hierarchy */<br>+ Scope (\_SB)<br>+ {<br>+ /* Top PCI device */<br>+ Device (PCI0)<br>+ {<br>+ Name (_HID, EisaId ("PNP0A03"))<br>+ Name (_ADR, 0x00)<br>+ Name (_UID, 0x00)<br>+ Name (_BBN, 0x00)<br>+<br>+ /* PCI Routing Table */<br>+ Name (_PRT, Package () {<br>+ Package (0x04) { 0x0001FFFF, 0, LNKA, 0 },<br>+ Package (0x04) { 0x0001FFFF, 1, LNKB, 0 },<br>+ Package (0x04) { 0x0001FFFF, 2, LNKC, 0 },<br>+ Package (0x04) { 0x0001FFFF, 3, LNKD, 0 },<br>+<br>+ Package (0x04) { 0x0004FFFF, 0, LNKA, 0 },<br>+ Package (0x04) { 0x0004FFFF, 1, LNKB, 0 },<br>+ Package (0x04) { 0x0004FFFF, 2, LNKC, 0 },<br>+ Package (0x04) { 0x0004FFFF, 3, LNKD, 0 },<br>+<br>+ Package (0x04) { 0x0006FFFF, 0, LNKD, 0 },<br>+ Package (0x04) { 0x0006FFFF, 1, LNKA, 0 },<br>+ Package (0x04) { 0x0006FFFF, 2, LNKB, 0 },<br>+ Package (0x04) { 0x0006FFFF, 3, LNKC, 0 },<br>+<br>+ Package (0x04) { 0x0009FFFF, 0, LNKD, 0 },<br>+ Package (0x04) { 0x0009FFFF, 1, LNKA, 0 },<br>+ Package (0x04) { 0x0009FFFF, 2, LNKB, 0 },<br>+ Package (0x04) { 0x0009FFFF, 3, LNKC, 0 },<br>+<br>+ Package (0x04) { 0x000AFFFF, 0, LNKC, 0 },<br>+ Package (0x04) { 0x000AFFFF, 1, LNKD, 0 },<br>+ Package (0x04) { 0x000AFFFF, 2, LNKA, 0 },<br>+ Package (0x04) { 0x000AFFFF, 3, LNKB, 0 },<br>+<br>+ Package (0x04) { 0x0007FFFF, 0, LNKC, 0 },<br>+ Package (0x04) { 0x0007FFFF, 1, LNKD, 0 },<br>+ Package (0x04) { 0x0007FFFF, 2, LNKA, 0 },<br>+ Package (0x04) { 0x0007FFFF, 3, LNKB, 0 },<br>+<br>+ Package (0x04) { 0x000BFFFF, 0, LNKB, 0 },<br>+ Package (0x04) { 0x000BFFFF, 1, LNKC, 0 },<br>+ Package (0x04) { 0x000BFFFF, 2, LNKD, 0 },<br>+ Package (0x04) { 0x000BFFFF, 3, LNKA, 0 },<br>+<br>+ Package (0x04) { 0x000CFFFF, 0, LNKA, 0 },<br>+ Package (0x04) { 0x000CFFFF, 1, LNKB, 0 },<br>+ Package (0x04) { 0x000CFFFF, 2, LNKC, 0 },<br>+ Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },<br>+<br>+ })<br>+ /* Begin PX40 southbridge block */<br>+#include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl"<br>+#include "southbridge/intel/i82371eb/acpi/i82371eb.asl"<br>+#include "southbridge/intel/i82371eb/acpi/pirq.asl"<br>+ }<br>+ }<br>+ OperationRegion (GPOB, SystemIO, 0xE42C, 0x10)<br>+ Field (GPOB, ByteAcc, NoLock, Preserve)<br>+ {<br>+ Offset (0x03),<br>+ TO12, 1, /* Device trap 12 */<br>+ Offset (0x08),<br>+ FANM, 1, /* GPO0, meant for fan */<br>+ Offset (0x09),<br>+ PLED, 1, /* GPO8, meant for power LED. Per PIIX4 datasheet this goes low when power is cut from its core. */<br>+ , 3,<br>+ , 2,<br>+ , 16,<br>+ MSG0, 1 /* GPO30, message LED */<br>+ }<br>+<br>+ Method (\_PTS, 1, NotSerialized) // _PTS: Prepare To Sleep, Arg0 is target S-state<br>+ {<br>+ If (LNotEqual (Arg0, 0x05)) /* Off */<br>+ {<br>+ Store (0x00, FANM) /* \FANM */<br>+ Store (0x00, PLED) /* \PLED */<br>+ }<br>+<br>+ If (LEqual (Arg0, 0x01))<br>+ {<br>+ Store (One, TO12) /* \TO12, arms SMI for device 12 */<br>+ }<br>+<br>+ Store (One, TO12) /* \TO12 */<br>+ Or (Arg0, 0xF0, Local2)<br>+ Store (Local2, P80) /* Put out a POST code. */<br>+ }<br>+<br>+ /* ACPI Message */<br>+ Scope (\_SI)<br>+ {<br>+ Method (_MSG, 1, NotSerialized)<br>+ {<br>+ If (LEqual (Arg0, Zero))<br>+ {<br>+ Store (One, MSG0)<br>+ }<br>+ Else<br>+ {<br>+ Store (Zero, MSG0)<br>+ }<br>+ }<br>+ }<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21672">change 21672</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I28b559406bd53efc555dcbb8282dfe2bd6d1af87 </div>
<div style="display:none"> Gerrit-Change-Number: 21672 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>