<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21671">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] sb/intel/i82371eb: Rework ACPI DSDT table<br><br>Enter a major ACPI table rework based on a mix of previous<br>work on asus/p2b, other boards in tree with better ACPI support,<br>and OEM BIOS. Pulls in DSDT table for superios if one is defined<br>(only winbond/w83977tf in this group of patches). To be pulled in<br>by DSDTs of mainboards using this southbridge.<br><br>Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>---<br>A src/southbridge/intel/i82371eb/acpi/i82371eb.asl<br>M src/southbridge/intel/i82371eb/acpi/pirq.asl<br>2 files changed, 245 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/21671/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/i82371eb/acpi/i82371eb.asl b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl<br>new file mode 100644<br>index 0000000..9f3916c<br>--- /dev/null<br>+++ b/src/southbridge/intel/i82371eb/acpi/i82371eb.asl<br>@@ -0,0 +1,241 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2004 Nick Barker <Nick.Barker9@btinternet.com><br>+ * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz><br>+ * Copyright (C) 2017 Keith Hui <buurin@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/*<br>+ * ISA portions taken from QEMU acpi-dsdt.dsl.<br>+ */<br>+#include "southbridge/intel/i82371eb/i82371eb.h"<br>+<br>+// Intel LPC Bus Device - 0:4.0<br>+Device (PX40)<br>+{<br>+ Name(_ADR, 0x00040000)<br>+ OperationRegion (PIRQ, PCI_Config, 0x60, 0x04)<br>+ Field (PIRQ, ByteAcc, NoLock, Preserve)<br>+ {<br>+ PIRA, 8,<br>+ PIRB, 8,<br>+ PIRC, 8,<br>+ PIRD, 8<br>+ }<br>+/*<br>+ * OEM BIOS for asus/p2b-ls reports mainboard resources here whereas<br>+ * ACPI programming of asus/p2b fills this in at runtime.<br>+ */<br>+#if 0<br>+ Device (SYSR)<br>+ {<br>+ Name (_HID, EisaId ("PNP0C02"))<br>+ Method (_CRS, 0, NotSerialized)<br>+ {<br>+ Name (BUF1, ResourceTemplate ()<br>+ {<br>+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x40, _Y06)<br>+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10, _Y07)<br>+ IO (Decode16, 0x0294, 0x0294, 0x01, 0x04, )<br>+ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10, )<br>+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E, )<br>+ IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C, )<br>+ IO (Decode16, 0x0062, 0x0062, 0x01, 0x02, )<br>+ IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B, )<br>+ IO (Decode16, 0x0074, 0x0074, 0x01, 0x0C, )<br>+ IO (Decode16, 0x0091, 0x0091, 0x01, 0x03, )<br>+ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E, )<br>+ IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10, )<br>+ IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x02, )<br>+ IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02, )<br>+ })<br>+ CreateByteField (BUF1, _Y06._MIN, PMLO) // _MIN: Minimum Base Address<br>+ CreateByteField (BUF1, 0x03, PMHI)<br>+ CreateByteField (BUF1, _Y06._MAX, PMRL) // _MAX: Maximum Base Address<br>+ CreateByteField (BUF1, 0x05, PMRH)<br>+ CreateByteField (BUF1, _Y07._MIN, SBLO) // _MIN: Minimum Base Address<br>+ CreateByteField (BUF1, 0x0B, SBHI)<br>+ CreateByteField (BUF1, _Y07._MAX, SBRL) // _MAX: Maximum Base Address<br>+ CreateByteField (BUF1, 0x0D, SBRH)<br>+ Store (\_SB.PCI0.PX43.PM00, Local0)<br>+ And (Local0, 0xFE, PMLO) /* \_SB_.PCI0.PX40.SYSR._CRS.PMLO */<br>+ Store (\_SB.PCI0.PX43.PM01, PMHI) /* \_SB_.PCI0.PX40.SYSR._CRS.PMHI */<br>+ Store (\_SB.PCI0.PX43.SB00, Local0)<br>+ And (Local0, 0xFE, SBLO) /* \_SB_.PCI0.PX40.SYSR._CRS.SBLO */<br>+ Store (\_SB.PCI0.PX43.SB01, SBHI) /* \_SB_.PCI0.PX40.SYSR._CRS.SBHI */<br>+ Store (PMLO, PMRL) /* \_SB_.PCI0.PX40.SYSR._CRS.PMRL */<br>+ Store (PMHI, PMRH) /* \_SB_.PCI0.PX40.SYSR._CRS.PMRH */<br>+ Store (SBLO, SBRL) /* \_SB_.PCI0.PX40.SYSR._CRS.SBRL */<br>+ Store (SBHI, SBRH) /* \_SB_.PCI0.PX40.SYSR._CRS.SBRH */<br>+ Return (BUF1) /* \_SB_.PCI0.PX40.SYSR._CRS.BUF1 */<br>+ }<br>+ }<br>+#endif<br>+/* If a superio (with DSDT table) is selected in mainboard Kconfig,<br>+ * include its ASL code here, otherwise declare a few basic devices<br>+ * that seems to be important for WinXP install. */<br>+#ifdef CONFIG_SUPERIO_WINBOND_W83977TF<br>+#include "superio/winbond/w83977tf/acpi/superio.asl"<br>+#else<br>+ /* PS/2 keyboard (seems to be important for WinXP install) */<br>+ Device (KBD)<br>+ {<br>+ Name (_HID, EisaId ("PNP0303"))<br>+ Method (_STA, 0, NotSerialized)<br>+ {<br>+ Return (0x0f)<br>+ }<br>+ Method (_CRS, 0, NotSerialized)<br>+ {<br>+ Name (TMP, ResourceTemplate () {<br>+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)<br>+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)<br>+ IRQNoFlags () {1}<br>+ })<br>+ Return (TMP)<br>+ }<br>+ }<br>+<br>+ /* PS/2 mouse */<br>+ Device (MOU)<br>+ {<br>+ Name (_HID, EisaId ("PNP0F13"))<br>+ Method (_STA, 0, NotSerialized)<br>+ {<br>+ Return (0x0f)<br>+ }<br>+ Method (_CRS, 0, NotSerialized)<br>+ {<br>+ Name (TMP, ResourceTemplate () {<br>+ IRQNoFlags () {12}<br>+ })<br>+ Return (TMP)<br>+ }<br>+ }<br>+<br>+ /* PS/2 floppy controller */<br>+ Device (FDC0)<br>+ {<br>+ Name (_HID, EisaId ("PNP0700"))<br>+ Method (_STA, 0, NotSerialized)<br>+ {<br>+ Return (0x0f)<br>+ }<br>+ Method (_CRS, 0, NotSerialized)<br>+ {<br>+ Name (BUF0, ResourceTemplate () {<br>+ IO (Decode16, 0x03F2, 0x03F2, 0x00, 0x04)<br>+ IO (Decode16, 0x03F7, 0x03F7, 0x00, 0x01)<br>+ IRQNoFlags () {6}<br>+ DMA (Compatibility, NotBusMaster, Transfer8) {2}<br>+ })<br>+ Return (BUF0)<br>+ }<br>+ }<br>+#endif<br>+ /* PNP Motherboard Resources */<br>+ Device(MBRS) {<br>+ Name (_HID, EisaId ("PNP0C02"))<br>+ Name (_UID, 0x01)<br>+<br>+ External(_CRS) /* Resource Template in SSDT */<br>+ }<br>+<br>+ /* 8259-compatible Programmable Interrupt Controller */<br>+ Device (PIC)<br>+ {<br>+ Name (_HID, EisaId ("PNP0000") )<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16, 0x0020, 0x0020, 0x01, 0x02, )<br>+ IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02, )<br>+ IRQNoFlags () {2}<br>+ })<br>+ }<br>+<br>+ /* PC-class DMA Controller */<br>+ Device (DMA1)<br>+ {<br>+ Name (_HID, EisaId ("PNP0200") )<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ DMA (Compatibility, BusMaster, Transfer8, ) {4}<br>+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10,)<br>+ IO (Decode16, 0x0080, 0x0080, 0x01, 0x11,)<br>+ IO (Decode16, 0x0094, 0x0094, 0x01, 0x0C,)<br>+ IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20,)<br>+ })<br>+ }<br>+<br>+ /* PC-class System Timer */<br>+ Device (TMR)<br>+ {<br>+ Name (_HID, EisaId ("PNP0100"))<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16,0x0040,0x0040,0x01,0x04,)<br>+ IRQNoFlags () {0}<br>+ })<br>+ }<br>+<br>+ /* AT Real-Time Clock */<br>+ Device (RTC)<br>+ {<br>+ Name (_HID, EisaId ("PNP0B00") )<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16,0x0070,0x0070,0x01,0x04,)<br>+ IRQNoFlags () {8}<br>+ })<br>+ }<br>+<br>+ Device (SPKR)<br>+ {<br>+ Name (_HID, EisaId ("PNP0800"))<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16,0x0061,0x0061,0x01,0x01,)<br>+ })<br>+ }<br>+<br>+ /* x87-compatible Floating Point Processing Unit */<br>+ Device (COPR)<br>+ {<br>+ Name (_HID, EisaId ("PNP0C04") )<br>+ Name (_CRS, ResourceTemplate ()<br>+ {<br>+ IO (Decode16,0x00F0,0x00F0,0x01,0x10,)<br>+ IRQNoFlags () {13}<br>+ })<br>+ }<br>+<br>+}<br>+/* Power management functions to allow ACPI reporting of<br>+ * PM and SMBus base port resources */<br>+Device (PX43)<br>+{<br>+ Name (_ADR, 0x00040003) // _ADR: Address<br>+ OperationRegion (IPMU, PCI_Config, PMBA, 0x02)<br>+ Field (IPMU, ByteAcc, NoLock, Preserve)<br>+ {<br>+ PM00, 8,<br>+ PM01, 8<br>+ }<br>+<br>+ OperationRegion (ISMB, PCI_Config, SMBBA, 0x02)<br>+ Field (ISMB, ByteAcc, NoLock, Preserve)<br>+ {<br>+ SB00, 8,<br>+ SB01, 8<br>+ }<br>+}<br>diff --git a/src/southbridge/intel/i82371eb/acpi/pirq.asl b/src/southbridge/intel/i82371eb/acpi/pirq.asl<br>index 6525e1e..e36a0ec 100644<br>--- a/src/southbridge/intel/i82371eb/acpi/pirq.asl<br>+++ b/src/southbridge/intel/i82371eb/acpi/pirq.asl<br>@@ -12,16 +12,6 @@<br> * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br> * GNU General Public License for more details.<br> */<br>-<br>-Field (\_SB.PCI0.LPCB.PCIC, AnyAcc, NoLock, Preserve)<br>-{<br>- Offset (0x60), // Interrupt Routing Registers<br>- PRTA, 8,<br>- PRTB, 8,<br>- PRTC, 8,<br>- PRTD, 8,<br>-}<br>-<br> Name(IRQB, ResourceTemplate(){<br> IRQ(Level,ActiveLow,Shared){15}<br> })<br>@@ -69,7 +59,7 @@<br> } \<br> } \<br> <br>-PCI_INTX_DEV(LNKA, PRTA, 1)<br>-PCI_INTX_DEV(LNKB, PRTB, 2)<br>-PCI_INTX_DEV(LNKC, PRTC, 3)<br>-PCI_INTX_DEV(LNKD, PRTD, 4)<br>+PCI_INTX_DEV(LNKA, \_SB.PCI0.PX40.PIRA, 1)<br>+PCI_INTX_DEV(LNKB, \_SB.PCI0.PX40.PIRB, 2)<br>+PCI_INTX_DEV(LNKC, \_SB.PCI0.PX40.PIRC, 3)<br>+PCI_INTX_DEV(LNKD, \_SB.PCI0.PX40.PIRD, 4)<br></pre><p>To view, visit <a href="https://review.coreboot.org/21671">change 21671</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21671"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Idda424de7859a36e4cac168d5469f9365a6ad421 </div>
<div style="display:none"> Gerrit-Change-Number: 21671 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>