<p>Ravishankar Sarawadi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21605">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/common/block: Update LPC lib<br><br>Add wrapper functions to support SoC specific functionality:<br> 1. Setup PCH LPC interrupt routing.<br> 2. Get SoC's generic IO decoder configuration settings.<br><br>Change-Id: Ib9359765f7293210044b411db49163df0418070a<br>Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com><br>---<br>M src/soc/intel/common/block/include/intelblocks/lpc_lib.h<br>M src/soc/intel/common/block/lpc/lpc_lib.c<br>2 files changed, 69 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/21605/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h<br>index 596c2b5..455f6c2 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h<br>@@ -38,6 +38,14 @@<br> #define LPC_IOE_COMB_EN (1 << 1)<br> #define LPC_IOE_COMA_EN (1 << 0)<br> <br>+#define PCR_DMI_LPCLGIR1 0x2730<br>+#define PCR_DMI_LPCLGIR2 0x2734<br>+#define PCR_DMI_LPCLGIR3 0x2738<br>+#define PCR_DMI_LPCLGIR4 0x273c<br>+<br>+#define PCR_DMI_LPCIOD 0x2770<br>+#define PCR_DMI_LPCIOE 0x2774<br>+<br> /* Serial IRQ control. SERIRQ_QUIET is the default (0). */<br> enum serirq_mode {<br> SERIRQ_QUIET,<br>@@ -75,6 +83,8 @@<br> void lpc_set_eiss(void);<br> /* Set LPC Serial IRQ mode. */<br> void lpc_set_serirq_mode(enum serirq_mode mode);<br>+/* Enable CLKRUN_EN for power gating LPC. */<br>+void lpc_enable_pci_clk_cntl(void);<br> /*<br> * Setup I/O Decode Range Register for LPC<br> * ComA Range 3F8h-3FFh [2:0]<br>@@ -82,5 +92,13 @@<br> * Enable ComA and ComB Port<br> */<br> void lpc_io_setup_comm_a_b(void);<br>+/* Enable PCH LPC by setting up generic decode range registers. */<br>+void pch_enable_lpc(void);<br>+/* Setup PCH LPC interrupt routing. */<br>+void pch_lpc_interrupt_init(void);<br>+/* Retrieve and setup SoC speicific PCH LPC interrupt routing. */<br>+void soc_pch_pirq_init(const struct device *dev);<br>+/* Get SoC's generic IO decoder configuration settings. */<br>+void soc_get_gen_io_dec_config(const struct device *dev, uint32_t *gen_io_dec);<br> <br> #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */<br>diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c<br>index 6b5f29a..6d695ee 100644<br>--- a/src/soc/intel/common/block/lpc/lpc_lib.c<br>+++ b/src/soc/intel/common/block/lpc/lpc_lib.c<br>@@ -18,12 +18,16 @@<br> #define __SIMPLE_DEVICE__<br> <br> #include <assert.h><br>+#include <chip.h><br> #include <console/console.h><br> #include <device/pci.h><br>+#include <intelblocks/itss.h><br> #include <intelblocks/lpc_lib.h><br>+#include <intelblocks/pcr.h><br> #include <lib.h><br> #include "lpc_def.h"<br> #include <soc/pci_devs.h><br>+#include <soc/pcr_ids.h><br> <br> void lpc_enable_fixed_io_ranges(uint16_t io_enables)<br> {<br>@@ -235,3 +239,50 @@<br> /* Enable ComA and ComB Port */<br> lpc_enable_fixed_io_ranges(LPC_IOE_COMA_EN | LPC_IOE_COMB_EN);<br> }<br>+<br>+void pch_enable_lpc(void)<br>+{<br>+ /* Lookup device tree in romstage */<br>+ const struct device *dev;<br>+ uint32_t gen_io_dec[4];<br>+<br>+ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));<br>+ if (!dev || !dev->chip_info)<br>+ return;<br>+<br>+ soc_get_gen_io_dec_config(dev, gen_io_dec);<br>+<br>+ /* Set in PCI generic decode range registers */<br>+ pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(0),<br>+ gen_io_dec[0]);<br>+ pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(1),<br>+ gen_io_dec[1]);<br>+ pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(2),<br>+ gen_io_dec[2]);<br>+ pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(3),<br>+ gen_io_dec[3]);<br>+<br>+ /* Mirror these same settings in DMI PCR */<br>+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1, gen_io_dec[0]);<br>+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR2, gen_io_dec[1]);<br>+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR3, gen_io_dec[2]);<br>+ pcr_write32(PID_DMI, PCR_DMI_LPCLGIR4, gen_io_dec[3]);<br>+}<br>+<br>+void pch_lpc_interrupt_init(void)<br>+{<br>+ const struct device *dev;<br>+<br>+ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));<br>+ if (!dev || !dev->chip_info)<br>+ return;<br>+<br>+ soc_pch_pirq_init(dev);<br>+}<br>+<br>+void lpc_enable_pci_clk_cntl(void)<br>+{<br>+ device_t dev = PCH_DEV_LPC;<br>+<br>+ pci_write_config8(dev, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN);<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21605">change 21605</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib9359765f7293210044b411db49163df0418070a </div>
<div style="display:none"> Gerrit-Change-Number: 21605 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>