<p>Mario Scheithauer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21584">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/apollolake: Make SCI configurable<br><br>The System Control Interrupt is routed per default to IRQ 9. Some<br>mainboards use IRQ 9 for different purpose. Therefore it is necessary to<br>make the SCI configurable on Apollo Lake.<br><br>Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1<br>Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com><br>---<br>M src/soc/intel/apollolake/acpi.c<br>M src/soc/intel/apollolake/chip.c<br>M src/soc/intel/apollolake/chip.h<br>M src/soc/intel/common/block/include/intelblocks/acpi.h<br>4 files changed, 46 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/21584/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c<br>index e4846e4..df4e630 100644<br>--- a/src/soc/intel/apollolake/acpi.c<br>+++ b/src/soc/intel/apollolake/acpi.c<br>@@ -2,6 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2016 Intel Corp.<br>+ * Copyright 2017 Siemens AG.<br> * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)<br> *<br> * This program is free software; you can redistribute it and/or modify<br>@@ -69,6 +70,12 @@<br> return read32((void *)pmc_bar + IRQ_REG);<br> }<br> <br>+void soc_write_sci_irq_select(uint32_t scis)<br>+{<br>+ uintptr_t pmc_bar = soc_read_pmc_base();<br>+ write32((void *)pmc_bar + IRQ_REG, scis);<br>+}<br>+<br> acpi_cstate_t *soc_get_cstate_map(size_t *entries)<br> {<br> *entries = ARRAY_SIZE(cstate_map);<br>diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c<br>index 2c47766..cdeb0a0 100644<br>--- a/src/soc/intel/apollolake/chip.c<br>+++ b/src/soc/intel/apollolake/chip.c<br>@@ -2,6 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2015 - 2017 Intel Corp.<br>+ * Copyright 2017 Siemens AG.<br> * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)<br> * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.)<br> *<br>@@ -25,6 +26,7 @@<br> #include <cpu/x86/msr.h><br> #include <device/device.h><br> #include <device/pci.h><br>+#include <intelblocks/acpi.h><br> #include <intelblocks/fast_spi.h><br> #include <intelblocks/msr.h><br> #include <fsp/api.h><br>@@ -287,6 +289,29 @@<br> MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~PKG_POWER_LIMIT_EN;<br> }<br> <br>+/* Overwrites the SCI IRQ if another IRQ number is given by device tree. */<br>+static void set_sci_irq(void)<br>+{<br>+ static struct soc_intel_apollolake_config *cfg;<br>+ struct device *dev = SA_DEV_ROOT;<br>+ uint32_t scis;<br>+<br>+ if (!dev || !dev->chip_info) {<br>+ printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");<br>+ return;<br>+ }<br>+<br>+ cfg = dev->chip_info;<br>+<br>+ /* Change only if an device tree entry exists. */<br>+ if (cfg->sci_irq) {<br>+ scis = soc_read_sci_irq_select();<br>+ scis &= ~SCI_IRQ_SEL;<br>+ scis |= (cfg->sci_irq << SCI_IRQ_ADJUST);<br>+ soc_write_sci_irq_select(scis);<br>+ }<br>+}<br>+<br> static void soc_init(void *data)<br> {<br> struct global_nvs_t *gnvs;<br>@@ -319,6 +344,12 @@<br> <br> /* Set RAPL MSR for Package power limits*/<br> set_power_limits();<br>+<br>+ /*<br>+ * FSP-S routes SCI to IRQ 9. With the help of this function you can<br>+ * select another IRQ for SCI.<br>+ */<br>+ set_sci_irq();<br> }<br> <br> static void soc_final(void *data)<br>diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h<br>index 33e2dad..882e481 100644<br>--- a/src/soc/intel/apollolake/chip.h<br>+++ b/src/soc/intel/apollolake/chip.h<br>@@ -2,6 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2015 Intel Corp.<br>+ * Copyright 2017 Siemens AG.<br> * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.)<br> *<br> * This program is free software; you can redistribute it and/or modify<br>@@ -78,6 +79,9 @@<br> */<br> uint32_t emmc_rx_cmd_data_cntl2;<br> <br>+ /* Specifies on which IRQ the SCI will internally appear. */<br>+ uint8_t sci_irq;<br>+<br> /* Configure serial IRQ (SERIRQ) line. */<br> enum serirq_mode serirq_mode;<br> <br>diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h<br>index 010773b..85e6ca3 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/acpi.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/acpi.h<br>@@ -2,6 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2017 Intel Corp.<br>+ * Copyright 2017 Siemens AG.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -31,6 +32,9 @@<br> /* Read the scis from soc specific register. Returns int scis value */<br> uint32_t soc_read_sci_irq_select(void);<br> <br>+/* Write the scis from soc specific register. */<br>+void soc_write_sci_irq_select(uint32_t scis);<br>+<br> /*<br> * Calls acpi_write_hpet which creates and fills HPET table and<br> * adds it to the RSDT (and XSDT) structure.<br></pre><p>To view, visit <a href="https://review.coreboot.org/21584">change 21584</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21584"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1 </div>
<div style="display:none"> Gerrit-Change-Number: 21584 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Mario Scheithauer <mario.scheithauer@siemens.com> </div>