<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21570">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/terra: add new board as variant of cyan baseboard<br><br>Add support for google/terra (Asus Chromebook C202SA/C300SA) as<br>a variant of the cyan Braswell baseboard.<br><br>- Add board-specific code as the new terra variant<br>- Add code to the baseboard to handle terra's unique thermal management<br>- Add new shared SPD files to baseboard<br><br>Sourced from Chromium branch firmware-terra-7287.154.B,<br>commit 153f08a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""<br><br>Change-Id: Ib2682eda15a989f2ec20c78317561f5b6a97483a<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/mainboard/google/cyan/Kconfig<br>M src/mainboard/google/cyan/Kconfig.name<br>M src/mainboard/google/cyan/acpi/dptf.asl<br>M src/mainboard/google/cyan/dsdt.asl<br>A src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.hex<br>A src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.hex<br>A src/mainboard/google/cyan/variants/terra/Makefile.inc<br>A src/mainboard/google/cyan/variants/terra/board_info.txt<br>A src/mainboard/google/cyan/variants/terra/devicetree.cb<br>A src/mainboard/google/cyan/variants/terra/gpio.c<br>A src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl<br>A src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl<br>A src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl<br>A src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl<br>A src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl<br>A src/mainboard/google/cyan/variants/terra/include/variant/onboard.h<br>A src/mainboard/google/cyan/variants/terra/ramstage.c<br>A src/mainboard/google/cyan/variants/terra/romstage.c<br>A src/mainboard/google/cyan/variants/terra/spd_util.c<br>19 files changed, 1,625 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/21570/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig<br>index 9e5bc8a..650ef9a 100644<br>--- a/src/mainboard/google/cyan/Kconfig<br>+++ b/src/mainboard/google/cyan/Kconfig<br>@@ -44,12 +44,14 @@<br> default "cyan" if BOARD_GOOGLE_CYAN<br> default "edgar" if BOARD_GOOGLE_EDGAR<br> default "reks" if BOARD_GOOGLE_REKS<br>+ default "terra" if BOARD_GOOGLE_TERRA<br> <br> config MAINBOARD_PART_NUMBER<br> string<br> default "Cyan" if BOARD_GOOGLE_CYAN<br> default "Edgar" if BOARD_GOOGLE_EDGAR<br> default "Reks" if BOARD_GOOGLE_REKS<br>+ default "Terra" if BOARD_GOOGLE_TERRA<br> <br> config MAINBOARD_VENDOR<br> string<br>@@ -60,6 +62,7 @@<br> default "variants/cyan/devicetree.cb" if BOARD_GOOGLE_CYAN<br> default "variants/edgar/devicetree.cb" if BOARD_GOOGLE_EDGAR<br> default "variants/reks/devicetree.cb" if BOARD_GOOGLE_REKS<br>+ default "variants/terra/devicetree.cb" if BOARD_GOOGLE_TERRA<br> <br> config VGA_BIOS_FILE<br> string<br>@@ -84,5 +87,6 @@<br> default "CYAN TEST A-A 1829" if BOARD_GOOGLE_CYAN<br> default "EDGAR TEST A-A 2507" if BOARD_GOOGLE_EDGAR<br> default "REKS TEST A-A 3004" if BOARD_GOOGLE_REKS<br>+ default "TERRA TEST A-A 1650" if BOARD_GOOGLE_TERRA<br> <br> endif # BOARD_GOOGLE_BASEBOARD_CYAN<br>diff --git a/src/mainboard/google/cyan/Kconfig.name b/src/mainboard/google/cyan/Kconfig.name<br>index 8c70a9c..c6c4d20 100644<br>--- a/src/mainboard/google/cyan/Kconfig.name<br>+++ b/src/mainboard/google/cyan/Kconfig.name<br>@@ -9,3 +9,7 @@<br> config BOARD_GOOGLE_REKS<br> bool "Reks"<br> select BOARD_GOOGLE_BASEBOARD_CYAN<br>+<br>+config BOARD_GOOGLE_TERRA<br>+ bool "Terra"<br>+ select BOARD_GOOGLE_BASEBOARD_CYAN<br>diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl<br>index d0eaadd..3ecb040 100644<br>--- a/src/mainboard/google/cyan/acpi/dptf.asl<br>+++ b/src/mainboard/google/cyan/acpi/dptf.asl<br>@@ -18,4 +18,6 @@<br> #include <variant/acpi/dptf.asl><br> <br> /* Include SoC DPTF */<br>+#if !IS_ENABLED(CONFIG_BOARD_GOOGLE_TERRA)<br> #include <acpi/dptf/dptf.asl><br>+#endif<br>diff --git a/src/mainboard/google/cyan/dsdt.asl b/src/mainboard/google/cyan/dsdt.asl<br>index cb6d91a..a49b1a9 100644<br>--- a/src/mainboard/google/cyan/dsdt.asl<br>+++ b/src/mainboard/google/cyan/dsdt.asl<br>@@ -36,7 +36,11 @@<br> Device (PCI0)<br> {<br> #include <acpi/southcluster.asl><br>+#if IS_ENABLED(CONFIG_BOARD_GOOGLE_TERRA)<br>+ #include <variant/acpi/cpu.asl><br>+#else<br> #include <acpi/dptf/cpu.asl><br>+#endif<br> }<br> <br> /* Dynamic Platform Thermal Framework */<br>diff --git a/src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.hex b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.hex<br>new file mode 100644<br>index 0000000..44cd73c<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.hex<br>@@ -0,0 +1,32 @@<br>+91 20 F1 03 04 11 05 0B<br>+03 11 01 08 0A 00 40 01<br>+78 78 90 50 90 11 50 E0<br>+10 04 3C 3C 01 90 00 00<br>+00 00 00 00 00 00 00 A8<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 02 FE 00<br>+00 00 00 00 00 00 00 00<br>+45 44 46 38 31 33 32 41<br>+33 4D 41 2D 47 44 2D 46<br>+20 20 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>diff --git a/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.hex b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.hex<br>new file mode 100644<br>index 0000000..5fd8b40<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.hex<br>@@ -0,0 +1,32 @@<br>+91 20 F1 03 05 19 05 03<br>+03 11 01 08 09 00 00 05<br>+78 78 90 50 90 11 50 E0<br>+90 06 3C 3C 01 90 00 00<br>+00 10 CA FA 00 00 00 A8<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 80 2C 00<br>+00 00 00 00 00 00 75 8C<br>+4D 54 35 32 4C 32 35 36<br>+4D 33 32 44 31 50 46 2D<br>+31 30 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>+00 00 00 00 00 00 00 00<br>diff --git a/src/mainboard/google/cyan/variants/terra/Makefile.inc b/src/mainboard/google/cyan/variants/terra/Makefile.inc<br>new file mode 100644<br>index 0000000..48d1d96<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/Makefile.inc<br>@@ -0,0 +1,42 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2013 Google Inc.<br>+## Copyright (C) 2015 Intel Corp.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+romstage-y += romstage.c<br>+romstage-y += spd_util.c<br>+<br>+ramstage-y += gpio.c<br>+ramstage-y += ramstage.c<br>+<br>+SPD_BIN = $(obj)/spd.bin<br>+<br>+SPD_SOURCES = samsung_dimm_K4E8E304EE-EGCE<br>+SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF<br>+SPD_SOURCES += micron_2GiB_dimm_EDF8132A3MA-GD-F-R<br>+SPD_SOURCES += micron_2GiB_dimm_MT52L256M32D1PF-107WT<br>+<br>+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)<br>+<br>+# Include spd ROM data<br>+$(SPD_BIN): $(SPD_DEPS)<br>+ for f in $+; \<br>+ do for c in $$(cat $$f | grep -v ^#); \<br>+ do printf $$(printf '\%o' 0x$$c); \<br>+ done; \<br>+ done > $@<br>+<br>+cbfs-files-y += spd.bin<br>+spd.bin-file := $(SPD_BIN)<br>+spd.bin-type := spd<br>diff --git a/src/mainboard/google/cyan/variants/terra/board_info.txt b/src/mainboard/google/cyan/variants/terra/board_info.txt<br>new file mode 100644<br>index 0000000..72fcabf<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/board_info.txt<br>@@ -0,0 +1,6 @@<br>+Vendor name: Google<br>+Board name: Terra<br>+Category: laptop<br>+ROM protocol: SPI<br>+ROM socketed: n<br>+Flashrom support: y<br>diff --git a/src/mainboard/google/cyan/variants/terra/devicetree.cb b/src/mainboard/google/cyan/variants/terra/devicetree.cb<br>new file mode 100644<br>index 0000000..2feb1a3<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/devicetree.cb<br>@@ -0,0 +1,150 @@<br>+chip soc/intel/braswell<br>+<br>+ ############################################################<br>+ # Set the parameters for MemoryInit<br>+ ############################################################<br>+<br>+ register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB<br>+<br>+ register "PcdMrcInitMmioSize" = "0x0800"<br>+ register "PcdMrcInitSpdAddr1" = "0xa0"<br>+ register "PcdMrcInitSpdAddr2" = "0xa2"<br>+ register "PcdIgdDvmt50PreAlloc" = "1"<br>+ register "PcdApertureSize" = "2"<br>+ register "PcdGttSize" = "1"<br>+ register "PcdDvfsEnable" = "1"<br>+ register "PcdCaMirrorEn" = "1"<br>+<br>+ ############################################################<br>+ # Set the parameters for SiliconInit<br>+ ############################################################<br>+<br>+ register "PcdSdcardMode" = "PCH_ACPI_MODE"<br>+ register "PcdEnableHsuart0" = "0"<br>+ register "PcdEnableHsuart1" = "1"<br>+ register "PcdEnableAzalia" = "1"<br>+ register "PcdEnableXhci" = "1"<br>+ register "PcdEnableLpe" = "1"<br>+ register "PcdEnableDma0" = "1"<br>+ register "PcdEnableDma1" = "1"<br>+ register "PcdEnableI2C0" = "0"<br>+ register "PcdEnableI2C1" = "1"<br>+ register "PcdEnableI2C2" = "0"<br>+ register "PcdEnableI2C3" = "0"<br>+ register "PcdEnableI2C4" = "1"<br>+ register "PcdEnableI2C5" = "1"<br>+ register "PcdEnableI2C6" = "0"<br>+ register "PunitPwrConfigDisable" = "0" # Enable SVID<br>+ register "ChvSvidConfig" = "SVID_PMIC_CONFIG"<br>+ register "PcdEmmcMode" = "PCH_ACPI_MODE"<br>+ register "PcdUsb3ClkSsc" = "1"<br>+ register "PcdDispClkSsc" = "1"<br>+ register "PcdSataClkSsc" = "1"<br>+ register "PcdEnableSata" = "0" # Disable SATA<br>+ register "Usb2Port0PerPortPeTxiSet" = "7"<br>+ register "Usb2Port0PerPortTxiSet" = "5"<br>+ register "Usb2Port0IUsbTxEmphasisEn" = "2"<br>+ register "Usb2Port0PerPortTxPeHalf" = "1"<br>+ register "Usb2Port1PerPortPeTxiSet" = "7"<br>+ register "Usb2Port1PerPortTxiSet" = "3"<br>+ register "Usb2Port1IUsbTxEmphasisEn" = "2"<br>+ register "Usb2Port1PerPortTxPeHalf" = "1"<br>+ register "Usb2Port2PerPortPeTxiSet" = "7"<br>+ register "Usb2Port2PerPortTxiSet" = "3"<br>+ register "Usb2Port2IUsbTxEmphasisEn" = "2"<br>+ register "Usb2Port2PerPortTxPeHalf" = "1"<br>+ register "Usb2Port3PerPortPeTxiSet" = "7"<br>+ register "Usb2Port3PerPortTxiSet" = "3"<br>+ register "Usb2Port3IUsbTxEmphasisEn" = "2"<br>+ register "Usb2Port3PerPortTxPeHalf" = "1"<br>+ register "Usb2Port4PerPortPeTxiSet" = "7"<br>+ register "Usb2Port4PerPortTxiSet" = "3"<br>+ register "Usb2Port4IUsbTxEmphasisEn" = "2"<br>+ register "Usb2Port4PerPortTxPeHalf" = "1"<br>+ register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a"<br>+ register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64"<br>+ register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64"<br>+ register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a"<br>+ register "PcdSataInterfaceSpeed" = "3"<br>+ register "PcdPchSsicEnable" = "1"<br>+ register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM<br>+ register "PMIC_I2CBus" = "1"<br>+ register "ISPEnable" = "0" # Disable IUNIT<br>+ register "ISPPciDevConfig" = "3"<br>+ register "PcdSdDetectChk" = "0" # Disable SD card detect<br>+ register "I2C0Frequency" = "1"<br>+ register "I2C1Frequency" = "2" # Set the PMIC clock speed to 1Mhz<br>+ register "I2C2Frequency" = "1"<br>+ register "I2C3Frequency" = "1"<br>+ register "I2C4Frequency" = "1"<br>+ register "I2C5Frequency" = "1"<br>+ register "I2C6Frequency" = "1"<br>+<br>+ # LPE audio codec settings<br>+ register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock<br>+<br>+ # Enable devices in ACPI mode<br>+ register "lpss_acpi_mode" = "1"<br>+ register "emmc_acpi_mode" = "1"<br>+ register "sd_acpi_mode" = "1"<br>+ register "lpe_acpi_mode" = "1"<br>+<br>+ # Disable SLP_X stretching after SUS power well fail.<br>+ register "disable_slp_x_stretch_sus_fail" = "1"<br>+<br>+ # Allow PCIe devices to wake system from suspend<br>+ register "pcie_wake_enable" = "1"<br>+<br>+ device cpu_cluster 0 on<br>+ device lapic 0 on end<br>+ end<br>+ device domain 0 on<br>+ # EDS Table 24-4, Figure 24-5<br>+ device pci 00.0 on end # 8086 2280 - SoC transaction router<br>+ device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display<br>+ device pci 03.0 off end # 8086 22b8 - Camera and Image Processor<br>+ device pci 0b.0 on end # 8086 22dc - ?<br>+ device pci 10.0 on end # 8086 2294 - MMC Port<br>+ device pci 11.0 off end # 8086 0F15 - SDIO Port<br>+ device pci 12.0 on end # 8086 0F16 - SD Port<br>+ device pci 13.0 off end # 8086 22a3 - Sata controller<br>+ device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time<br>+ device pci 15.0 on end # 8086 22a8 - LP Engine Audio<br>+ device pci 16.0 off end # 8086 22b7 - USB device<br>+ device pci 18.0 on end # 8086 22c0 - SIO - DMA<br>+ device pci 18.1 off end # 8086 22c1 - I2C Port 1<br>+ device pci 18.2 on end # 8086 22c2 - I2C Port 2<br>+ device pci 18.3 off end # 8086 22c3 - I2C Port 3<br>+ device pci 18.4 off end # 8086 22c4 - I2C Port 4<br>+ device pci 18.5 on end # 8086 22c5 - I2C Port 5<br>+ device pci 18.6 on end # 8086 22c6 - I2C Port 6<br>+ device pci 18.7 off end # 8086 22c7 - I2C Port 7<br>+ device pci 1a.0 off end # 8086 0F18 - Trusted Execution Engine<br>+ device pci 1b.0 on end # 8086 0F04 - HD Audio<br>+ device pci 1c.0 on end # 8086 0000 - PCIe Root Port 1<br>+ device pci 1c.1 off end # 8086 0000 - PCIe Root Port 2<br>+ device pci 1c.2 on end # 8086 0000 - PCIe Root Port 3<br>+ device pci 1c.3 off end # 8086 0000 - PCIe Root Port 4<br>+ device pci 1e.0 on end # 8086 2286 - SIO - DMA<br>+ device pci 1e.1 off end # 8086 0F08 - PWM 1<br>+ device pci 1e.2 off end # 8086 0F09 - PWM 2<br>+ device pci 1e.3 on end # 8086 228a - HSUART 1<br>+ device pci 1e.4 off end # 8086 228c - HSUART 2<br>+ device pci 1e.5 on end # 8086 228e - SPI 1<br>+ device pci 1e.6 off end # 8086 2290 - SPI 2<br>+ device pci 1e.7 off end # 8086 22ac - SPI 3<br>+ device pci 1f.0 on # 8086 229c - LPC bridge<br>+ chip drivers/pc80/tpm<br>+ # Rising edge interrupt<br>+ register "irq_polarity" = "2"<br>+ device pnp 0c31.0 on<br>+ irq 0x70 = 10<br>+ end<br>+ end<br>+ chip ec/google/chromeec<br>+ device pnp 0c09.0 on end<br>+ end<br>+ end # LPC Bridge<br>+ device pci 1f.3 off end # 8086 0F12 - SMBus 0<br>+ end<br>+end<br>diff --git a/src/mainboard/google/cyan/variants/terra/gpio.c b/src/mainboard/google/cyan/variants/terra/gpio.c<br>new file mode 100644<br>index 0000000..200ef2b<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/gpio.c<br>@@ -0,0 +1,257 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright(C) 2013 Google Inc.<br>+ * Copyright (C) 2015 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <mainboard/google/cyan/irqroute.h><br>+#include <soc/gpio.h><br>+#include <stdlib.h><br>+<br>+/* South East Community */<br>+static const struct soc_gpio_map gpse_gpio_map[] = {<br>+ Native_M1,/* MF_PLT_CLK0 */<br>+ GPIO_NC, /* 01 PWM1 */<br>+ GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */<br>+ GPIO_NC, /* 03 MF_PLT_CLK4 */<br>+ GPIO_NC, /* 04 MF_PLT_CLK3 */<br>+ GPIO_NC, /* PWM0 05 */<br>+ GPIO_NC, /* 06 MF_PLT_CLK5 */<br>+ GPIO_NC, /* 07 MF_PLT_CLK2 */<br>+ GPIO_NC, /* 15 SDMMC2_D3_CD_B */<br>+ Native_M1, /* 16 SDMMC1_CLK */<br>+ NATIVE_PU20K(1), /* 17 SDMMC1_D0 */<br>+ GPIO_NC, /* 18 SDMMC2_D1 */<br>+ GPIO_NC, /* 19 SDMMC2_CLK */<br>+ NATIVE_PU20K(1),/* 20 SDMMC1_D2 */<br>+ GPIO_NC, /* 21 SDMMC2_D2 */<br>+ GPIO_NC, /* 22 SDMMC2_CMD */<br>+ NATIVE_PU20K(1), /* 23 SDMMC1_CMD */<br>+ NATIVE_PU20K(1), /* 24 SDMMC1_D1 */<br>+ GPIO_NC, /* 25 SDMMC2_D0 */<br>+ NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */<br>+ NATIVE_PU20K(1), /* 30 SDMMC3_D1 */<br>+ Native_M1, /* 31 SDMMC3_CLK */<br>+ NATIVE_PU20K(1), /* 32 SDMMC3_D3 */<br>+ NATIVE_PU20K(1), /* 33 SDMMC3_D2 */<br>+ NATIVE_PU20K(1), /* 34 SDMMC3_CMD */<br>+ NATIVE_PU20K(1), /* 35 SDMMC3_D0 */<br>+ NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */<br>+ NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */<br>+ NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */<br>+ Native_M1, /* 48 LPC_FRAMEB */<br>+ Native_M1, /* 49 MF_LPC_CLKOUT1 */<br>+ NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */<br>+ Native_M1, /* 51 MF_LPC_CLKOUT0 */<br>+ NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */<br>+ Native_M1,/* SPI1_MISO */<br>+ Native_M1, /* 61 SPI1_CS0_B */<br>+ Native_M1, /* SPI1_CLK */<br>+ NATIVE_PU20K(1), /* 63 MMC1_D6 */<br>+ Native_M1, /* 62 SPI1_MOSI */<br>+ NATIVE_PU20K(1), /* 65 MMC1_D5 */<br>+ GPIO_NC, /* SPI1_CS1_B 66 */<br>+ NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */<br>+ NATIVE_PU20K(1), /* 68 MMC1_D7 */<br>+ GPIO_NC, /* 69 MMC1_RCLK */<br>+ Native_M1, /* 75 GPO USB_OC1_B */<br>+ Native_M1, /* 76 PMU_RESETBUTTON_B */<br>+ GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA),<br>+ /* GPIO_ALERT 77 */<br>+ Native_M1, /* 78 SDMMC3_PWR_EN_B */<br>+ GPIO_NC, /* 79 GPI ILB_SERIRQ */<br>+ Native_M1, /* 80 USB_OC0_B */<br>+ NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */<br>+ GPIO_NC, /* 82 spkr asummed gpio number */<br>+ Native_M1, /* 83 SUSPWRDNACK */<br>+ SPARE_PIN,/* 84 spare pin */<br>+ Native_M1, /* 85 SDMMC3_1P8_EN */<br>+ GPIO_END<br>+};<br>+<br>+<br>+/* South West Community */<br>+static const struct soc_gpio_map gpsw_gpio_map[] = {<br>+ GPIO_NC, /* 00 FST_SPI_D2 */<br>+ Native_M1, /* 01 FST_SPI_D0 */<br>+ Native_M1, /* 02 FST_SPI_CLK */<br>+ GPIO_NC, /* 03 FST_SPI_D3 */<br>+ GPIO_NC, /* GPO FST_SPI_CS1_B */<br>+ Native_M1, /* 05 FST_SPI_D1 */<br>+ Native_M1, /* 06 FST_SPI_CS0_B */<br>+ GPIO_NC, /* 07 FST_SPI_CS2_B */<br>+ GPIO_NC, /* 15 UART1_RTS_B */<br>+ Native_M2, /* 16 UART1_RXD */<br>+ GPIO_NC, /* 17 UART2_RXD */<br>+ GPIO_NC, /* 18 UART1_CTS_B */<br>+ GPIO_NC, /* 19 UART2_RTS_B */<br>+ Native_M2, /* 20 UART1_TXD */<br>+ GPIO_NC, /* 21 UART2_TXD */<br>+ GPIO_NC, /* 22 UART2_CTS_B */<br>+ GPIO_NC, /* 30 MF_HDA_CLK */<br>+ GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */<br>+ GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */<br>+ GPIO_NC, /* 33 MF_HDA_SDO */<br>+ GPIO_NC, /* 34 MF_HDA_DOCKRSTB */<br>+ GPIO_NC, /* 35 MF_HDA_SYNC */<br>+ GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */<br>+ GPIO_NC, /* 37 MF_HDA_DOCKENB */<br>+ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */<br>+ NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */<br>+ Native_M2, /* 47 I2C6_SDA */<br>+ NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */<br>+ GPIO_NC, /* 49 I2C_NFC_SDA */<br>+ NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */<br>+ GPIO_NC, /* 51 I2C6_SCL */<br>+ GPIO_NC, /* 52 I2C_NFC_SCL */<br>+ NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */<br>+ GPIO_NC, /* 61 I2C0_SDA */<br>+ GPIO_NC, /* 62 I2C2_SDA */<br>+ NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */<br>+ GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/<br>+ GPIO_NC, /* 65 I2C0_SCL */<br>+ GPIO_NC, /* 66 I2C2_SCL */<br>+ GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */<br>+ GPIO_OUT_HIGH, /* 75 SATA_GP0 */<br>+ GPIO_NC, /* 76 GPI SATA_GP1 */<br>+ GPIO_INPUT_PU_20K, /* 77 SATA_LEDN, EC_IN_RW */<br>+ GPIO_NC, /* 78 SATA_GP2 */<br>+ GPIO_NC, /* 79 MF_SMB_ALERTB */<br>+ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */<br>+ Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */<br>+ Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */<br>+ /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */<br>+ Native_M1, /* 90 PCIE_CLKREQ0B */<br>+ GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */<br>+ Native_M1, /* 92 GP_SSP_2_CLK */<br>+ NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */<br>+ Native_M1, /* 94 GP_SSP_2_RXD */<br>+ GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA),<br>+ /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */<br>+ Native_M1, /* 96 GP_SSP_2_FS */<br>+ NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */<br>+ GPIO_END<br>+};<br>+<br>+<br>+/* North Community */<br>+static const struct soc_gpio_map gpn_gpio_map[] = {<br>+ GPIO_NC, /* 00 GPIO_DFX0 */<br>+ GPIO_NC, /* 01 GPIO_DFX3 */<br>+ GPIO_NC, /* 02 GPIO_DFX7 */<br>+ GPIO_NC, /* 03 GPIO_DFX1 */<br>+ GPIO_NC, /* 04 GPIO_DFX5 */<br>+ GPIO_NC, /* 05 GPIO_DFX4 */<br>+ GPIO_NC, /* 06 GPIO_DFX8 */<br>+ GPIO_NC, /* 07 GPIO_DFX2 */<br>+ GPIO_NC, /* 08 GPIO_DFX6 */<br>+ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data ,<br>+ UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */<br>+ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */<br>+ GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA),<br>+ /* 17 GPIO_SUS3 */<br>+ GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA),<br>+ /* 18 GPIO_SUS7 */<br>+ GPIO_NC, /* 19 GPIO_SUS1 */<br>+ GPIO_NC, /* 20 GPIO_SUS5 */<br>+ GPIO_NC, /* 21 SEC_GPIO_SUS11 */<br>+ GPIO_NC, /* 22 GPIO_SUS4 */<br>+ GPIO_NC,<br>+ /* 23 SEC_GPIO_SUS8 */<br>+ Native_M6, /* 24 GPIO_SUS2 */<br>+ GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */<br>+ Native_M1, /* 26 CX_PREQ_B */<br>+ GPIO_NC, /* 27 SEC_GPIO_SUS9 */<br>+ Native_M1, /* 30 TRST_B */<br>+ Native_M1, /* 31 TCK */<br>+ GPIO_SKIP, /* 32 PROCHOT_B */<br>+ GPIO_SKIP, /* 33 SVID0_DATA */<br>+ Native_M1, /* 34 TMS */<br>+ GPIO_NC, /* 35 CX_PRDY_B_2 */<br>+ GPIO_NC, /* 36 TDO_2 */<br>+ Native_M1, /* 37 CX_PRDY_B */<br>+ GPIO_SKIP, /* 38 SVID0_ALERT_B */<br>+ Native_M1, /* 39 TDO */<br>+ GPIO_SKIP, /* 40 SVID0_CLK */<br>+ Native_M1, /* 41 TDI */<br>+ Native_M2, /* 45 GP_CAMERASB05 */<br>+ Native_M2, /* 46 GP_CAMERASB02 */<br>+ Native_M2, /* 47 GP_CAMERASB08 */<br>+ Native_M2, /* 48 GP_CAMERASB00 */<br>+ Native_M2, /* 49 GP_CAMERASBO6 */<br>+ GPIO_NC, /* 50 GP_CAMERASB10 */<br>+ Native_M2, /* 51 GP_CAMERASB03 */<br>+ GPIO_NC, /* 52 GP_CAMERASB09 */<br>+ Native_M2, /* 53 GP_CAMERASB01 */<br>+ Native_M2, /* 54 GP_CAMERASB07 */<br>+ GPIO_NC, /* 55 GP_CAMERASB11 */<br>+ Native_M2, /* 56 GP_CAMERASB04 */<br>+ GPIO_NC, /* 60 PANEL0_BKLTEN */<br>+ GPIO_NC, /* 61 HV_DDI0_HPD */<br>+ NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */<br>+ Native_M1, /* 63 PANEL1_BKLTCTL */<br>+ NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */<br>+ GPIO_NC, /* 65 PANEL0_BKLTCTL */<br>+ GPIO_NC, /* 66 HV_DDI0_DDC_SDA */<br>+ NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */<br>+ NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */<br>+ Native_M1, /* 69 PANEL1_VDDEN */<br>+ Native_M1, /* 70 PANEL1_BKLTEN */<br>+ GPIO_NC, /* 71 HV_DDI0_DDC_SCL */<br>+ GPIO_NC, /* 72 PANEL0_VDDEN */<br>+ GPIO_END<br>+};<br>+<br>+<br>+/* East Community */<br>+static const struct soc_gpio_map gpe_gpio_map[] = {<br>+ Native_M1, /* 00 PMU_SLP_S3_B */<br>+ GPIO_NC, /* 01 PMU_BATLOW_B */<br>+ Native_M1, /* 02 SUS_STAT_B */<br>+ Native_M1, /* 03 PMU_SLP_S0IX_B */<br>+ Native_M1, /* 04 PMU_AC_PRESENT */<br>+ Native_M1, /* 05 PMU_PLTRST_B */<br>+ Native_M1, /* 06 PMU_SUSCLK */<br>+ GPIO_NC, /* 07 PMU_SLP_LAN_B */<br>+ Native_M1, /* 08 PMU_PWRBTN_B */<br>+ Native_M1, /* 09 PMU_SLP_S4_B */<br>+ NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */<br>+ GPIO_NC, /* 11 PMU_WAKE_LAN_B */<br>+ GPIO_NC, /* 15 MF_GPIO_3 */<br>+ GPIO_NC, /* 16 MF_GPIO_7 */<br>+ GPIO_NC, /* 17 MF_I2C1_SCL */<br>+ GPIO_NC, /* 18 MF_GPIO_1 */<br>+ GPIO_NC, /* 19 MF_GPIO_5 */<br>+ GPIO_NC, /* 20 MF_GPIO_9 */<br>+ GPIO_NC, /* 21 MF_GPIO_0 */<br>+ GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */<br>+ GPIO_NC, /* 23 MF_GPIO_8 */<br>+ GPIO_NC, /* 24 MF_GPIO_2 */<br>+ GPIO_NC, /* 25 MF_GPIO_6 */<br>+ GPIO_NC, /* 26 MF_I2C1_SDA */<br>+ GPIO_END<br>+};<br>+<br>+<br>+static struct soc_gpio_config gpio_config = {<br>+ /* BSW */<br>+ .north = gpn_gpio_map,<br>+ .southeast = gpse_gpio_map,<br>+ .southwest = gpsw_gpio_map,<br>+ .east = gpe_gpio_map<br>+};<br>+<br>+struct soc_gpio_config *mainboard_get_gpios(void)<br>+{<br>+ return &gpio_config;<br>+}<br>diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl<br>new file mode 100644<br>index 0000000..ee247f2<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/charger.asl<br>@@ -0,0 +1,93 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Google Inc.<br>+ * Copyright (C) 2105 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+Device (TCHG)<br>+{<br>+ Name (_HID, "INT3403")<br>+ Name (_UID, 0)<br>+ Name (PTYP, 0x0B)<br>+ Name (_STR, Unicode("Battery Charger"))<br>+<br>+ Method (_STA)<br>+ {<br>+ If (LEqual (\DPTE, One)) {<br>+ Return (0xF)<br>+ } Else {<br>+ Return (0x0)<br>+ }<br>+ }<br>+<br>+ /* Return charger performance states defined by Terra2 or Terra3 mainboard */<br>+ Method (PPSS)<br>+ {<br>+ If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Return (\_SB.CPT2)<br>+ } Else {<br>+ Return (\_SB.CPT3)<br>+ }<br>+ }<br>+<br>+ /* Return maximum charger current limit */<br>+ Method (PPPC)<br>+ {<br>+ /* Convert size of PPSS table to index */<br>+ If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Store (SizeOf (\_SB.CPT2), Local0)<br>+ } Else {<br>+ Store (SizeOf (\_SB.CPT3), Local0)<br>+ }<br>+<br>+ Decrement (Local0)<br>+<br>+ /* Check if charging is disabled (AC removed) */<br>+ If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) {<br>+ /* Return last power state */<br>+ Return (Local0)<br>+ } Else {<br>+ /* Return highest power state */<br>+ Return (0)<br>+ }<br>+<br>+ Return (0)<br>+ }<br>+<br>+ /* Set charger current limit */<br>+ Method (SPPC, 1)<br>+ {<br>+ /* Retrieve Control (index 4) for specified PPSS level */<br>+ /* Convert size of PPSS table to index */<br>+ If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Store (DeRefOf (Index (DeRefOf (Index<br>+ (\_SB.CPT2, ToInteger (Arg0))), 4)), Local0)<br>+ } Else {<br>+ Store (DeRefOf (Index (DeRefOf (Index<br>+ (\_SB.CPT3, ToInteger (Arg0))), 4)), Local0)<br>+ }<br>+<br>+ /* Pass Control value to EC to limit charging */<br>+ \_SB.PCI0.LPCB.EC0.CHGS (Local0)<br>+ }<br>+<br>+ /* Initialize charger participant */<br>+ Method (INIT)<br>+ {<br>+ /* Disable charge limit */<br>+ \_SB.PCI0.LPCB.EC0.CHGD ()<br>+ }<br>+}<br>diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl<br>new file mode 100644<br>index 0000000..bab215d<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl<br>@@ -0,0 +1,227 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef DPTF_CPU_PASSIVE<br>+#define DPTF_CPU_PASSIVE 80<br>+#endif<br>+<br>+#ifndef DPTF_CPU_CRITICAL<br>+#define DPTF_CPU_CRITICAL 90<br>+#endif<br>+<br>+#ifndef DPTF_CPU_ACTIVE_AC0<br>+#define DPTF_CPU_ACTIVE_AC0 90<br>+#endif<br>+<br>+#ifndef DPTF_CPU_ACTIVE_AC1<br>+#define DPTF_CPU_ACTIVE_AC1 80<br>+#endif<br>+<br>+#ifndef DPTF_CPU_ACTIVE_AC2<br>+#define DPTF_CPU_ACTIVE_AC2 70<br>+#endif<br>+<br>+#ifndef DPTF_CPU_ACTIVE_AC3<br>+#define DPTF_CPU_ACTIVE_AC3 60<br>+#endif<br>+<br>+#ifndef DPTF_CPU_ACTIVE_AC4<br>+#define DPTF_CPU_ACTIVE_AC4 50<br>+#endif<br>+<br>+External (\_PR.CP00._TSS, MethodObj)<br>+External (\_PR.CP00._TPC, MethodObj)<br>+External (\_PR.CP00._PTC, PkgObj)<br>+External (\_PR.CP00._TSD, PkgObj)<br>+External (\_PR.CP00._PSS, MethodObj)<br>+External (\_SB.DPTF.CTOK, MethodObj)<br>+External (\_SB.GPID, MethodObj)<br>+<br>+Device (B0DB)<br>+{<br>+ Name (_ADR, 0x000B0000) /* Bus 0, Device B, Function 0 */<br>+<br>+ Method (_STA)<br>+ {<br>+ If (LEqual (\DPTE, One)) {<br>+ Return (0xF)<br>+ } Else {<br>+ Return (0x0)<br>+ }<br>+ }<br>+<br>+ /*<br>+ * Processor Throttling Controls<br>+ */<br>+<br>+ Method (_TSS)<br>+ {<br>+ If (CondRefOf (\_PR.CP00._TSS)) {<br>+ Return (\_PR.CP00._TSS)<br>+ } Else {<br>+ Return (Package ()<br>+ {<br>+ Package () { 0, 0, 0, 0, 0 }<br>+ })<br>+ }<br>+ }<br>+<br>+ Method (_TPC)<br>+ {<br>+ If (CondRefOf (\_PR.CP00._TPC)) {<br>+ Return (\_PR.CP00._TPC)<br>+ } Else {<br>+ Return (0)<br>+ }<br>+ }<br>+<br>+ Method (_PTC)<br>+ {<br>+ If (CondRefOf (\_PR.CP00._PTC)) {<br>+ Return (\_PR.CP00._PTC)<br>+ } Else {<br>+ Return (Package ()<br>+ {<br>+ Buffer () { 0 },<br>+ Buffer () { 0 }<br>+ })<br>+ }<br>+ }<br>+<br>+ Method (_TSD)<br>+ {<br>+ If (CondRefOf (\_PR.CP00._TSD)) {<br>+ Return (\_PR.CP00._TSD)<br>+ } Else {<br>+ Return (Package ()<br>+ {<br>+ Package () { 5, 0, 0, 0, 0 }<br>+ })<br>+ }<br>+ }<br>+<br>+ Method (_TDL)<br>+ {<br>+ If (CondRefOf (\_PR.CP00._TSS)) {<br>+ Store (SizeOf (\_PR.CP00._TSS ()), Local0)<br>+ Decrement (Local0)<br>+ Return (Local0)<br>+ } Else {<br>+ Return (0)<br>+ }<br>+ }<br>+<br>+ /*<br>+ * Processor Performance Control<br>+ */<br>+<br>+ Method (_PPC)<br>+ {<br>+ Return (0)<br>+ }<br>+<br>+ Method (SPPC, 1)<br>+ {<br>+ Store (Arg0, \PPCM)<br>+<br>+ /* Notify OS to re-read _PPC limit on each CPU */<br>+ \PPCN ()<br>+ }<br>+<br>+ Method (_PSS)<br>+ {<br>+ If (CondRefOf (\_PR.CP00._PSS)) {<br>+ Return (\_PR.CP00._PSS)<br>+ } Else {<br>+ Return (Package ()<br>+ {<br>+ Package () { 0, 0, 0, 0, 0, 0 }<br>+ })<br>+ }<br>+ }<br>+<br>+ Method (_PDL)<br>+ {<br>+ /* Check for mainboard specific _PDL override */<br>+ If (CondRefOf (\_SB.MPDL)) {<br>+ Return (\_SB.MPDL)<br>+ } ElseIf (CondRefOf (\_PR.CP00._PSS)) {<br>+ Store (SizeOf (\_PR.CP00._PSS ()), Local0)<br>+ Decrement (Local0)<br>+ Return (Local0)<br>+ } Else {<br>+ Return (0)<br>+ }<br>+ }<br>+<br>+ /* Return PPCC table defined by Terra2 or Terra3 mainboard */<br>+ Method (PPCC)<br>+ {<br>+ If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Return (\_SB.PPT2)<br>+ } Else {<br>+ Return (\_SB.PPT3)<br>+ }<br>+ }<br>+<br>+ /* Return critical thermal point defined by Terra2 or Terra3 mainboard */<br>+ Method (_CRT)<br>+ {<br>+ If (Lequal(\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Return (\_SB.DPTF.CTOK(DPTF_TERRA2_CPU_CRITICAL))<br>+ } Else {<br>+ Return (\_SB.DPTF.CTOK(DPTF_TERRA3_CPU_CRITICAL))<br>+ }<br>+ }<br>+<br>+ /* Return passive thermal point defined by Terra2 or Terra3 mainboard */<br>+ Method (_PSV)<br>+ {<br>+ If (Lequal(\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Return (\_SB.DPTF.CTOK(DPTF_TERRA2_CPU_PASSIVE))<br>+ } Else {<br>+ Return (\_SB.DPTF.CTOK(DPTF_TERRA3_CPU_PASSIVE))<br>+ }<br>+ }<br>+<br>+ Method (_AC0)<br>+ {<br>+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC0))<br>+ }<br>+<br>+ Method (_AC1)<br>+ {<br>+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC1))<br>+ }<br>+<br>+ Method (_AC2)<br>+ {<br>+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC2))<br>+ }<br>+<br>+ Method (_AC3)<br>+ {<br>+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC3))<br>+ }<br>+<br>+ Method (_AC4)<br>+ {<br>+ Return (\_SB.DPTF.CTOK(DPTF_CPU_ACTIVE_AC4))<br>+ }<br>+}<br>diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl<br>new file mode 100644<br>index 0000000..7dd3cac<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/dptf.asl<br>@@ -0,0 +1,236 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Google Inc.<br>+ * Copyright (C) 2105 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#define DPTF_TSR0_SENSOR_ID 0<br>+#define DPTF_TSR0_SENSOR_NAME "TMP432_CPU"<br>+<br>+#define DPTF_TSR1_SENSOR_ID 1<br>+#define DPTF_TSR1_SENSOR_NAME "TMP432_WLAN"<br>+<br>+#define DPTF_TSR2_SENSOR_ID 2<br>+#define DPTF_TSR2_SENSOR_NAME "TMP432_CHARGER"<br>+<br>+#define DPTF_TERRA2_TSR0_PASSIVE 60<br>+#define DPTF_TERRA2_TSR0_CRITICAL 75<br>+<br>+#define DPTF_TERRA2_TSR1_PASSIVE 53<br>+#define DPTF_TERRA2_TSR1_CRITICAL 75<br>+<br>+#define DPTF_TERRA2_TSR2_PASSIVE 53<br>+#define DPTF_TERRA2_TSR2_CRITICAL 75<br>+<br>+#define DPTF_TERRA3_TSR0_PASSIVE 50<br>+#define DPTF_TERRA3_TSR0_CRITICAL 75<br>+<br>+#define DPTF_TERRA3_TSR1_PASSIVE 52<br>+#define DPTF_TERRA3_TSR1_CRITICAL 75<br>+<br>+#define DPTF_TERRA3_TSR2_PASSIVE 53<br>+#define DPTF_TERRA3_TSR2_CRITICAL 75<br>+<br>+#define DPTF_ENABLE_CHARGER<br>+<br>+/* Terra2 - Charger performance states, board-specific values from charger and EC */<br>+Name (CPT2, Package () {<br>+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */<br>+ Package () { 0, 0, 0, 0, 24, 0x320, "mA", 0 }, /* 0.8A */<br>+ Package () { 0, 0, 0, 0, 16, 0x258, "mA", 0 }, /* 0.6A */<br>+ Package () { 0, 0, 0, 0, 8, 0x190, "mA", 0 }, /* 0.4A */<br>+ Package () { 0, 0, 0, 0, 0, 0x64, "mA", 0 }, /* 0.1A */<br>+})<br>+<br>+/* Terra3 - Charger performance states, board-specific values from charger and EC */<br>+Name (CPT3, Package () {<br>+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */<br>+ Package () { 0, 0, 0, 0, 24, 0x320, "mA", 0 }, /* 0.8A */<br>+ Package () { 0, 0, 0, 0, 16, 0x258, "mA", 0 }, /* 0.6A */<br>+ Package () { 0, 0, 0, 0, 8, 0x190, "mA", 0 }, /* 0.4A */<br>+ Package () { 0, 0, 0, 0, 0, 0x64, "mA", 0 }, /* 0.1A */<br>+})<br>+<br>+/* Mainboard specific _PDL is 1GHz */<br>+Name (MPDL, 8)<br>+<br>+/* Terra2 - Thermal Relationship Table for method _TRT */<br>+Name (TRT2, Package () {<br>+ /* CPU Throttle Effect on CPU */<br>+ Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 10, 0, 0, 0, 0 },<br>+#ifdef DPTF_ENABLE_CHARGER<br>+ /* Charger Effect on Temp Sensor 0 */<br>+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 200, 100, 0, 0, 0, 0 },<br>+#endif<br>+ /* CPU Effect on Temp Sensor 0 */<br>+ Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },<br>+#ifdef DPTF_ENABLE_CHARGER<br>+ /* Charger Effect on Temp Sensor 1 */<br>+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 100, 0, 0, 0, 0 },<br>+#endif<br>+ /* CPU Effect on Temp Sensor 1 */<br>+ Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 200, 100, 0, 0, 0, 0 },<br>+#ifdef DPTF_ENABLE_CHARGER<br>+ /* Charger Effect on Temp Sensor 2 */<br>+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 100, 0, 0, 0, 0 },<br>+#endif<br>+ /* CPU Effect on Temp Sensor 2 */<br>+ Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 200, 100, 0, 0, 0, 0 },<br>+})<br>+<br>+/* Terra3 - Thermal Relationship Table for method _TRT */<br>+Name (TRT3, Package () {<br>+ /* CPU Throttle Effect on CPU */<br>+ Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 10, 0, 0, 0, 0 },<br>+<br>+ /* CPU Effect on Temp Sensor 0 */<br>+ Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 },<br>+#ifdef DPTF_ENABLE_CHARGER<br>+ /* Charger Effect on Temp Sensor 1 */<br>+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 100, 0, 0, 0, 0 },<br>+#endif<br>+<br>+ /* CPU Effect on Temp Sensor 1 */<br>+ Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 200, 100, 0, 0, 0, 0 },<br>+<br>+ /* Charger Effect on Temp Sensor 2 */<br>+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 100, 0, 0, 0, 0 },<br>+})<br>+<br>+/* Terra2 - PPCC table defined by mainboard for method PPCC */<br>+Name (PPT2, Package ()<br>+{<br>+ 0x2, /* Revision */<br>+ Package () { /* Power Limit 1 */<br>+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */<br>+ 1600, /* PowerLimitMinimum */<br>+ 10000, /* PowerLimitMaximum */<br>+ 1000, /* TimeWindowMinimum */<br>+ 1000, /* TimeWindowMaximum */<br>+ 200 /* StepSize */<br>+ },<br>+ Package () { /* Power Limit 2 */<br>+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */<br>+ 8000, /* PowerLimitMinimum */<br>+ 8000, /* PowerLimitMaximum */<br>+ 1000, /* TimeWindowMinimum */<br>+ 1000, /* TimeWindowMaximum */<br>+ 1000 /* StepSize */<br>+ }<br>+})<br>+<br>+/* Terra3 - PPCC table defined by mainboard for method PPCC */<br>+Name (PPT3, Package ()<br>+{<br>+ 0x2, /* Revision */<br>+ Package () { /* Power Limit 1 */<br>+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */<br>+ 1600, /* PowerLimitMinimum */<br>+ 10000, /* PowerLimitMaximum */<br>+ 1000, /* TimeWindowMinimum */<br>+ 1000, /* TimeWindowMaximum */<br>+ 200 /* StepSize */<br>+ },<br>+ Package () { /* Power Limit 2 */<br>+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */<br>+ 8000, /* PowerLimitMinimum */<br>+ 8000, /* PowerLimitMaximum */<br>+ 1000, /* TimeWindowMinimum */<br>+ 1000, /* TimeWindowMaximum */<br>+ 1000 /* StepSize */<br>+ }<br>+})<br>+<br>+Device (DPTF)<br>+{<br>+ Name (_HID, EISAID ("INT3400"))<br>+ Name (_UID, 0)<br>+<br>+ Name (IDSP, Package()<br>+ {<br>+ /* DPPM Passive Policy 1.0 */<br>+ ToUUID ("42A441D6-AE6A-462B-A84B-4A8CE79027D3"),<br>+<br>+ /* DPPM Critical Policy */<br>+ ToUUID ("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"),<br>+<br>+ /* DPPM Cooling Policy */<br>+ ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"),<br>+ })<br>+<br>+ Method (_STA)<br>+ {<br>+ If (LEqual (\DPTE, One)) {<br>+ Return (0xF)<br>+ } Else {<br>+ Return (0x0)<br>+ }<br>+ }<br>+<br>+ /*<br>+ * Arg0: Buffer containing UUID<br>+ * Arg1: Integer containing Revision ID of buffer format<br>+ * Arg2: Integer containing count of entries in Arg3<br>+ * Arg3: Buffer containing list of DWORD capabilities<br>+ * Return: Buffer containing list of DWORD capabilities<br>+ */<br>+ Method (_OSC, 4, Serialized)<br>+ {<br>+ /* Check for Passive Policy UUID */<br>+ If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) {<br>+ /* Initialize Thermal Devices */<br>+ ^TINI ()<br>+<br>+#ifdef DPTF_ENABLE_CHARGER<br>+ /* Initialize Charger Device */<br>+ ^TCHG.INIT ()<br>+#endif<br>+ }<br>+<br>+ Return (Arg3)<br>+ }<br>+<br>+ /* Priority based _TRT */<br>+ Name (TRTR, 1)<br>+<br>+ /* Return TRT table defined by Terra2 or Terra3 mainboard */<br>+ Method (_TRT)<br>+ {<br>+ If (Lequal(\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Return (\_SB.TRT2)<br>+ } Else {<br>+ Return (\_SB.TRT3)<br>+ }<br>+ }<br>+<br>+ /* Convert from Degrees C to 1/10 Kelvin for ACPI */<br>+ Method (CTOK, 1) {<br>+ /* 10th of Degrees C */<br>+ Multiply (Arg0, 10, Local0)<br>+<br>+ /* Convert to Kelvin */<br>+ Add (Local0, 2732, Local0)<br>+<br>+ Return (Local0)<br>+ }<br>+<br>+ /* Include Thermal Participants */<br>+ #include "thermal.asl"<br>+<br>+#ifdef DPTF_ENABLE_CHARGER<br>+ /* Include Charger Participant */<br>+ #include "charger.asl"<br>+#endif<br>+}<br>+<br>diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl<br>new file mode 100644<br>index 0000000..32bdbfb<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/mainboard.asl<br>@@ -0,0 +1,30 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Matt DeVillier<br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* Elan trackpad */<br>+#include <acpi/trackpad_elan.asl><br>+<br>+/* Realtek audio codec */<br>+#include <acpi/codec_realtek.asl><br>+<br>+Scope (\_SB)<br>+{<br>+ Method (GPID, 0, Serialized) // GPID: Get Project ID for Terra2/Terra3<br>+ {<br>+ And( ShiftRight (\BDID, 3, Local0), 0x01, Local0)<br>+ Return (Local0)<br>+ }<br>+}<br>diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl<br>new file mode 100644<br>index 0000000..6879076<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/thermal.asl<br>@@ -0,0 +1,255 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2012 Google Inc.<br>+ * Copyright (C) 2105 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* Thermal Threshold Event Handler */<br>+Method (TEVT, 1, NotSerialized)<br>+{<br>+ Store (ToInteger (Arg0), Local0)<br>+<br>+#ifdef DPTF_TSR0_SENSOR_ID<br>+ If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) {<br>+ Notify (^TSR0, 0x90)<br>+ }<br>+#endif<br>+#ifdef DPTF_TSR1_SENSOR_ID<br>+ If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) {<br>+ Notify (^TSR1, 0x90)<br>+ }<br>+#endif<br>+#ifdef DPTF_TSR2_SENSOR_ID<br>+ If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) {<br>+ Notify (^TSR2, 0x90)<br>+ }<br>+#endif<br>+}<br>+<br>+/* Thermal device initialization - Disable Aux Trip Points */<br>+Method (TINI)<br>+{<br>+#ifdef DPTF_TSR0_SENSOR_ID<br>+ ^TSR0.PATD ()<br>+#endif<br>+#ifdef DPTF_TSR1_SENSOR_ID<br>+ ^TSR1.PATD ()<br>+#endif<br>+#ifdef DPTF_TSR2_SENSOR_ID<br>+ ^TSR2.PATD ()<br>+#endif<br>+}<br>+<br>+#ifdef DPTF_TSR0_SENSOR_ID<br>+Device (TSR0)<br>+{<br>+ Name (_HID, EISAID ("INT3403"))<br>+ Name (_UID, 1)<br>+ Name (PTYP, 0x03)<br>+ Name (TMPI, DPTF_TSR0_SENSOR_ID)<br>+ Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME))<br>+ Name (GTSH, 20) /* 2 degree hysteresis */<br>+<br>+ Method (_STA)<br>+ {<br>+ If (LEqual (\DPTE, One)) {<br>+ Return (0xF)<br>+ } Else {<br>+ Return (0x0)<br>+ }<br>+ }<br>+<br>+ Method (_TMP, 0, Serialized)<br>+ {<br>+ Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))<br>+ }<br>+<br>+ /* Return passive thermal point defined by Terra2 or Terra3 mainboard */<br>+ Method (_PSV)<br>+ {<br>+ If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Return (CTOK (DPTF_TERRA2_TSR0_PASSIVE))<br>+ } Else {<br>+ Return (CTOK (DPTF_TERRA3_TSR0_PASSIVE))<br>+ }<br>+ }<br>+<br>+ /* Return critical thermal point defined by Terra2 or Terra3 mainboard */<br>+ Method (_CRT)<br>+ {<br>+ If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Return (CTOK (DPTF_TERRA2_TSR0_CRITICAL))<br>+ } Else {<br>+ Return (CTOK (DPTF_TERRA3_TSR0_CRITICAL))<br>+ }<br>+ }<br>+<br>+ Name (PATC, 2)<br>+<br>+ /* Set Aux Trip Point */<br>+ Method (PAT0, 1, Serialized)<br>+ {<br>+ \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)<br>+ }<br>+<br>+ /* Set Aux Trip Point */<br>+ Method (PAT1, 1, Serialized)<br>+ {<br>+ \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)<br>+ }<br>+<br>+ /* Disable Aux Trip Point */<br>+ Method (PATD, 0, Serialized)<br>+ {<br>+ \_SB.PCI0.LPCB.EC0.PATD (TMPI)<br>+ }<br>+}<br>+#endif<br>+<br>+#ifdef DPTF_TSR1_SENSOR_ID<br>+Device (TSR1)<br>+{<br>+ Name (_HID, EISAID ("INT3403"))<br>+ Name (_UID, 2)<br>+ Name (PTYP, 0x03)<br>+ Name (TMPI, DPTF_TSR1_SENSOR_ID)<br>+ Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME))<br>+ Name (GTSH, 20) /* 2 degree hysteresis */<br>+<br>+ Method (_STA)<br>+ {<br>+ If (LEqual (\DPTE, One)) {<br>+ Return (0xF)<br>+ } Else {<br>+ Return (0x0)<br>+ }<br>+ }<br>+<br>+ Method (_TMP, 0, Serialized)<br>+ {<br>+ Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))<br>+ }<br>+<br>+ /* Return passive thermal point defined by Terra2 or Terra3 mainboard */<br>+ Method (_PSV)<br>+ {<br>+ If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Return (CTOK (DPTF_TERRA2_TSR1_PASSIVE))<br>+ } Else {<br>+ Return (CTOK (DPTF_TERRA3_TSR1_PASSIVE))<br>+ }<br>+ }<br>+<br>+ /* Return critical thermal point defined by Terra2 or Terra3 mainboard */<br>+ Method (_CRT)<br>+ {<br>+ If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Return (CTOK (DPTF_TERRA2_TSR1_CRITICAL))<br>+ } Else {<br>+ Return (CTOK (DPTF_TERRA3_TSR1_CRITICAL))<br>+ }<br>+ }<br>+<br>+ Name (PATC, 2)<br>+<br>+ /* Set Aux Trip Point */<br>+ Method (PAT0, 1, Serialized)<br>+ {<br>+ \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)<br>+ }<br>+<br>+ /* Set Aux Trip Point */<br>+ Method (PAT1, 1, Serialized)<br>+ {<br>+ \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)<br>+ }<br>+<br>+ /* Disable Aux Trip Point */<br>+ Method (PATD, 0, Serialized)<br>+ {<br>+ \_SB.PCI0.LPCB.EC0.PATD (TMPI)<br>+ }<br>+}<br>+#endif<br>+<br>+#ifdef DPTF_TSR2_SENSOR_ID<br>+Device (TSR2)<br>+{<br>+ Name (_HID, EISAID ("INT3403"))<br>+ Name (_UID, 3)<br>+ Name (PTYP, 0x03)<br>+ Name (TMPI, DPTF_TSR2_SENSOR_ID)<br>+ Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME))<br>+ Name (GTSH, 20) /* 2 degree hysteresis */<br>+<br>+ Method (_STA)<br>+ {<br>+ If (LEqual (\DPTE, One)) {<br>+ Return (0xF)<br>+ } Else {<br>+ Return (0x0)<br>+ }<br>+ }<br>+<br>+ Method (_TMP, 0, Serialized)<br>+ {<br>+ Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI))<br>+ }<br>+<br>+ /* Return passive thermal point defined by Terra2 or Terra3 mainboard */<br>+ Method (_PSV)<br>+ {<br>+ If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Return (CTOK (DPTF_TERRA2_TSR2_PASSIVE))<br>+ } Else {<br>+ Return (CTOK (DPTF_TERRA3_TSR2_PASSIVE))<br>+ }<br>+ }<br>+<br>+ /* Return critical thermal point defined by Terra2 or Terra3 mainboard */<br>+ Method (_CRT)<br>+ {<br>+ If (LEqual (\_SB.GPID, TERRA2_PROJECT_ID))<br>+ {<br>+ Return (CTOK (DPTF_TERRA2_TSR2_CRITICAL))<br>+ } Else {<br>+ Return (CTOK (DPTF_TERRA3_TSR2_CRITICAL))<br>+ }<br>+ }<br>+<br>+ Name (PATC, 2)<br>+<br>+ /* Set Aux Trip Point */<br>+ Method (PAT0, 1, Serialized)<br>+ {<br>+ \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0)<br>+ }<br>+<br>+ /* Set Aux Trip Point */<br>+ Method (PAT1, 1, Serialized)<br>+ {<br>+ \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0)<br>+ }<br>+<br>+ /* Disable Aux Trip Point */<br>+ Method (PATD, 0, Serialized)<br>+ {<br>+ \_SB.PCI0.LPCB.EC0.PATD (TMPI)<br>+ }<br>+}<br>+#endif<br>diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h b/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h<br>new file mode 100644<br>index 0000000..d03e4a6<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/include/variant/onboard.h<br>@@ -0,0 +1,66 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Google Inc.<br>+ * Copyright (C) 2015 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef ONBOARD_H<br>+#define ONBOARD_H<br>+<br>+#include <mainboard/google/cyan/irqroute.h><br>+<br>+/*<br>+ * Calculation of gpio based irq.<br>+ * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE<br>+ * Max direct irq (MAX_DIRECT_IRQ) is 114.<br>+ * Size of gpio banks are<br>+ * GPSW_SIZE = 98<br>+ * GPNC_SIZE = 73<br>+ * GPEC_SIZE = 27<br>+ * GPSE_SIZE = 86<br>+ */<br>+<br>+/* KBD: Gpio index in N bank */<br>+#define BOARD_I8042_GPIO_INDEX 17<br>+/* Audio: Gpio index in SW bank */<br>+#define JACK_DETECT_GPIO_INDEX 95<br>+/* SCI: Gpio index in N bank */<br>+#define BOARD_SCI_GPIO_INDEX 15<br>+/* Trackpad: Gpio index in N bank */<br>+#define BOARD_TRACKPAD_GPIO_INDEX 18<br>+<br>+#define BOARD_TRACKPAD_NAME "trackpad"<br>+#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)<br>+#define BOARD_TRACKPAD_I2C_BUS 5<br>+#define BOARD_TRACKPAD_I2C_ADDR 0x15<br>+<br>+/* SD CARD gpio */<br>+#define SDCARD_CD 81<br>+<br>+#define AUDIO_CODEC_HID "10EC5650"<br>+#define AUDIO_CODEC_CID "10EC5650"<br>+#define AUDIO_CODEC_DDN "RTEK Codec Controller "<br>+#define AUDIO_CODEC_I2C_ADDR 0x1A<br>+<br>+#define TERRA2_PROJECT_ID 0x00<br>+<br>+#define DPTF_TERRA2_CPU_PASSIVE 80<br>+#define DPTF_TERRA2_CPU_CRITICAL 90<br>+#define DPTF_TERRA3_CPU_PASSIVE 80<br>+#define DPTF_TERRA3_CPU_CRITICAL 90<br>+<br>+/* I2C data hold time */<br>+#define BOARD_I2C5_DATA_HOLD_TIME 0x1E<br>+#define BOARD_I2C6_DATA_HOLD_TIME 0x1E<br>+<br>+#endif<br>diff --git a/src/mainboard/google/cyan/variants/terra/ramstage.c b/src/mainboard/google/cyan/variants/terra/ramstage.c<br>new file mode 100644<br>index 0000000..6ef4360<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/ramstage.c<br>@@ -0,0 +1,71 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Intel Corporation<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/ramstage.h><br>+#include <boardid.h><br>+#include <variant/onboard.h><br>+<br>+void mainboard_silicon_init_params(SILICON_INIT_UPD *params)<br>+{<br>+ uint8_t boardid = 0;<br>+ uint8_t projectid = 0;<br>+<br>+ boardid = board_id();<br>+ projectid = (boardid >> 3) & 0x01;<br>+<br>+ if (projectid == TERRA2_PROJECT_ID) {<br>+ params->Usb2Port0PerPortPeTxiSet = 7;<br>+ params->Usb2Port0PerPortTxiSet = 6;<br>+ params->Usb2Port0IUsbTxEmphasisEn = 3;<br>+ params->Usb2Port0PerPortTxPeHalf = 1;<br>+ params->Usb2Port1PerPortPeTxiSet = 7;<br>+ params->Usb2Port1PerPortTxiSet = 6;<br>+ params->Usb2Port1IUsbTxEmphasisEn = 3;<br>+ params->Usb2Port1PerPortTxPeHalf = 1;<br>+ params->Usb2Port2PerPortPeTxiSet = 7;<br>+ params->Usb2Port2PerPortTxiSet = 6;<br>+ params->Usb2Port2IUsbTxEmphasisEn = 3;<br>+ params->Usb2Port2PerPortTxPeHalf = 1;<br>+ params->Usb2Port3PerPortPeTxiSet = 7;<br>+ params->Usb2Port3PerPortTxiSet = 6;<br>+ params->Usb2Port3IUsbTxEmphasisEn = 3;<br>+ params->Usb2Port3PerPortTxPeHalf = 1;<br>+ params->Usb2Port4PerPortPeTxiSet = 7;<br>+ params->Usb2Port4PerPortTxiSet = 6;<br>+ params->Usb2Port4IUsbTxEmphasisEn = 3;<br>+ params->Usb2Port4PerPortTxPeHalf = 1;<br>+ } else {<br>+ params->Usb2Port0PerPortPeTxiSet = 7;<br>+ params->Usb2Port0PerPortTxiSet = 6;<br>+ params->Usb2Port0IUsbTxEmphasisEn = 3;<br>+ params->Usb2Port0PerPortTxPeHalf = 1;<br>+ params->Usb2Port1PerPortPeTxiSet = 7;<br>+ params->Usb2Port1PerPortTxiSet = 6;<br>+ params->Usb2Port1IUsbTxEmphasisEn = 3;<br>+ params->Usb2Port1PerPortTxPeHalf = 1;<br>+ params->Usb2Port2PerPortPeTxiSet = 7;<br>+ params->Usb2Port2PerPortTxiSet = 3;<br>+ params->Usb2Port2IUsbTxEmphasisEn = 2;<br>+ params->Usb2Port2PerPortTxPeHalf = 1;<br>+ params->Usb2Port3PerPortPeTxiSet = 7;<br>+ params->Usb2Port3PerPortTxiSet = 6;<br>+ params->Usb2Port3IUsbTxEmphasisEn = 3;<br>+ params->Usb2Port3PerPortTxPeHalf = 1;<br>+ params->Usb2Port4PerPortPeTxiSet = 7;<br>+ params->Usb2Port4PerPortTxiSet = 3;<br>+ params->Usb2Port4IUsbTxEmphasisEn = 2;<br>+ params->Usb2Port4PerPortTxPeHalf = 1;<br>+ }<br>+}<br>diff --git a/src/mainboard/google/cyan/variants/terra/romstage.c b/src/mainboard/google/cyan/variants/terra/romstage.c<br>new file mode 100644<br>index 0000000..e670461<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/romstage.c<br>@@ -0,0 +1,54 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Google Inc.<br>+ * Copyright (C) 2015 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/romstage.h><br>+#include <chip.h><br>+#include <mainboard/google/cyan/spd/spd_util.h><br>+<br>+void mainboard_memory_init_params(struct romstage_params *params,<br>+ MEMORY_INIT_UPD *memory_params)<br>+{<br>+ int ram_id = get_ramid();<br>+<br>+ /*<br>+ * RAMID = 3 - 2GiB Micron MT52L256M32D1PF-107<br>+ * RAMID = 11 - 4GiB Micron MT52L256M32D1PF-107<br>+ */<br>+ if (ram_id == 3 || ram_id == 11) {<br>+<br>+ /*<br>+ * For new micron part, it requires read/receive<br>+ * enable training before sending cmds to get MR8.<br>+ * To override dram geometry settings as below:<br>+ *<br>+ * PcdDramWidth = x32<br>+ * PcdDramDensity = 8Gb<br>+ * PcdDualRankDram = disable<br>+ */<br>+ memory_params->PcdRxOdtLimitChannel0 = 1;<br>+ memory_params->PcdRxOdtLimitChannel1 = 1;<br>+ memory_params->PcdDisableAutoDetectDram = 1;<br>+ memory_params->PcdDramWidth = 2;<br>+ memory_params->PcdDramDensity = 3;<br>+ memory_params->PcdDualRankDram = 0;<br>+ }<br>+<br>+ /* Update SPD data */<br>+ memory_params->PcdMemoryTypeEnable = MEM_LPDDR3;<br>+ memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0;<br>+ memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config;<br>+ memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config;<br>+}<br>diff --git a/src/mainboard/google/cyan/variants/terra/spd_util.c b/src/mainboard/google/cyan/variants/terra/spd_util.c<br>new file mode 100644<br>index 0000000..7b4629d<br>--- /dev/null<br>+++ b/src/mainboard/google/cyan/variants/terra/spd_util.c<br>@@ -0,0 +1,60 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Google Inc.<br>+ * Copyright (C) 2015 Intel Corp.<br>+ * Copyright (C) 2017 Matt DeVillier<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <mainboard/google/cyan/spd/spd_util.h><br>+<br>+/*<br>+ * RAMID3 -1: Dual channel SKU, 0: Single channel SKU<br>+ * 0b0010 - 2GiB total - 1 x 2GiB Micron EDF8132A3MA-GD-F-R 1600MHz<br>+ * 0b0011 - 2GiB total - 1 x 2GiB Micron MT52L256M32D1PF-107WT 1866MHz<br>+ * 0b0100 - 2GiB total - 1 x 2GiB Samsung K4E8E304EE-EGCE 1600MHz<br>+ * 0b0101 - 2GiB total - 1 x 2GiB Samsung K4E8E324EB-EGCF 1866MHz<br>+ *<br>+ * 0b1010 - 4GiB total - 2 x 2GiB Micron EDF8132A3MA-GD-F-R 1600MHz<br>+ * 0b1011 - 4GiB total - 2 x 2GiB Micron MT52L256M32D1PF-107WT 1866MHz<br>+ * 0b1100 - 4GiB total - 2 x 2GiB Samsung K4E8E304EE-EGCE 1600MHz<br>+ * 0b1101 - 4GiB total - 2 x 2GiB Samsung K4E8E324EB-EGCF 1866MHz<br>+ */<br>+<br>+int get_variant_spd_index(int ram_id, int *dual)<br>+{<br>+ int spd_index = ram_id & 0x03;<br>+<br>+ /* Determine if single or dual channel memory system */<br>+ /* RAMID3 is deterministic for terra */<br>+ *dual = ((ram_id > 3) & 0x1) ? 1 : 0;<br>+<br>+ /* Display the RAM type */<br>+ printk(BIOS_DEBUG, dual ? "4GiB " : "2GiB ");<br>+ switch (spd_index) {<br>+ case 0:<br>+ printk(BIOS_DEBUG, "Samsung K4E8E304EE-EGCE 1600MHz\n");<br>+ break;<br>+ case 1:<br>+ printk(BIOS_DEBUG, "Samsung K4E8E324EB-EGCF 1866MHz\n");<br>+ break;<br>+ case 2:<br>+ printk(BIOS_DEBUG, "Micron EDF8132A3MA-GD-F-R 1600MHz\n");<br>+ break;<br>+ case 3:<br>+ printk(BIOS_DEBUG, "Micron MT52L256M32D1PF-107WT 1866MHz\n");<br>+ break;<br>+ }<br>+<br>+ return spd_index;<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21570">change 21570</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21570"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib2682eda15a989f2ec20c78317561f5b6a97483a </div>
<div style="display:none"> Gerrit-Change-Number: 21570 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>