<p>frank vibrans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21564">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd/stoneyridge: PSP SMM implementation (WIP)<br><br>Add end of post bios to psp smm mailbox path.<br>Add psp to bios smm mailbox path.<br>Test code included - will be removed later.<br><br>Change-Id: Id747289b62e3d450a901401eafa9ac243e6aa25d<br>Signed-off-by: Frank Vibrans <frank.vibrans@scarletltd.com><br><br>soc/amd/stoneyridge: BIOS-PSP SMM interface framework<br><br>Add end-of-post BIOS-to-PSP smm mailbox path.<br>Add PSP-to-BIOS smm mailbox path.<br>Test code removed.<br>SPI access code not yet in place.<br><br>Change-Id: I88d45b73263369917b67a2e586f44e331bb7028b<br>Signed-off-by: Frank Vibrans <frank.vibrans@scarletltd.com><br>---<br>M src/soc/amd/common/block/include/amdblocks/psp.h<br>A src/soc/amd/common/block/include/amdblocks/psp_get_mbox.h<br>A src/soc/amd/common/block/include/amdblocks/psp_init.h<br>A src/soc/amd/common/block/include/amdblocks/psp_smm.h<br>M src/soc/amd/common/block/psp/Makefile.inc<br>A src/soc/amd/common/block/psp/p2cmbox.c<br>M src/soc/amd/common/block/psp/psp.c<br>A src/soc/amd/common/block/psp/psp_get_mbox.c<br>A src/soc/amd/common/block/psp/psp_init.c<br>A src/soc/amd/common/block/psp/psp_init_smm.c<br>A src/soc/amd/common/block/psp/psp_smm_get_mbox.c<br>M src/soc/amd/stoneyridge/cpu.c<br>M src/soc/amd/stoneyridge/include/soc/smi.h<br>M src/soc/amd/stoneyridge/smihandler.c<br>14 files changed, 737 insertions(+), 22 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21564/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h<br>index 42b9fb7..36f743c 100644<br>--- a/src/soc/amd/common/block/include/amdblocks/psp.h<br>+++ b/src/soc/amd/common/block/include/amdblocks/psp.h<br>@@ -18,8 +18,24 @@<br> <br> #include <stdint.h><br> #include <compiler.h><br>-#include <Porting.h><br>-#include <Proc/Psp/PspBaseLib/PspBaseLib.h><br>+<br>+/* This block MUST match the file<br>+ * src/vendorcode/amd/pi/00670f00/Proc/Psp/PspBaseLib/PspBaseLib.h */<br>+#define PSP_PCI_SEG 0x00 ///< PSP Seg address<br>+#define PSP_PCI_BUS 0x00 ///< PSP Bus address<br>+#define PSP_PCI_DEV 0x08 ///< PSP Device address<br>+#define PSP_PCI_FN 0x00 ///< PSP Fn address<br>+#define PSP_PCI_BDA ((PSP_PCI_DEV << 11) + (PSP_PCI_FN << 8))<br>+#define GET_PSP_PCI_ADDR(Offset) MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset)<br>+<br>+#define PSP_PCI_DEVID_REG 0x00 ///< DevId<br>+#define PSP_PCI_CMD_REG 0x04 ///< CmdReg<br>+#define PSP_PCI_BAR1_REG 0x18 ///< Pci Bar1<br>+#define PSP_PCI_BAR3_REG 0x20 ///< Pci Bar3<br>+#define PSP_PCI_MIRRORCTRL1_REG 0x44 ///< PSP Mirror Reg Ctrl 1<br>+#define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr<br>+#define PSP_PCI_HTMSICAP_REG 0x5C ///< HT MSI Capability<br>+/* End of PspBaseLib.h matching block */<br> <br> /* x86 to PSP commands */<br> #define MBOX_BIOS_CMD_DRAM_INFO 0x01<br>@@ -70,6 +86,37 @@<br> struct mbox_buffer_header header;<br> } __attribute__((packed,aligned(32)));<br> <br>+/* Definitions for MboxBiosCmdSmmInfo buffer - command 0x2 */<br>+#define PSP_SMMINFO_TYPE_IO 0<br>+#define PSP_SMMINFO_TYPE_MMIO 1<br>+#define PSP_SMMINFO_TYPE_PCI 2<br>+<br>+#define PSP_SMMINFO_WIDTH_BYTE 0<br>+#define PSP_SMMINFO_WIDTH_WORD 1<br>+#define PSP_SMMINFO_WIDTH_DWORD 2<br>+#define PSP_SMMINFO_WIDTH_QWORD 3<br>+<br>+struct smm_trigger_info {<br>+ u64 address;<br>+ u32 address_type;<br>+ u32 value_width;<br>+ u32 value_and_mask;<br>+ u32 value_or_mask;<br>+} __attribute__((packed,aligned(32)));<br>+<br>+struct smm_req_buffer {<br>+ u64 smm_base;<br>+ u64 smm_length;<br>+ u64 psp_smm_data_base;<br>+ u64 psp_smm_data_length;<br>+ struct smm_trigger_info smm_trig_info;<br>+} __attribute__((packed,aligned(32)));<br>+<br>+struct mbox_smm_info_buffer {<br>+ struct mbox_buffer_header header;<br>+ struct smm_req_buffer req;<br>+} __attribute__((packed,aligned(32)));<br>+<br> /* send_psp_command() error codes */<br> #define PSPSTS_SUCCESS 0<br> #define PSPSTS_NOBASE 1<br>@@ -93,5 +140,7 @@<br> <br> /* BIOS-to-PSP functions return 0 if successful, else negative value */<br> int psp_notify_dram(void);<br>+int psp_notify_smm_info(uintptr_t base, u64 length, uintptr_t psp_data_base,<br>+ u64 psp_data_length, struct smm_trigger_info *smm_trig_info);<br> <br> #endif /* __AMD_PSP_H__ */<br>diff --git a/src/soc/amd/common/block/include/amdblocks/psp_get_mbox.h b/src/soc/amd/common/block/include/amdblocks/psp_get_mbox.h<br>new file mode 100644<br>index 0000000..1dc885b<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/include/amdblocks/psp_get_mbox.h<br>@@ -0,0 +1,22 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef AMD_PSP_GET_MBOX_H<br>+#define AMD_PSP_GET_MBOX_H<br>+<br>+struct psp_mbox *get_mbox_address(void);<br>+void PSPProgBar3Msr(void);<br>+<br>+#endif /* AMD_PSP_GET_MBOX_H */<br>diff --git a/src/soc/amd/common/block/include/amdblocks/psp_init.h b/src/soc/amd/common/block/include/amdblocks/psp_init.h<br>new file mode 100644<br>index 0000000..3612cd5<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/include/amdblocks/psp_init.h<br>@@ -0,0 +1,27 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __AMD_PSP_INIT_H__<br>+#define __AMD_PSP_INIT_H__<br>+<br>+/* Trap 0xfed80e00 memory read, no override */<br>+#define MEMTRAP0_CONFIG 0xfed80e00<br>+<br>+void psp_initialize(void);<br>+//void enable_smi_generation(void);<br>+void disable_smi_generation(void);<br>+void clear_smi_status(void);<br>+<br>+#endif /* __AMD_PSP_INIT_H__ */<br>diff --git a/src/soc/amd/common/block/include/amdblocks/psp_smm.h b/src/soc/amd/common/block/include/amdblocks/psp_smm.h<br>new file mode 100644<br>index 0000000..1a96c10<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/include/amdblocks/psp_smm.h<br>@@ -0,0 +1,156 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __AMD_PSP_SMM_H__<br>+#define __AMD_PSP_SMM_H__<br>+<br>+#include <stdint.h><br>+<br>+/* PSP Directory Entry Type Encodings */<br>+#define TYPE_AMD_PUBKEY 0x00<br>+#define TYPE_BOOT_LOAD_FW 0x01<br>+#define TYPE_SECURE_OS_FW 0x02<br>+#define TYPE_REC_BOOT_LDR 0x03<br>+#define TYPE_NON_VOL_DATA 0x04<br>+#define TYPE_SIGNED_OEM_BIOS_PUBKEY 0x05<br>+#define TYPE_BIOS_RTM_VOLUME 0x06<br>+#define TYPE_BIOS_RTM_OEMSIG 0x07<br>+#define TYPE_SMU_OFFCHIP_FW 0x08<br>+#define TYPE_AMD_SEC_DEBKEY 0x09<br>+#define TYPE_SIGNED_SEC_OS_PUBKEY 0x0a<br>+#define TYPE_SOFT_FUSE_CHAIN 0x0b<br>+#define TYPE_LOADED_TPM96_TR_BINARY 0x0c<br>+#define TYPE_SIGNED_TR_PUBKEY 0x0d<br>+<br>+#define TYPE_S3_MEM_BOOT_LDR 0x10<br>+#define TYPE_SMU_OFFCHIP_FW2 0x12<br>+#define TYPE_LOADED_TPM122_TR_BINARY 0x14<br>+#define TYPE_S3_DATA_BLOB_ENTRY_PTR 0x1a<br>+#define TYPE_SW_CONFIG_DATA_BLK 0x5f<br>+<br>+#define TYPE_OEM_TA 0x80<br>+#define TYPE_SIGNED_OEM_TA_PUBKEY 0x81<br>+<br>+#define PSP_DATA_BLK_SIZE (8 * 1024) + 32<br>+<br>+struct psp_embedded_fw {<br>+ u32 signature;<br>+ u32 reserved1;<br>+ u32 imc_fw_entry;<br>+ u32 xhci_fw_entry;<br>+ u32 psp_dir_table;<br>+ u32 new_psp_dir_table;<br>+ u32 reserved2[10];<br>+ u8 spi_mode;<br>+ u8 spi_read_spd;<br>+ u16 reserved3;<br>+} __attribute__ ((packed));<br>+<br>+struct p2cmbox_dir_tbl_hdr {<br>+ u32 cookie;<br>+ u32 chksum;<br>+ u32 num_entries;<br>+ u32 reserved;<br>+} __attribute__ ((packed));<br>+<br>+struct p2cmbox_dir_tbl_entry {<br>+ u32 type;<br>+ u32 size;<br>+ u64 loc_val;<br>+} __attribute__ ((packed));<br>+<br>+/* PSP to BIOS commands */<br>+#define SPI_GET_ATTRIBUTE 0x81<br>+#define SPI_SET_ATTRIBUTE 0x82 /* Not currently supported */<br>+#define SPI_GET_BLOCKSIZE 0x83<br>+#define SPI_READ_FW_VOLUME 0x84<br>+#define SPI_READ_WR_VOLUME 0x85<br>+#define SPI_ERASE_FW_VOLUME 0x86<br>+<br>+struct psp_smm_mailbox {<br>+ u8 buffer[PSP_DATA_BLK_SIZE];<br>+} __attribute__ ((packed,aligned (32)));<br>+<br>+struct spi_info_req {<br>+ u64 lba;<br>+ u64 blocksize;<br>+ u64 number_of_blocks;<br>+} __attribute__ ((packed));<br>+<br>+struct spi_rw_fw_vol {<br>+ u64 lba;<br>+ u64 offset;<br>+ u64 number_of_bytes;<br>+ u8 *buffer;<br>+} __attribute__ ((packed));<br>+<br>+struct spi_erase_fw_vol {<br>+ u64 lba;<br>+ u64 number_of_blocks;<br>+} __attribute__ ((packed));<br>+<br>+#define PSP_CMD_STATUS_CMD_READY (1 << 31)<br>+#define PSP_CMD_STATUS_CHKSUM_ENABLE (1 << 8)<br>+struct psp_smi_mbox_status {<br>+ u32 checksum_value:8;<br>+ u32 checksum_enable:1;<br>+ u32 reserved:22;<br>+ u32 command_ready:1;<br>+} __attribute__ ((packed));<br>+<br>+struct psp_smi_mbox_buffer_header {<br>+ u32 total_size;<br>+ u32 status;<br>+} __attribute__ ((packed));<br>+<br>+struct psp_smm_mbox {<br>+ u32 command;<br>+ struct psp_smi_mbox_status status;<br>+ u8 buffer[];<br>+} __attribute__ ((packed));<br>+<br>+/* command specific command/response buffer layouts */<br>+/* SPI_GET_ATTRIBUTE (0x81) and SPI_SET_ATTRIBUTE (0x82) */<br>+struct spi_attrib {<br>+ struct psp_smi_mbox_buffer_header header;<br>+ u64 attribute;<br>+} __attribute__ ((packed));<br>+<br>+/* SPI_GET_BLOCKSIZE (0x83) */<br>+struct spi_blocksize {<br>+ struct psp_smi_mbox_buffer_header header;<br>+ struct spi_info_req block_data;<br>+} __attribute__ ((packed));<br>+<br>+/* SPI_READ_FW_VOLUME (0x84) and SPI_WRITE_FW_VOLUME (0x85) */<br>+struct spi_fw_vol {<br>+ struct psp_smi_mbox_buffer_header header;<br>+ struct spi_rw_fw_vol data;<br>+} __attribute__ ((packed));<br>+<br>+/* SPI_ERASE_FW_VOLUME (0x86) */<br>+struct spi_erase_req {<br>+ struct psp_smi_mbox_buffer_header header;<br>+ struct spi_erase_fw_vol block_data;<br>+} __attribute__ ((packed));<br>+<br>+extern struct psp_smm_mailbox psp_smm_mbox;<br>+<br>+void psp_p2cmbox_init(u32 status);<br>+void psp_smm_init(u32 status);<br>+void psp_p2cmbox_event(u32 status);<br>+uint8_t test_checksum(u8 *start, u32 len);<br>+<br>+#endif /* __AMD_PSP_SMM_H__ */<br>diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc<br>index eebba16..9d314a0 100644<br>--- a/src/soc/amd/common/block/psp/Makefile.inc<br>+++ b/src/soc/amd/common/block/psp/Makefile.inc<br>@@ -1,2 +1,10 @@<br> romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c<br>+romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_get_mbox.c<br> ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c<br>+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_get_mbox.c<br>+ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_init.c<br>+<br>+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c<br>+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_init_smm.c<br>+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_smm_get_mbox.c<br>+smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += p2cmbox.c<br>diff --git a/src/soc/amd/common/block/psp/p2cmbox.c b/src/soc/amd/common/block/psp/p2cmbox.c<br>new file mode 100644<br>index 0000000..38a2574<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/psp/p2cmbox.c<br>@@ -0,0 +1,76 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <console/console.h><br>+#include <cpu/x86/msr.h><br>+#include <cpu/amd/amdfam15.h><br>+#include <amdblocks/psp.h><br>+#include <amdblocks/psp_smm.h><br>+#include <soc/smi.h><br>+<br>+struct psp_smm_mailbox psp_smm_mbox;<br>+<br>+uint8_t test_checksum(uint8_t *start, uint32_t len)<br>+{<br>+ uint8_t test_sum = 0;<br>+ uint32_t i;<br>+<br>+ for (i=0; i<len; i++) {<br>+ test_sum += *(uint8_t *)(start + i);<br>+ };<br>+<br>+ return test_sum;<br>+}<br>+<br>+void psp_p2cmbox_event(uint32_t status)<br>+{<br>+ /* Check for supported SMI */<br>+ if (!(status & SMISTAT4_FAKESMI_0))<br>+ return;<br>+<br>+ uintptr_t psp_data_base = (uintptr_t)&psp_smm_mbox;<br>+<br>+ /* Check if a command is ready */<br>+ uint32_t cmd_status = *(uint32_t *)(psp_data_base + 4);<br>+ if (!(cmd_status & PSP_CMD_STATUS_CMD_READY))<br>+ return;<br>+<br>+ /* Test checksum if necessary */<br>+ if (cmd_status & PSP_CMD_STATUS_CHKSUM_ENABLE) {<br>+ uint32_t length = *(uint32_t *)(psp_data_base + 8);<br>+ if (test_checksum((uint8_t *)psp_data_base, length))<br>+ return;<br>+ };<br>+<br>+ /* */<br>+ uint32_t psp_cmd = *(uint32_t *)psp_data_base;<br>+ switch (psp_cmd) {<br>+ case SPI_GET_ATTRIBUTE:<br>+ break;<br>+ /* case SPI_SET_ATTRIBUTE Not currently supported */<br>+ /* break; */<br>+ case SPI_GET_BLOCKSIZE:<br>+ break;<br>+ case SPI_READ_FW_VOLUME:<br>+ break;<br>+ case SPI_READ_WR_VOLUME:<br>+ break;<br>+ case SPI_ERASE_FW_VOLUME:<br>+ break;<br>+ default:<br>+ return;<br>+ }<br>+}<br>diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c<br>index d61a914..3b6ef5e 100644<br>--- a/src/soc/amd/common/block/psp/psp.c<br>+++ b/src/soc/amd/common/block/psp/psp.c<br>@@ -20,6 +20,7 @@<br> #include <device/pci_def.h><br> #include <console/console.h><br> #include <amdblocks/psp.h><br>+#include <amdblocks/psp_get_mbox.h><br> <br> static const char *psp_status_nobase = "error: PSP BAR3 not assigned";<br> static const char *psp_status_halted = "error: PSP in halted state";<br>@@ -47,24 +48,6 @@<br> default:<br> return psp_status_noerror;<br> }<br>-}<br>-<br>-static struct psp_mbox *get_mbox_address(void)<br>-{<br>- UINT32 base; /* UINT32 for compatibility with PspBaseLib */<br>- BOOLEAN bar3_status;<br>- uintptr_t baseptr;<br>-<br>- bar3_status = GetPspBar3Addr(&base);<br>- if (!bar3_status) {<br>- PspBarInitEarly();<br>- bar3_status = GetPspBar3Addr(&base);<br>- }<br>- if (!bar3_status)<br>- return NULL;<br>-<br>- baseptr = base;<br>- return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE);<br> }<br> <br> static u32 rd_mbox_sts(struct psp_mbox *mbox)<br>@@ -201,3 +184,32 @@<br> <br> return cmd_status;<br> }<br>+<br>+/*<br>+ * Inform the PSP of the systems System Management Mode settings.<br>+ */<br>+int psp_notify_smm_info(uintptr_t base, u64 length, uintptr_t psp_data_base,<br>+ u64 psp_data_length, struct smm_trigger_info *smm_trig_info)<br>+{<br>+ struct mbox_smm_info_buffer buffer;<br>+ int cmd_status;<br>+<br>+ printk(BIOS_DEBUG, "PSP: Notify SMM info... ");<br>+<br>+ buffer.header.size = sizeof(struct mbox_smm_info_buffer);<br>+ buffer.header.status = 0;<br>+ buffer.req.smm_base = base;<br>+ buffer.req.smm_length = length;<br>+ buffer.req.psp_smm_data_base = psp_data_base;<br>+ buffer.req.psp_smm_data_length = psp_data_length;<br>+ buffer.req.smm_trig_info = *smm_trig_info;<br>+<br>+ cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer);<br>+<br>+ if (cmd_status)<br>+ printk(BIOS_DEBUG, "%s\n", status_to_string(cmd_status));<br>+ else<br>+ printk(BIOS_DEBUG, "OK\n");<br>+<br>+ return cmd_status;<br>+}<br>diff --git a/src/soc/amd/common/block/psp/psp_get_mbox.c b/src/soc/amd/common/block/psp/psp_get_mbox.c<br>new file mode 100644<br>index 0000000..19812da<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/psp/psp_get_mbox.c<br>@@ -0,0 +1,53 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <Porting.h><br>+#include <device/pci_def.h><br>+#include <console/console.h><br>+#include <Proc/Psp/PspBaseLib/PspBaseLib.h><br>+#include <amdblocks/psp.h><br>+#include <amdblocks/psp_get_mbox.h><br>+<br>+struct psp_mbox *get_mbox_address(void)<br>+{<br>+ UINT32 base; /* UINT32 for compatibility with PspBaseLib */<br>+ BOOLEAN bar3_status;<br>+ uintptr_t baseptr;<br>+<br>+ bar3_status = GetPspBar3Addr(&base);<br>+ if (!bar3_status) {<br>+ PspBarInitEarly();<br>+ bar3_status = GetPspBar3Addr(&base);<br>+ }<br>+ if (!bar3_status)<br>+ return NULL;<br>+<br>+ baseptr = base;<br>+ return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE);<br>+}<br>+<br>+void PSPProgBar3Msr(void)<br>+{<br>+ UINT32 Bar3Addr;<br>+ UINT64 Tmp64;<br>+ <br>+ /* Get Bar3 Addr */<br>+ Bar3Addr = PspLibPciReadPspConfig(0x20);<br>+ Tmp64 = Bar3Addr;<br>+ printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64);<br>+ LibAmdMsrWrite(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL);<br>+ /* LibAmdMsrRead(PSP_MSR_PRIVATE_BLOCK_BAR, &Tmp64, NULL); */<br>+}<br>diff --git a/src/soc/amd/common/block/psp/psp_init.c b/src/soc/amd/common/block/psp/psp_init.c<br>new file mode 100644<br>index 0000000..dea7717<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/psp/psp_init.c<br>@@ -0,0 +1,78 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <console/console.h><br>+#include <cpu/x86/msr.h><br>+#include <soc/smi.h><br>+#include <amdblocks/psp.h><br>+#include <amdblocks/psp_init.h><br>+#include <amdblocks/psp_get_mbox.h><br>+<br>+/** Clear the EOS bit and disable SMI generation from southbridge */<br>+void disable_smi_generation(void)<br>+{<br>+ uint32_t reg = smi_read32(SMI_REG_SMITRIG0);<br>+ reg |= SMITRG0_SMIENB; /* Disable SMI generation */<br>+ reg &= ~SMITRG0_EOS; /* Clear EOS bit */<br>+ smi_write32(SMI_REG_SMITRIG0, reg);<br>+}<br>+<br>+/** Arbitrarily clear all SMI status by reading each status<br>+ register and writing the read data back into it.<br>+*/<br>+void clear_smi_status(void)<br>+{<br>+ uint32_t reg = smi_read32(SMI_REG_GPESTAT);<br>+ smi_write32(SMI_REG_GPESTAT, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT0);<br>+ smi_write32(SMI_REG_SMISTAT0, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT1);<br>+ smi_write32(SMI_REG_SMISTAT1, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT2);<br>+ smi_write32(SMI_REG_SMISTAT2, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT4);<br>+ smi_write32(SMI_REG_SMISTAT4, reg);<br>+}<br>+<br>+void psp_initialize(void)<br>+{<br>+ uint32_t reg;<br>+ uint32_t *mem_ptr = (uint32_t *)MEMTRAP0_CONFIG;<br>+<br>+ /* Required setup */<br>+ PSPProgBar3Msr();<br>+<br>+ disable_smi_generation();<br>+<br>+ /* Set up for trap on read because it is non-destructive */<br>+ smi_write32(SMI_REG_MEM_TRAP0, MEMTRAP0_CONFIG);<br>+<br>+ /* Enable the memory read trap */<br>+ reg = smi_read32(SMI_REG_SMICTRL9);<br>+ reg |= SMICTRL9_MTRAP_EN;<br>+ smi_write32(SMI_REG_SMICTRL9, reg);<br>+<br>+ clear_smi_status();<br>+<br>+ enable_smi_generation();<br>+<br>+ /* Trigger SMI that starts PSP SMM initialization*/<br>+ reg = *mem_ptr;<br>+}<br>diff --git a/src/soc/amd/common/block/psp/psp_init_smm.c b/src/soc/amd/common/block/psp/psp_init_smm.c<br>new file mode 100644<br>index 0000000..c69d071<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/psp/psp_init_smm.c<br>@@ -0,0 +1,70 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <console/console.h><br>+#include <cpu/x86/msr.h><br>+#include <cpu/amd/amdfam15.h><br>+#include <amdblocks/psp.h><br>+#include <amdblocks/psp_smm.h><br>+#include <soc/smi.h><br>+<br>+void psp_p2cmbox_init(uint32_t status)<br>+{<br>+ struct smm_trigger_info trig_info;<br>+<br>+ /* Have FakeSMI0 generate an SMI with status routed to SmiStatus4 */<br>+ uint32_t reg = smi_read32(SMI_REG_SMICTRL8);<br>+ reg |= SMICTRL8_FAKE0_SMI_EN;<br>+ smi_write32(SMI_REG_SMICTRL8, reg);<br>+<br>+ /* Determine MBoxBiosCmdSmmInfo message parameters */<br>+ /* SMI trigger information */<br>+ trig_info.address = (uintptr_t)(SMI_BASE + SMI_REG_SMITRIG0);<br>+ trig_info.address_type = PSP_SMMINFO_TYPE_MMIO;<br>+ trig_info.value_width = PSP_SMMINFO_WIDTH_WORD;<br>+ trig_info.value_and_mask = ~SMITRG0_FAKE0;<br>+ trig_info.value_or_mask = SMITRG0_FAKE0;<br>+<br>+ /* TSEG information */<br>+ msr_t msr = rdmsr(MSR_TSEG_BASE);<br>+ uintptr_t tseg_base = ((uint64_t)(msr.hi) << 32) | (uint64_t)(msr.lo);<br>+ msr = rdmsr(MSR_SMM_MASK);<br>+ /* The size mask extends from bit 17 to bit 47, but it is not<br>+ likely we will see a TSEG greater than 2GB, so we will cheat<br>+ in our math and ignore mask bits 32-47. */<br>+ uint64_t tseg_length = (uint64_t)(~(msr.lo)) + (uint64_t)1;<br>+<br>+ /* PSP SMM mailbox information */<br>+ uintptr_t psp_data_base = (uintptr_t)&psp_smm_mbox;<br>+ uint64_t psp_data_length = sizeof(psp_smm_mbox);<br>+<br>+ /* Now send the MBoxBiosCmdSmmInfo command to the PSP */<br>+ psp_notify_smm_info(tseg_base, tseg_length, psp_data_base,<br>+ psp_data_length, (struct smm_trigger_info *)&trig_info);<br>+}<br>+<br>+void psp_smm_init(uint32_t status)<br>+{<br>+ /* Disable memory read trap that got us here */<br>+ uint32_t reg = smi_read32(SMI_REG_SMICTRL9);<br>+ reg &= ~SMICTRL9_MTRAP_MASK;<br>+ smi_write32(SMI_REG_SMICTRL9, reg);<br>+<br>+ /* Clear the memory trap address */<br>+ smi_write32(SMI_REG_MEM_TRAP0, (uint32_t)0);<br>+<br>+ psp_p2cmbox_init(status);<br>+}<br>diff --git a/src/soc/amd/common/block/psp/psp_smm_get_mbox.c b/src/soc/amd/common/block/psp/psp_smm_get_mbox.c<br>new file mode 100644<br>index 0000000..6ec0f12<br>--- /dev/null<br>+++ b/src/soc/amd/common/block/psp/psp_smm_get_mbox.c<br>@@ -0,0 +1,31 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <console/console.h><br>+#include <amdblocks/psp.h><br>+#include <amdblocks/psp_get_mbox.h><br>+<br>+struct psp_mbox psp_c2p_smm_mbox;<br>+<br>+struct psp_mbox *get_mbox_address(void)<br>+{<br>+ return (struct psp_mbox *)&psp_c2p_smm_mbox;<br>+}<br>+<br>+void PSPProgBar3Msr(void)<br>+{<br>+ printk(BIOS_DEBUG, "SMM stub - PSPProgBar3Msr\n");<br>+}<br>diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c<br>index fe4ab9f..9f1ca9b 100644<br>--- a/src/soc/amd/stoneyridge/cpu.c<br>+++ b/src/soc/amd/stoneyridge/cpu.c<br>@@ -28,6 +28,7 @@<br> #include <soc/southbridge.h><br> #include <soc/smi.h><br> #include <console/console.h><br>+#include <amdblocks/psp_init.h><br> #include <cpu/amd/amdfam15.h><br> #include <smp/node.h><br> <br>@@ -109,9 +110,15 @@<br> .post_mp_init = enable_smi_generation,<br> };<br> <br>+void __attribute__((weak)) psp_initialize(void) { /* no-op */ }<br>+<br> void stoney_init_cpus(struct device *dev)<br> {<br> /* Clear for take-off */<br>- if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)<br>+ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0) {<br> printk(BIOS_ERR, "MP initialization failure.\n");<br>+ return;<br>+ }<br>+<br>+ psp_initialize();<br> }<br>diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h<br>index 46004c9..6f7cadb 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/smi.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/smi.h<br>@@ -16,11 +16,107 @@<br> */<br> #define SMI_BASE 0xfed80200<br> <br>+#define SMI_REG_GPESTAT 0x00 /* GPE event status */<br>+#define SMI_REG_GPE_EVT_EN 0x04 /* GPE event enable */<br>+<br>+#define SMI_REG_SCI_TRIGGER 0x08<br>+#define SMI_REG_SCI_LEVEL 0x0c<br>+#define SMI_REG_SCI_STATUS 0x10<br>+#define SMI_REG_SCI_ENABLE 0x14<br>+#define SMI_REG_SW_SCI_ENABLE 0x18<br>+#define SMI_REG_SW_SCI_DATA 0x1c<br>+#define SMI_REG_SCI_SLP_DISABLE 0x20<br>+<br>+#define SMI_REG_CAPTURED_DATA 0x30<br>+#define SMI_REG_CAPTURED_VALID 0x34<br>+#define SMI_REG_EPBIF_AER_STPS 0x38<br>+#define SMI_REG_DATA_ERR_STS 0x3c<br>+<br>+#define SMI_REG_SCI_MAP0 0x40<br>+#define SMI_REG_SCI_MAP1 0x44<br>+#define SMI_REG_SCI_MAP2 0x48<br>+#define SMI_REG_SCI_MAP3 0x4c<br>+#define SMI_REG_SCI_MAP4 0x50<br>+#define SMI_REG_SCI_MAP5 0x54<br>+#define SMI_REG_SCI_MAP6 0x58<br>+#define SMI_REG_SCI_MAP7 0x5c<br>+#define SMI_REG_SCI_MAP8 0x60<br>+#define SMI_REG_SCI_MAP9 0x64<br>+#define SMI_REG_SCI_MAP10 0x68<br>+#define SMI_REG_SCI_MAP11 0x6c<br>+#define SMI_REG_SCI_MAP12 0x70<br>+#define SMI_REG_SCI_MAP13 0x74<br>+#define SMI_REG_SCI_MAP14 0x78<br>+#define SMI_REG_SCI_MAP15 0x7c<br>+<br>+#define SMI_REG_SMISTAT0 0x80<br>+#define SMI_REG_SMISTAT1 0x84<br>+#define SMISTAT1_FAKESMI_0 (1 << 1)<br>+#define SMISTAT1_FAKESMI_1 (1 << 2)<br>+#define SMISTAT1_FAKESMI_2 (1 << 3)<br>+#define SMISTAT1_FAKESMI_EVTS (0b111 << 1)<br>+#define SMISTAT1_FAKE_SMI_EVTS (SMISTAT1_FAKESMI_0 | SMISTAT1_FAKESMI_1 | SMISTAT1_FAKESMI_2)<br>+#define SMISTAT1_ECGE0_EVTS (1 << 8)<br>+#define SMISTAT1_TWARN_EVTS (1 << 16))<br>+#define SMISTAT1_PWRBTN_EVTS (1 << 19)<br>+#define SMISTAT1_PROCHOT_EVTS (1 << 20)<br>+#define SMI_REG_SMISTAT2 0x88<br>+#define SMISTAT2_SLPTYP_EVTS (1 << 1)<br>+#define SMISTAT2_PWRBTN_EVTS (1 << 10)<br>+#define SMISTAT2_ACPI_CMD_EVTS (1 << 11)<br>+#define SMISTAT2_ECSMI0_EVTS (1 << 15)<br>+#define SMISTAT2_PROCHOT_EVTS (1 << 19)<br>+#define SMI_REG_SMISTAT3 0x8c<br>+#define SMI_REG_SMISTAT4 0x90<br>+#define SMISTAT4_FAKESMI_EVTS (0b111 << 10)<br>+#define SMISTAT4_FAKESMI_0 (1 << 10)<br>+#define SMISTAT4_FAKESMI_1 (1 << 11)<br>+#define SMISTAT4_FAKESMI_2 (1 << 12)<br>+#define SMISTAT4_MEMTRAP_EVT (1 << 24)<br>+<br>+#define SMI_REG_SMI_TIMERT 0x94<br>+<br> #define SMI_REG_SMITRIG0 0x98<br>-#define SMITRG0_EOS (1 << 28)<br> #define SMITRG0_SMIENB (1 << 31)<br>+#define SMITRG0_EOS (1 << 28)<br>+#define SMITRG0_FAKE2 (1 << 27)<br>+#define SMITRG0_FAKE1 (1 << 26)<br>+#define SMITRG0_FAKE0 (1 << 25)<br>+<br>+#define SMI_REG_SMITRIG1 0x9c<br>+<br>+/* Bit settings for SMI_CTL */<br>+#define SMI_CTL_SET_DISABLE (0b00)<br>+#define SMI_CTL_SET_SMI (0b01)<br>+#define SMI_CTL_SET_NMI (0b10)<br>+#define SMI_CTL_SET_IRQ13 (0b11)<br> <br> #define SMI_REG_CONTROL0 0xa0<br>+#define SMI_REG_CONTROL1 0xa4<br>+<br>+#define SMI_REG_SMICTRL2 0xa8 /* SMIs reported in SMIx84 */<br>+#define SMICTRL2_FAKE2_SMI_EN (SMI_CTL_SET_SMI << 6)<br>+#define SMICTRL2_FAKE1_SMI_EN (SMI_CTL_SET_SMI << 4)<br>+#define SMICTRL2_FAKE0_SMI_EN (SMI_CTL_SET_SMI << 2)<br>+<br>+#define SMI_REG_CONTROL3 0xac<br>+#define SMI_REG_CONTROL4 0xb0<br>+#define SMI_REG_CONTROL5 0xb4<br>+#define SMI_REG_CONTROL6 0xb8<br>+#define SMI_REG_CONTROL7 0xbc<br>+<br>+#define SMI_REG_SMICTRL8 0xc0 /* SMIs reported in SMIx90 */<br>+#define SMICTRL8_FAKE2_SMI_EN (SMI_CTL_SET_SMI << 24)<br>+#define SMICTRL8_FAKE1_SMI_EN (SMI_CTL_SET_SMI << 22)<br>+#define SMICTRL8_FAKE0_SMI_EN (SMI_CTL_SET_SMI << 20)<br>+<br>+#define SMI_REG_SMICTRL9 0xc4 /* SMIs reported in SMIx90 */<br>+#define SMICTRL9_MTRAP_EN (SMI_CTL_SET_SMI << 16) /* Enable memory trap SMI */<br>+#define SMICTRL9_MTRAP_MASK (0x03 << 16) /* Memory trap field mask */<br>+#define SMI_REG_IO_TRAP0 0xc8<br>+#define SMI_REG_MEM_TRAP0 0xd0<br>+#define SMI_REG_MEM_RD_OVR_DATA 0xd4<br>+#define SMI_REG_CFG_TRAP0 0xf0<br> <br> enum smi_mode {<br> SMI_MODE_DISABLE = 0,<br>@@ -54,6 +150,8 @@<br> write16((void *)(SMI_BASE + offset), value);<br> }<br> <br>+void smm_southbridge_clear_state(void);<br>+<br> void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);<br> void disable_gevent_smi(uint8_t gevent);<br> void enable_acpi_cmd_smi(void);<br>diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c<br>index 9aff690..9865191 100644<br>--- a/src/soc/amd/stoneyridge/smihandler.c<br>+++ b/src/soc/amd/stoneyridge/smihandler.c<br>@@ -9,6 +9,7 @@<br> #include <console/console.h><br> #include <cpu/x86/smm.h><br> #include <delay.h><br>+#include <amdblocks/psp_smm.h><br> #include <soc/smi.h><br> #include <soc/southbridge.h><br> <br>@@ -105,10 +106,37 @@<br> {<br> const uint32_t status = smi_read32(0x90);<br> <br>+ /* Check for PSP mailbox initialization */<br>+ if (status & SMISTAT4_MEMTRAP_EVT) {<br>+ psp_smm_init(status);<br>+ }<br>+<br>+ /* Check for PSP mailbox event */<br>+ if (status & SMISTAT4_FAKESMI_0)<br>+ psp_p2cmbox_event(status);<br>+<br> /* Clear events to prevent re-entering SMI if event isn't handled */<br> smi_write32(0x90, status);<br> }<br> <br>+void smm_southbridge_clear_state(void)<br>+{<br>+ uint32_t reg = smi_read32(SMI_REG_GPESTAT);<br>+ smi_write32(SMI_REG_GPESTAT, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT0);<br>+ smi_write32(SMI_REG_SMISTAT0, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT1);<br>+ smi_write32(SMI_REG_SMISTAT1, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT2);<br>+ smi_write32(SMI_REG_SMISTAT2, reg);<br>+<br>+ reg = smi_read32(SMI_REG_SMISTAT4);<br>+ smi_write32(SMI_REG_SMISTAT4, reg);<br>+}<br>+<br> void southbridge_smi_handler(void)<br> {<br> const uint16_t smi_src = smi_read16(0x94);<br></pre><p>To view, visit <a href="https://review.coreboot.org/21564">change 21564</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21564"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I88d45b73263369917b67a2e586f44e331bb7028b </div>
<div style="display:none"> Gerrit-Change-Number: 21564 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: frank vibrans <frank.vibrans@scarletltd.com> </div>