<p>Rizwan Qureshi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21547">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Add config for enabling LTR for PCIe Root port<br><br>There are a lot errors reported by AER driver for root port 0.<br>The erors are being caused by an unsupported request from the<br>device to the upstream port. Enabling LTR on the root port stops<br>these errors, it is because LTR is enabled on the device side but<br>not on the root port and hence root port was logging the LTR messages<br>from the device as unsupported.<br><br>The PCIe base spec (v3.1a) section 6.18 also states that:<br>LTR support is discovered and enabled through reporting and control<br>registers described in Chapter 7. Software must not enable LTR in an<br>Endpoint unless the Root Complex and all intermediate Switches indicate<br>support for LTR. Note that it is not required that all Endpoints support<br>LTR to permit enabling LTR in those Endpoints that do support it. When<br>enabling the LTR mechanism in a hierarchy, devices closest to the<br>Root Port must be enabled first.<br><br>If an LTR Message is received at a Downstream Port that does not<br>support LTR or if LTR is not enabled, the Message must be treated<br>as an Unsupported Request. FSP has a UPD for enabling/disabling<br>LTR on root port, use the same for configuring LTR on PCIe root ports.<br><br>BUG=b:65570878<br>TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported<br> by AER driver for root port 0.<br><br>Change-Id: Ica97faa78fcd991dad63ae54d2ada82194b4202a<br>Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com><br>---<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/chip_fsp20.c<br>2 files changed, 36 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21547/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h<br>index 45f3f99..606078b 100644<br>--- a/src/soc/intel/skylake/chip.h<br>+++ b/src/soc/intel/skylake/chip.h<br>@@ -169,12 +169,45 @@<br> /* DCI Enable/Disable */<br> u8 PchDciEn;<br> <br>- /* Pcie Root Ports */<br>+ /*<br>+ * Pcie Root Port configuration:<br>+ * each element of array corresponds to<br>+ * respective PCIe root port.<br>+ */<br>+<br>+ /*<br>+ * Enable/Disable Root Port<br>+ * 0: Disable Root Port<br>+ * 1: Enable Root Port<br>+ */<br> u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS];<br>+<br>+ /*<br>+ * Enable/Disable Clk-req support for Root Port<br>+ * 0: Disable Clk-Req<br>+ * 1: Enable Clk-req<br>+ */<br> u8 PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];<br>+<br>+ /*<br>+ * Clk-req source for Root Port<br>+ */<br> u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];<br>+<br>+ /*<br>+ * Enable/Disable AER (Advanced Error Reporting) for Root Port<br>+ * 0: Disable AER<br>+ * 1: Enable AER<br>+ */<br> u8 PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];<br> <br>+ /*<br>+ * Enable/Disable Latency Tolerance Reporting for Root Port<br>+ * 0: Disable LTR<br>+ * 1: Enable LTR<br>+ */<br>+ u8 PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];<br>+<br> /* USB related */<br> struct usb2_port_config usb2_ports[16];<br> struct usb3_port_config usb3_ports[10];<br>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c<br>index adf8772..b1697ae 100644<br>--- a/src/soc/intel/skylake/chip_fsp20.c<br>+++ b/src/soc/intel/skylake/chip_fsp20.c<br>@@ -169,6 +169,8 @@<br> memcpy(params->PcieRpAdvancedErrorReporting,<br> config->PcieRpAdvancedErrorReporting,<br> sizeof(params->PcieRpAdvancedErrorReporting));<br>+ memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable,<br>+ sizeof(params->PcieRpLtrEnable));<br> <br> /* disable Legacy PME */<br> memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));<br></pre><p>To view, visit <a href="https://review.coreboot.org/21547">change 21547</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21547"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ica97faa78fcd991dad63ae54d2ada82194b4202a </div>
<div style="display:none"> Gerrit-Change-Number: 21547 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>