<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21501">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Enable SMM in TSEG<br><br>Add necessary features to allow mp_init_with_smm() to install and<br>relocate an SMM handler.<br><br>SMM region functions are added to easily identify SMM the attributes.<br>Add relocation attributes to be set by each core a relocation handler<br><br>Modify the definition of smi_southbridge_handler() to match TSEG<br>prototype.<br><br>Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/Kconfig<br>M src/soc/amd/stoneyridge/cpu.c<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/northbridge.c<br>M src/soc/amd/stoneyridge/ramtop.c<br>M src/soc/amd/stoneyridge/smihandler.c<br>6 files changed, 136 insertions(+), 2 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/21501/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig<br>index f708750..beba741 100644<br>--- a/src/soc/amd/stoneyridge/Kconfig<br>+++ b/src/soc/amd/stoneyridge/Kconfig<br>@@ -51,6 +51,8 @@<br> select BOOTBLOCK_CONSOLE<br> select RELOCATABLE_MODULES<br> select PARALLEL_MP<br>+ select HAVE_SMI_HANDLER<br>+ select SMM_TSEG<br> <br> config VBOOT<br> select AMDFW_OUTSIDE_CBFS<br>@@ -286,6 +288,10 @@<br> default 0x800000 if SMM_TSEG && HAVE_SMI_HANDLER<br> default 0x0<br> <br>+config SMM_RESERVED_SIZE<br>+ hex<br>+ default 0x100000<br>+<br> config ACPI_CPU_STRING<br> string<br> default "\\_PR.P%03d"<br>diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c<br>index 22e1a03..fe4ab9f 100644<br>--- a/src/soc/amd/stoneyridge/cpu.c<br>+++ b/src/soc/amd/stoneyridge/cpu.c<br>@@ -26,9 +26,21 @@<br> #include <soc/cpu.h><br> #include <soc/northbridge.h><br> #include <soc/southbridge.h><br>+#include <soc/smi.h><br> #include <console/console.h><br> #include <cpu/amd/amdfam15.h><br> #include <smp/node.h><br>+<br>+/*<br>+ * MP and SMM loading initialization.<br>+ */<br>+struct smm_relocation_attrs {<br>+ uint32_t smbase;<br>+ uint32_t tseg_base;<br>+ uint32_t tseg_mask;<br>+};<br>+<br>+static struct smm_relocation_attrs relo_attrs;<br> <br> /*<br> * Do essential initialization tasks before APs can be fired up -<br>@@ -49,9 +61,52 @@<br> return (pci_read_config16(nb, D18F0_CPU_CNT) & 0xf) + 1;<br> }<br> <br>+static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,<br>+ size_t *smm_save_state_size)<br>+{<br>+ void *smm_base;<br>+ size_t smm_size;<br>+ void *handler_base;<br>+ size_t handler_size;<br>+<br>+ const uint32_t rmask = ~((1 << 17) - 1);<br>+<br>+ /* Initialize global tracking state. */<br>+ smm_region_info(&smm_base, &smm_size);<br>+ smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);<br>+<br>+ relo_attrs.smbase = (uint32_t)smm_base;<br>+ relo_attrs.tseg_base = relo_attrs.smbase;<br>+ relo_attrs.tseg_mask = ~(smm_size - 1) & rmask;<br>+ relo_attrs.tseg_mask |= SMM_TSEG_WB | SMM_TSEG_VALID;<br>+<br>+ *perm_smbase = (uintptr_t)handler_base;<br>+ *perm_smsize = handler_size;<br>+ *smm_save_state_size = sizeof(amd64_smm_state_save_area_t);<br>+}<br>+<br>+static void relocation_handler(int cpu, uintptr_t curr_smbase,<br>+ uintptr_t staggered_smbase)<br>+{<br>+ msr_t tseg_base, tseg_mask;<br>+ amd64_smm_state_save_area_t *smm_state;<br>+<br>+ tseg_base.lo = relo_attrs.tseg_base;<br>+ tseg_base.hi = 0;<br>+ wrmsr(MSR_TSEG_BASE, tseg_base);<br>+ tseg_mask.lo = relo_attrs.tseg_mask;<br>+ tseg_mask.hi = 0;<br>+ wrmsr(MSR_SMM_MASK, tseg_mask);<br>+ smm_state = (void *)(SMM_AMD64_SAVE_STATE_OFFSET + curr_smbase);<br>+ smm_state->smbase = staggered_smbase;<br>+}<br>+<br> static const struct mp_ops mp_ops = {<br> .pre_mp_init = pre_mp_init,<br> .get_cpu_count = get_cpu_count,<br>+ .get_smm_info = get_smm_info,<br>+ .relocation_handler = relocation_handler,<br>+ .post_mp_init = enable_smi_generation,<br> };<br> <br> void stoney_init_cpus(struct device *dev)<br>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>index 4f8707c..da5fa59 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>@@ -2,6 +2,7 @@<br> * This file is part of the coreboot project.<br> *<br> * Copyright (C) 2015 Advanced Micro Devices, Inc.<br>+ * Copyright (C) 2015 Intel Corp.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -20,6 +21,21 @@<br> #include <arch/io.h><br> #include <device/device.h><br> <br>+enum {<br>+ /* SMM handler area. */<br>+ SMM_SUBREGION_HANDLER,<br>+ /* SMM cache region. */<br>+ SMM_SUBREGION_CACHE,<br>+ /* Chipset specific area. */<br>+ SMM_SUBREGION_CHIPSET,<br>+ /* Total sub regions supported. */<br>+ SMM_SUBREGION_NUM,<br>+};<br>+<br>+/* Fills in the arguments for the entire SMM region covered by chipset<br>+ * protections. e.g. TSEG. */<br>+void smm_region_info(void **start, size_t *size);<br>+int smm_subregion(int sub, void **start, size_t *size);<br> void domain_enable_resources(device_t dev);<br> void domain_read_resources(device_t dev);<br> void domain_set_resources(device_t dev);<br>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c<br>index ef075b6..d248c94 100644<br>--- a/src/soc/amd/stoneyridge/northbridge.c<br>+++ b/src/soc/amd/stoneyridge/northbridge.c<br>@@ -418,6 +418,8 @@<br> u32 hole;<br> int idx;<br> struct bus *link;<br>+ void *tseg_base;<br>+ size_t tseg_size;<br> <br> pci_tolm = 0xffffffffUL;<br> for (link = dev->link_list ; link ; link = link->next)<br>@@ -501,6 +503,11 @@<br> */<br> mmio_resource(dev, 0xa0000, 0xa0000 / KiB, 0x20000 / KiB);<br> reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB);<br>+<br>+ /* Reserve TSEG */<br>+ smm_region_info(&tseg_base, &tseg_size);<br>+ idx += 0x10;<br>+ mmio_resource(dev, idx, (unsigned long)tseg_base/KiB, tseg_size/KiB);<br> }<br> <br> /*********************************************************************<br>diff --git a/src/soc/amd/stoneyridge/ramtop.c b/src/soc/amd/stoneyridge/ramtop.c<br>index bbe11d2..6a54710 100644<br>--- a/src/soc/amd/stoneyridge/ramtop.c<br>+++ b/src/soc/amd/stoneyridge/ramtop.c<br>@@ -1,6 +1,8 @@<br> /*<br> * This file is part of the coreboot project.<br> *<br>+ * Copyright (C) 2015 Intel Corp.<br>+ *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br> * the Free Software Foundation; version 2 of the License.<br>@@ -13,11 +15,13 @@<br> <br> #define __SIMPLE_DEVICE__<br> <br>+#include <assert.h><br> #include <stdint.h><br> #include <arch/io.h><br> #include <cpu/x86/msr.h><br> #include <cpu/amd/mtrr.h><br> #include <cbmem.h><br>+#include <soc/northbridge.h><br> <br> #define CBMEM_TOP_SCRATCHPAD 0x78<br> <br>@@ -44,3 +48,50 @@<br> return (void *)ALIGN_DOWN(restore_top_of_low_cacheable()<br> - CONFIG_SMM_TSEG_SIZE, 128*KiB);<br> }<br>+<br>+static uintptr_t smm_region_start(void)<br>+{<br>+ return (uintptr_t)cbmem_top();<br>+}<br>+<br>+static size_t smm_region_size(void)<br>+{<br>+ return CONFIG_SMM_TSEG_SIZE;<br>+}<br>+<br>+void smm_region_info(void **start, size_t *size)<br>+{<br>+ *start = (void *)smm_region_start();<br>+ *size = smm_region_size();<br>+}<br>+<br>+int smm_subregion(int sub, void **start, size_t *size)<br>+{<br>+ uintptr_t sub_base;<br>+ size_t sub_size;<br>+ const size_t cache_size = CONFIG_SMM_RESERVED_SIZE;<br>+<br>+ sub_base = smm_region_start();<br>+ sub_size = smm_region_size();<br>+<br>+ assert(sub_size > CONFIG_SMM_RESERVED_SIZE);<br>+<br>+ switch (sub) {<br>+ case SMM_SUBREGION_HANDLER:<br>+ /* Handler starts at the base of TSEG. */<br>+ sub_size -= cache_size;<br>+ break;<br>+ case SMM_SUBREGION_CACHE:<br>+ /* External cache is in the middle of TSEG. */<br>+ sub_base += sub_size - cache_size;<br>+ sub_size = cache_size;<br>+ break;<br>+ default:<br>+ return -1;<br>+ }<br>+<br>+ *start = (void *)sub_base;<br>+ *size = sub_size;<br>+<br>+ return 0;<br>+}<br>diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c<br>index a8ff96a..9aff690 100644<br>--- a/src/soc/amd/stoneyridge/smihandler.c<br>+++ b/src/soc/amd/stoneyridge/smihandler.c<br>@@ -109,8 +109,7 @@<br> smi_write32(0x90, status);<br> }<br> <br>-void southbridge_smi_handler(unsigned int node,<br>- smm_state_save_area_t *state_save)<br>+void southbridge_smi_handler(void)<br> {<br> const uint16_t smi_src = smi_read16(0x94);<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21501">change 21501</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21501"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce </div>
<div style="display:none"> Gerrit-Change-Number: 21501 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>