<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21503">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/car/cache_as_ram.inc: Fix long standing issues<br><br>Do not set %ebp before and switch directly to stack returned by<br>romstage_main().<br><br>Remove an unneeded 4-byte gap in CAR stack.<br><br>The caching strategy for flash XIP area should be WRPROT.<br><br>Clarify the various comments in the file on the logic.<br><br>Together they lay the groundwork for bringing EARLY_CBMEM_INIT to<br>intel/slot_1 boards.<br><br>Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>---<br>M src/cpu/intel/car/cache_as_ram.inc<br>1 file changed, 23 insertions(+), 35 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/21503/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc<br>index 7cf55b3..d208cee 100644<br>--- a/src/cpu/intel/car/cache_as_ram.inc<br>+++ b/src/cpu/intel/car/cache_as_ram.inc<br>@@ -22,9 +22,6 @@<br> #include <cpu/x86/lapic_def.h><br> #include <cpu/x86/post_code.h><br> <br>-#define CacheSize CONFIG_DCACHE_RAM_SIZE<br>-#define CacheBase (0xd0000 - CacheSize)<br>-<br> /* Save the BIST result. */<br> movl %eax, %ebp<br> <br>@@ -128,32 +125,29 @@<br> */<br> .endm<br> <br>-#if CacheSize > 0x10000<br>+#if CONFIG_DCACHE_RAM_SIZE > 0x10000<br> #error Invalid CAR size, must be at most 64k.<br> #endif<br>-#if CacheSize < 0x1000<br>+#if CONFIG_DCACHE_RAM_SIZE < 0x1000<br> #error Invalid CAR size, must be at least 4k. This is a processor limitation.<br> #endif<br>-#if (CacheSize & (0x1000 - 1))<br>+#if (CONFIG_DCACHE_RAM_SIZE & (0x1000 - 1))<br> #error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.<br> #endif<br> <br>-#if CacheSize > 0x8000<br>+#if CONFIG_DCACHE_RAM_SIZE > 0x8000<br> /* Enable caching for 32K-64K using fixed MTRR. */<br> movl $MTRR_FIX_4K_C0000, %ecx<br>- simplemask CacheSize, 0x8000<br>+ simplemask CONFIG_DCACHE_RAM_SIZE, 0x8000<br> wrmsr<br> #endif<br> <br> /* Enable caching for 0-32K using fixed MTRR. */<br> movl $MTRR_FIX_4K_C8000, %ecx<br>- simplemask CacheSize, 0<br>+ simplemask CONFIG_DCACHE_RAM_SIZE, 0<br> wrmsr<br> <br>- /*<br>- * Enable write base caching so we can do execute in place (XIP)<br>- * on the flash ROM.<br>- */<br>+ /* Enable cache for our code in Flash because we do XIP here. */<br> movl $MTRR_PHYS_BASE(1), %ecx<br> xorl %edx, %edx<br> /*<br>@@ -162,7 +156,7 @@<br> */<br> movl $copy_and_run, %eax<br> andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax<br>- orl $MTRR_TYPE_WRBACK, %eax<br>+ orl $MTRR_TYPE_WRPROT, %eax<br> wrmsr<br> <br> movl $MTRR_PHYS_MASK(1), %ecx<br>@@ -175,33 +169,31 @@<br> andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax<br> movl %eax, %cr0<br> <br>- /* Read the range with lodsl. */<br>- movl $CacheBase, %esi<br>+ /* Read the CAR region. This will also fill up the cache.<br>+ * IMPORTANT: This step is mandatory.<br>+ */<br>+ movl $CONFIG_DCACHE_RAM_BASE, %esi<br> cld<br>- movl $(CacheSize >> 2), %ecx<br>+ movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx<br> rep lodsl<br> <br>- /* Clear the range. */<br>- movl $CacheBase, %edi<br>- movl $(CacheSize >> 2), %ecx<br>+ /* Clear the CAR region. */<br>+ movl $CONFIG_DCACHE_RAM_BASE, %edi<br>+ movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx<br> xorl %eax, %eax<br> rep stosl<br> <br>- movl $(CacheBase + CacheSize - 4), %eax<br>+ movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax<br> movl %eax, %esp<br> lout:<br> /* Restore the BIST result. */<br> movl %ebp, %eax<br> <br>- /* We need to set EBP? No need. */<br>- movl %esp, %ebp<br> pushl %eax /* BIST */<br> call romstage_main<br> <br>- /* Save return value from romstage_main. It contains the stack to use<br>- * after cache-as-ram is torn down.<br>- */<br>- movl %eax, %ebx<br>+ /* Setup stack as indicated by return value from romstage_main(). */<br>+ movl %eax, %esp<br> <br> /* We don't need CAR from now on. */<br> <br>@@ -210,7 +202,7 @@<br> orl $CR0_CacheDisable, %eax<br> movl %eax, %cr0<br> <br>- /* Clear sth. */<br>+ /* Clear the fixed MTRR we used. */<br> movl $MTRR_FIX_4K_C8000, %ecx<br> xorl %edx, %edx<br> xorl %eax, %eax<br>@@ -222,12 +214,12 @@<br> #endif<br> <br> /*<br>- * Set the default memory type and disable fixed<br>- * and enable variable MTRRs.<br>+ * Enable variable and disable fixed MTRRs.<br>+ * Default memory type will be UC.<br> */<br> movl $MTRR_DEF_TYPE_MSR, %ecx<br> xorl %edx, %edx<br>- movl $MTRR_DEF_TYPE_EN, %eax /* Enable variable and disable fixed MTRRs. */<br>+ movl $MTRR_DEF_TYPE_EN, %eax<br> wrmsr<br> <br> /* Enable cache. */<br>@@ -238,10 +230,6 @@<br> __main:<br> post_code(POST_PREPARE_RAMSTAGE)<br> cld /* Clear direction flag. */<br>-<br>- /* Setup stack as indicated by return value from romstage_main(). */<br>- movl %ebx, %esp<br>- movl %esp, %ebp<br> call copy_and_run<br> <br> .Lhlt:<br></pre><p>To view, visit <a href="https://review.coreboot.org/21503">change 21503</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484 </div>
<div style="display:none"> Gerrit-Change-Number: 21503 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>