<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21498">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Convert MP init to mp_init_with_smm<br><br>Change the Stoney Ridge SOC to a more modern method for setting up<br>the multiple cores.<br><br>Add a new cpu.c file for most of the processor initiliazation. Build<br>mp_ops with the necessary callbacks. Note also that this patch removes<br>cpu_bus_scan. Rather than manually find CPUs and add them to the<br>devicetree, allow this to be done automatically in the generic<br>mp_init.c file.<br><br>SMM information is left blank in mp_ops to avoid having mp_init.c<br>install a handler at this time. A later patch will add TSEG SMM<br>capabilities for the APU.<br><br>Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/Kconfig<br>M src/soc/amd/stoneyridge/Makefile.inc<br>M src/soc/amd/stoneyridge/chip.c<br>A src/soc/amd/stoneyridge/cpu.c<br>A src/soc/amd/stoneyridge/include/soc/cpu.h<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/northbridge.c<br>7 files changed, 88 insertions(+), 83 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/21498/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig<br>index 1e13cc0..f708750 100644<br>--- a/src/soc/amd/stoneyridge/Kconfig<br>+++ b/src/soc/amd/stoneyridge/Kconfig<br>@@ -49,6 +49,8 @@<br> select SOC_AMD_COMMON_BLOCK_CAR<br> select C_ENVIRONMENT_BOOTBLOCK<br> select BOOTBLOCK_CONSOLE<br>+ select RELOCATABLE_MODULES<br>+ select PARALLEL_MP<br> <br> config VBOOT<br> select AMDFW_OUTSIDE_CBFS<br>diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc<br>index b6669f1..07c14ce 100644<br>--- a/src/soc/amd/stoneyridge/Makefile.inc<br>+++ b/src/soc/amd/stoneyridge/Makefile.inc<br>@@ -61,6 +61,7 @@<br> verstage-y += tsc_freq.c<br> <br> ramstage-y += chip.c<br>+ramstage-y += cpu.c<br> ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c<br> ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c<br> ramstage-y += fixme.c<br>diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c<br>index 14f76b7..325d2ea 100644<br>--- a/src/soc/amd/stoneyridge/chip.c<br>+++ b/src/soc/amd/stoneyridge/chip.c<br>@@ -18,20 +18,16 @@<br> #include <cpu/cpu.h><br> #include <device/device.h><br> #include <device/pci.h><br>-#include <soc/southbridge.h><br>+#include <soc/cpu.h><br> #include <soc/northbridge.h><br>-<br>-static void cpu_bus_init(device_t dev)<br>-{<br>- initialize_cpus(dev->link_list);<br>-}<br>+#include <soc/southbridge.h><br> <br> struct device_operations cpu_bus_ops = {<br> .read_resources = DEVICE_NOOP,<br> .set_resources = DEVICE_NOOP,<br> .enable_resources = DEVICE_NOOP,<br>- .init = &cpu_bus_init,<br>- .scan_bus = cpu_bus_scan,<br>+ .init = stoney_init_cpus,<br>+ .scan_bus = NULL,<br> .acpi_fill_ssdt_generator = generate_cpu_entries,<br> };<br> <br>diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c<br>new file mode 100644<br>index 0000000..22e1a03<br>--- /dev/null<br>+++ b/src/soc/amd/stoneyridge/cpu.c<br>@@ -0,0 +1,62 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015-2016 Intel Corp.<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <chip.h><br>+#include <cpu/x86/mp.h><br>+#include <cpu/x86/mtrr.h><br>+#include <cpu/x86/lapic.h><br>+#include <cpu/amd/mtrr.h><br>+#include <cpu/cpu.h><br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <soc/pci_devs.h><br>+#include <soc/cpu.h><br>+#include <soc/northbridge.h><br>+#include <soc/southbridge.h><br>+#include <console/console.h><br>+#include <cpu/amd/amdfam15.h><br>+#include <smp/node.h><br>+<br>+/*<br>+ * Do essential initialization tasks before APs can be fired up -<br>+ *<br>+ * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This<br>+ * creates the MTRR solution that the APs will use. Otherwise APs will try to<br>+ * apply the incomplete solution as the BSP is calculating it.<br>+ */<br>+static void pre_mp_init(void)<br>+{<br>+ x86_setup_mtrrs_with_detect();<br>+ x86_mtrr_check();<br>+}<br>+<br>+static int get_cpu_count(void)<br>+{<br>+ device_t nb = dev_find_slot(0, HT_DEVFN);<br>+ return (pci_read_config16(nb, D18F0_CPU_CNT) & 0xf) + 1;<br>+}<br>+<br>+static const struct mp_ops mp_ops = {<br>+ .pre_mp_init = pre_mp_init,<br>+ .get_cpu_count = get_cpu_count,<br>+};<br>+<br>+void stoney_init_cpus(struct device *dev)<br>+{<br>+ /* Clear for take-off */<br>+ if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)<br>+ printk(BIOS_ERR, "MP initialization failure.\n");<br>+}<br>diff --git a/src/soc/amd/stoneyridge/include/soc/cpu.h b/src/soc/amd/stoneyridge/include/soc/cpu.h<br>new file mode 100644<br>index 0000000..029d0a6<br>--- /dev/null<br>+++ b/src/soc/amd/stoneyridge/include/soc/cpu.h<br>@@ -0,0 +1,19 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Advanced Micro Devices, Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#define D18F0_NODE_ID 0x60<br>+#define D18F0_CPU_CNT 0x62<br>+<br>+void stoney_init_cpus(struct device *dev);<br>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>index 13d7d36..4f8707c 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>@@ -20,7 +20,6 @@<br> #include <arch/io.h><br> #include <device/device.h><br> <br>-void cpu_bus_scan(device_t dev);<br> void domain_enable_resources(device_t dev);<br> void domain_read_resources(device_t dev);<br> void domain_set_resources(device_t dev);<br>diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c<br>index 739b979..ef075b6 100644<br>--- a/src/soc/amd/stoneyridge/northbridge.c<br>+++ b/src/soc/amd/stoneyridge/northbridge.c<br>@@ -503,80 +503,6 @@<br> reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB);<br> }<br> <br>-void cpu_bus_scan(device_t dev)<br>-{<br>- struct bus *cpu_bus;<br>- device_t cpu;<br>- device_t cdb_dev;<br>- device_t dev_mc;<br>- int j;<br>- int core_max;<br>- int core_nums;<br>- int siblings;<br>- int family;<br>- int enable_node;<br>- u32 lapicid_start;<br>- u32 apic_id;<br>- u32 pccount;<br>-<br>-<br>- dev_mc = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 0));<br>- if (!dev_mc) {<br>- printk(BIOS_ERR, "%02x:%02x.0 not found", CONFIG_CBB,<br>- CONFIG_CDB);<br>- die("");<br>- }<br>-<br>- /* Get max and actual number of cores */<br>- pccount = cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT);<br>- core_max = 1 << ((pccount >> 12) & 0xf);<br>- core_nums = (pccount & 0xF);<br>-<br>- family = (cpuid_eax(1) >> 20) & 0xff;<br>-<br>- cdb_dev = dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, 5));<br>- siblings = pci_read_config32(cdb_dev, 0x84) & 0xff;<br>-<br>- printk(BIOS_SPEW, "%s family%xh, core_max=%d, core_nums=%d,"<br>- " siblings=%d\n", dev_path(cdb_dev), 0x0f + family,<br>- core_max, core_nums, siblings);<br>-<br>- /*<br>- * APIC ID calucation is tightly coupled with AGESA v5 code.<br>- * This calculation MUST match the assignment calculation done<br>- * in LocalApicInitializationAtEarly() function.<br>- * And reference GetLocalApicIdForCore()<br>- *<br>- * Apply apic enumeration rules<br>- * For systems with >= 16 APICs, put the IO-APICs at 0..n and<br>- * put the local-APICs at m..z<br>- *<br>- * This is needed because many IO-APIC devices only have 4 bits<br>- * for their APIC id and therefore must reside at 0..15<br>- */<br>-<br>- /*<br>- * While the above statement is true, we know some things about<br>- * this silicon. It is an SOC and can't have >= 16 APICs, but<br>- * we will start numbering at 0x10. We also know there is only<br>- * on physical node (module in AMD speak).<br>- */<br>-<br>- lapicid_start = 0x10; /* Get this from devicetree? see comment above. */<br>- enable_node = cdb_dev->enabled;<br>- cpu_bus = dev->link_list;<br>-<br>- for (j = 0 ; j <= siblings ; j++) {<br>- apic_id = lapicid_start + j;<br>- printk(BIOS_SPEW, "lapicid_start 0x%x, core 0x%x,"<br>- " apicid=0x%x\n", lapicid_start, j, apic_id);<br>-<br>- cpu = add_cpu_device(cpu_bus, apic_id, enable_node);<br>- if (cpu)<br>- amd_cpu_topology(cpu, 1, j);<br>- }<br>-}<br>-<br> /*********************************************************************<br> * Change the vendor / device IDs to match the generic VBIOS header. *<br> *********************************************************************/<br></pre><p>To view, visit <a href="https://review.coreboot.org/21498">change 21498</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914 </div>
<div style="display:none"> Gerrit-Change-Number: 21498 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>