<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21493">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Remove CONFIG_LOGICAL_CPUS setup<br><br>Delete the check for sibling cores and the programming of CPUID HTT<br>and CmpLegacy back-door bits. The code has no effect on modern<br>Family 15h APUs. The bits being modified come up set out of reset.<br><br>Change-Id: Ida76863d84109b49ce6b12c71bad5b44331a2ff9<br>Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com><br>---<br>M src/soc/amd/stoneyridge/model_15_init.c<br>1 file changed, 0 insertions(+), 20 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/21493/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/model_15_init.c b/src/soc/amd/stoneyridge/model_15_init.c<br>index 631e89c..7dfcdb8 100644<br>--- a/src/soc/amd/stoneyridge/model_15_init.c<br>+++ b/src/soc/amd/stoneyridge/model_15_init.c<br>@@ -37,9 +37,6 @@<br> u8 i;<br> msr_t msr;<br> int msrno;<br>-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br>- u32 siblings;<br>-#endif<br> <br> disable_cache();<br> /* Enable access to AMD RdDram and WrDram extension bits */<br>@@ -71,30 +68,13 @@<br> for (i = 0 ; i < 6 ; i++)<br> wrmsr(MCI_STATUS + (i * 4), msr);<br> <br>-<br> /* Enable the local CPU APICs */<br> setup_lapic();<br>-<br>-#if IS_ENABLED(CONFIG_LOGICAL_CPUS)<br>- siblings = cpuid_ecx(0x80000008) & 0xff;<br>-<br>- if (siblings > 0) {<br>- msr = rdmsr_amd(CPU_ID_FEATURES_MSR);<br>- msr.lo |= 1 << 28;<br>- wrmsr_amd(CPU_ID_FEATURES_MSR, msr);<br>-<br>- msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);<br>- msr.hi |= 1 << (33 - 32);<br>- wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);<br>- }<br>- printk(BIOS_DEBUG, "siblings = %02d, ", siblings);<br>-#endif<br> <br> /* DisableCf8ExtCfg */<br> msr = rdmsr(NB_CFG_MSR);<br> msr.hi &= ~(1 << (46 - 32));<br> wrmsr(NB_CFG_MSR, msr);<br>-<br> <br> /* Write protect SMM space with SMMLOCK. */<br> msr = rdmsr(HWCR_MSR);<br></pre><p>To view, visit <a href="https://review.coreboot.org/21493">change 21493</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21493"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ida76863d84109b49ce6b12c71bad5b44331a2ff9 </div>
<div style="display:none"> Gerrit-Change-Number: 21493 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>