<p>Pratikkumar V Prajapati has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21482">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] mainboard/intel/cannonlake_rvp-u: Configure USB ports<br><br>Configure USB2, USB3 and Type-C ports for CannonLake-U RVP<br><br>Change-Id: Id875063721ccb62ad4b5187c81f6abf44bf93f74<br>Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>1 file changed, 18 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/21482/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>index a3c4c80..2c693c3 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb<br>@@ -9,6 +9,24 @@<br>    register "FspSkipMpInit" = "1"<br>    register "SmbusEnable" = "1"<br> <br>+  register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"<br>+       register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"<br>+  register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"<br>+  register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"<br>+  register "usb2_ports[4]" = "USB2_PORT_MID(OC0)"<br>+  register "usb2_ports[5]" = "USB2_PORT_MID(OC0)"<br>+  register "usb2_ports[6]" = "USB2_PORT_MID(OC0)"<br>+  register "usb2_ports[7]" = "USB2_PORT_MID(OC0)"<br>+  register "usb2_ports[8]" = "USB2_PORT_MID(OC0)"<br>+  register "usb2_ports[9]" = "USB2_PORT_MID(OC0)"<br>+<br>+       register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"<br>+      register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"<br>+      register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)"<br>+      register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)"<br>+      register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)"<br>+      register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)"<br>+<br>    device domain 0 on<br>            device pci 00.0 on  end # Host Bridge<br>                 device pci 02.0 on  end # Integrated Graphics Device<br></pre><p>To view, visit <a href="https://review.coreboot.org/21482">change 21482</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21482"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id875063721ccb62ad4b5187c81f6abf44bf93f74 </div>
<div style="display:none"> Gerrit-Change-Number: 21482 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>