<p>Marshall Dawson has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21495">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">amd/stoneyridge: Remove multi-node support<br><br>The Stoney Ridge APU can never be used in a multi-node system. Reduce<br>the feature set to a single node.<br><br>Remove the static variables for each D18Fn device and replace the routines<br>with coreboot config read and write functions.<br><br>Strip down domain_set_resources() to consider only a single node. A<br>follow-on patch will further simplify this.<br><br>Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a<br>---<br>M src/soc/amd/stoneyridge/northbridge.c<br>1 file changed, 36 insertions(+), 88 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/21495/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c<br>index 8e3c13c..2ed3156 100644<br>--- a/src/soc/amd/stoneyridge/northbridge.c<br>+++ b/src/soc/amd/stoneyridge/northbridge.c<br>@@ -31,6 +31,7 @@<br> #include <agesawrapper.h><br> #include <agesawrapper_call.h><br> #include <soc/northbridge.h><br>+#include <soc/pci_devs.h><br> #include <stdint.h><br> #include <stdlib.h><br> #include <string.h><br>@@ -46,8 +47,6 @@<br> #include <Porting.h><br> #include <Topology.h><br> <br>-#define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)<br>-<br> #if IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)<br> #error CONFIG_EXT_CONF_SUPPORT == 1 not support anymore!<br> #endif<br>@@ -57,33 +56,26 @@<br> u32 mask; /* [47:27] at [28:8] and enable at bit 0 */<br> } dram_base_mask_t;<br> <br>-static unsigned int node_nums;<br>-static device_t __f0_dev;<br>-static device_t __f1_dev;<br>-static device_t __f2_dev;<br>-static device_t __f4_dev;<br>-static unsigned int fx_dev = 0;<br>-<br>-static dram_base_mask_t get_dram_base_mask(u32 nodeid)<br>+static dram_base_mask_t get_dram_base_mask(void)<br> {<br>- device_t dev = __f1_dev;<br>+ device_t dev = dev_find_slot(0, ADDR_DEVFN);<br> dram_base_mask_t d;<br> u32 temp;<br> <br> /* [39:24] at [31:16] */<br>- temp = pci_read_config32(dev, 0x44 + (nodeid << 3));<br>+ temp = pci_read_config32(dev, 0x44);<br> <br> /* mask out DramMask [26:24] too */<br> d.mask = ((temp & 0xfff80000) >> (8 + 3));<br> <br> /* [47:40] at [7:0] */<br>- temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff;<br>+ temp = pci_read_config32(dev, 0x144) & 0xff;<br> d.mask |= temp << 21;<br> <br>- temp = pci_read_config32(dev, 0x40 + (nodeid << 3));<br>+ temp = pci_read_config32(dev, 0x40);<br> d.mask |= (temp & 1); /* enable bit */<br> d.base = ((temp & 0xfff80000) >> (8 + 3));<br>- temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff;<br>+ temp = pci_read_config32(dev, 0x140) & 0xff;<br> d.base |= temp << 21;<br> return d;<br> }<br>@@ -92,54 +84,27 @@<br> u32 io_min, u32 io_max)<br> {<br> u32 tempreg;<br>+ device_t addr_map = dev_find_slot(0, ADDR_DEVFN);<br>+<br> /* io range allocation. Limit */<br> tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4)<br> | ((io_max & 0xf0) << (12 - 4));<br>- pci_write_config32(__f1_dev, reg + 4, tempreg);<br>+ pci_write_config32(addr_map, reg + 4, tempreg);<br> tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */<br>- pci_write_config32(__f1_dev, reg, tempreg);<br>+ pci_write_config32(addr_map, reg, tempreg);<br> }<br> <br> static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,<br> u32 mmio_min, u32 mmio_max)<br> {<br> u32 tempreg;<br>+ device_t addr_map = dev_find_slot(0, ADDR_DEVFN);<br>+<br> /* io range allocation. Limit */<br> tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00);<br>- pci_write_config32(__f1_dev, reg + 4, tempreg);<br>+ pci_write_config32(addr_map, reg + 4, tempreg);<br> tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00);<br>- pci_write_config32(__f1_dev, reg, tempreg);<br>-}<br>-<br>-static device_t get_node_pci(u32 fn)<br>-{<br>- return dev_find_slot(CONFIG_CBB, PCI_DEVFN(CONFIG_CDB, fn));<br>-}<br>-<br>-static void get_fx_dev(void)<br>-{<br>- __f0_dev = get_node_pci(0);<br>- __f1_dev = get_node_pci(1);<br>- __f2_dev = get_node_pci(2);<br>- __f4_dev = get_node_pci(4);<br>- fx_dev = 1;<br>-<br>- if (__f1_dev == NULL || __f0_dev == NULL || fx_dev == 0)<br>- die("Cannot find 0:0x18.[0|1]\n");<br>-}<br>-<br>-static u32 f1_read_config32(unsigned int reg)<br>-{<br>- if (fx_dev == 0)<br>- get_fx_dev();<br>- return pci_read_config32(__f1_dev, reg);<br>-}<br>-<br>-static void f1_write_config32(unsigned int reg, u32 value)<br>-{<br>- if (fx_dev == 0)<br>- get_fx_dev();<br>- pci_write_config32(__f1_dev, reg, value);<br>+ pci_write_config32(addr_map, reg, tempreg);<br> }<br> <br> static void read_resources(device_t dev)<br>@@ -216,7 +181,8 @@<br> return;<br> <br> printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev));<br>- f1_write_config32(0xf4, 1); /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */<br>+ /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */<br>+ pci_write_config32(dev_find_slot(0, ADDR_DEVFN), 0xf4, 1);<br> }<br> <br> static void set_resources(device_t dev)<br>@@ -403,24 +369,23 @@<br> void domain_read_resources(device_t dev)<br> {<br> unsigned int reg;<br>+ device_t addr_map = dev_find_slot(0, ADDR_DEVFN);<br> <br> /* Find the already assigned resource pairs */<br>- get_fx_dev();<br> for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) {<br> u32 base, limit;<br>- base = f1_read_config32(reg);<br>- limit = f1_read_config32(reg + 0x04);<br>+ base = pci_read_config32(addr_map, reg);<br>+ limit = pci_read_config32(addr_map, reg + 4);<br> /* Is this register allocated? */<br> if ((base & 3) != 0) {<br> unsigned int nodeid, reg_link;<br>- device_t reg_dev;<br>+ device_t reg_dev = dev_find_slot(0, HT_DEVFN);<br> if (reg < 0xc0) /* mmio */<br> nodeid = (limit & 0xf) + (base & 0x30);<br> else /* io */<br> nodeid = (limit & 0xf) + ((base >> 4) & 0x30);<br> <br> reg_link = (limit >> 4) & 7;<br>- reg_dev = __f0_dev;<br> if (reg_dev) {<br> /* Reserve the resource */<br> struct resource *res;<br>@@ -463,8 +428,8 @@<br> mem_hole.node_id = -1;<br> dram_base_mask_t d;<br> u32 hole;<br>- d = get_dram_base_mask(0);<br>- hole = pci_read_config32(__f1_dev, 0xf0);<br>+ d = get_dram_base_mask();<br>+ hole = pci_read_config32(dev_find_slot(0, ADDR_DEVFN), 0xf0);<br> if (hole & 2) {<br> /* We found the hole */<br> mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;<br>@@ -479,7 +444,7 @@<br> {<br> unsigned long mmio_basek;<br> u32 pci_tolm;<br>- int i, idx;<br>+ int idx;<br> struct bus *link;<br> #if CONFIG_HW_MEM_HOLE_SIZEK != 0<br> struct hw_mem_hole_info mem_hole;<br>@@ -517,14 +482,12 @@<br> #endif<br> <br> idx = 0x10;<br>- for (i = 0 ; i < node_nums ; i++) {<br>- dram_base_mask_t d;<br>- resource_t basek, limitk, sizek; /* 4 1T */<br>+ dram_base_mask_t d;<br>+ resource_t basek, limitk, sizek; /* 4 1T */<br> <br>- d = get_dram_base_mask(i);<br>+ d = get_dram_base_mask();<br> <br>- if (!(d.mask & 1))<br>- continue;<br>+ if ((d.mask & 1)) { /* if enabled... */<br> /* could overflow, we may lose 6 bit here */<br> basek = ((resource_t)(d.base & 0x1fffff00)) << 9;<br> limitk = ((resource_t)(((d.mask & ~1) + 0x000ff)<br>@@ -535,7 +498,7 @@<br> /* see if we need a hole from 0xa0000 to 0xbffff */<br> if ((basek < ((8 * 64) + (8 * 16))) && (sizek > ((8 * 64) +<br> (16 * 16)))) {<br>- ram_resource(dev, (idx | i), basek,<br>+ ram_resource(dev, idx, basek,<br> ((8 * 64) + (8 * 16)) - basek);<br> idx += 0x10;<br> basek = (8 * 64) + (16 * 16);<br>@@ -549,7 +512,7 @@<br> unsigned int pre_sizek;<br> pre_sizek = mmio_basek - basek;<br> if (pre_sizek > 0) {<br>- ram_resource(dev, (idx | i), basek,<br>+ ram_resource(dev, idx, basek,<br> pre_sizek);<br> idx += 0x10;<br> sizek -= pre_sizek;<br>@@ -565,11 +528,9 @@<br> }<br> }<br> <br>- ram_resource(dev, (idx | i), basek, sizek);<br>- idx += 0x10;<br>- printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx,"<br>- " limitk=%08llx\n", i, mmio_basek, basek,<br>- limitk);<br>+ ram_resource(dev, idx, basek, sizek);<br>+ printk(BIOS_DEBUG, "node 0: mmio_basek=%08lx, basek=%08llx,"<br>+ " limitk=%08llx\n", mmio_basek, basek, limitk);<br> }<br> <br> add_uma_resource_below_tolm(dev, 7);<br>@@ -586,13 +547,6 @@<br> */<br> mmio_resource(dev, 0xa0000, 0xa0000 / KiB, 0x20000 / KiB);<br> reserved_ram_resource(dev, 0xc0000, 0xc0000 / KiB, 0x40000 / KiB);<br>-}<br>-<br>-/* first node */<br>-static void sysconf_init(device_t dev)<br>-{<br>- /* NodeCnt[2:0] */<br>- node_nums = ((pci_read_config32(dev, 0x60) >> 4) & 7) + 1;<br> }<br> <br> void cpu_bus_scan(device_t dev)<br>@@ -618,11 +572,6 @@<br> CONFIG_CDB);<br> die("");<br> }<br>- sysconf_init(dev_mc); /* sets global node_nums */<br>-<br>- if (node_nums != 1)<br>- die("node_nums != 1. This is an SOC."<br>- " Something is terribly wrong.");<br> <br> /* Get max and actual number of cores */<br> pccount = cpuid_ecx(AMD_CPUID_ASIZE_PCCOUNT);<br>@@ -665,13 +614,12 @@<br> <br> for (j = 0 ; j <= siblings ; j++) {<br> apic_id = lapicid_start + j;<br>- printk(BIOS_SPEW, "lapicid_start 0x%x, node 0x%x, core 0x%x,"<br>- " apicid=0x%x\n", lapicid_start, node_nums,<br>- j, apic_id);<br>+ printk(BIOS_SPEW, "lapicid_start 0x%x, core 0x%x,"<br>+ " apicid=0x%x\n", lapicid_start, j, apic_id);<br> <br> cpu = add_cpu_device(cpu_bus, apic_id, enable_node);<br> if (cpu)<br>- amd_cpu_topology(cpu, node_nums, j);<br>+ amd_cpu_topology(cpu, 1, j);<br> }<br> }<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21495">change 21495</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21495"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a </div>
<div style="display:none"> Gerrit-Change-Number: 21495 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Marshall Dawson <marshalldawson3rd@gmail.com> </div>