<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21468">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82371eb: Consolidate bootblock.c logic<br><br>The southbridge bootblock entry point bootblock_southbridge_init()<br>just calls i82371eb_enable_rom() which does all the work. Move all<br>that code into bootblock_southbridge_init() and drop the second<br>function.<br><br>Plus combine the 3 lines that set 3 bits in XBCS into one.<br><br>Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>---<br>M src/southbridge/intel/i82371eb/bootblock.c<br>1 file changed, 2 insertions(+), 9 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21468/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/i82371eb/bootblock.c b/src/southbridge/intel/i82371eb/bootblock.c<br>index 07f94f3..6f52aa7 100644<br>--- a/src/southbridge/intel/i82371eb/bootblock.c<br>+++ b/src/southbridge/intel/i82371eb/bootblock.c<br>@@ -19,7 +19,7 @@<br> #include <device/pci_ids.h><br> #include "i82371eb.h"<br> <br>-static void i82371eb_enable_rom(void)<br>+static void bootblock_southbridge_init(void)<br> {<br>    u16 reg16;<br>    pci_devfn_t dev;<br>@@ -36,14 +36,7 @@<br> <br>       /* Enable access to the whole ROM, disable ROM write access. */<br>       reg16 = pci_read_config16(dev, XBCS);<br>-        reg16 |= LOWER_BIOS_ENABLE;<br>-  reg16 |= EXT_BIOS_ENABLE;<br>-    reg16 |= EXT_BIOS_ENABLE_1MB;<br>+        reg16 |= (LOWER_BIOS_ENABLE | EXT_BIOS_ENABLE | EXT_BIOS_ENABLE_1MB);<br>         reg16 &= ~(WRITE_PROTECT_ENABLE);   /* Disable ROM write access. */<br>       pci_write_config16(dev, XBCS, reg16);<br>-}<br>-<br>-static void bootblock_southbridge_init(void)<br>-{<br>-      i82371eb_enable_rom();<br> }<br></pre><p>To view, visit <a href="https://review.coreboot.org/21468">change 21468</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21468"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I07a5a28c91da9586e3bdaaf4521cba3f53a5cc01 </div>
<div style="display:none"> Gerrit-Change-Number: 21468 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>