<p>Nathaniel Roach has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21466">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/bd82x6x: Add Awareness of ME's AltDisable<br><br>me_cleaner now allows setting a bit in the PCH<br>straps - AltDisableBit tells the ME to stop<br>execution after BUP - disabling the 30 minute<br>watchdog - but also "breaking" the ME. The ME<br>reports OpMode = 2.<br><br>This means the ME will not respond when we wait<br>for an acknowledgement about the DRAM being ready.<br><br>Change the label for OpMode = 2 from DEBUG to<br>DISABLE, and when DISABLEd, don't wait for a response<br>to the DRAM notification.<br><br>Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa<br>Signed-off-by: Nathaniel Roach <nroach44@gmail.com><br>---<br>M src/southbridge/intel/bd82x6x/early_me.c<br>M src/southbridge/intel/bd82x6x/me.c<br>M src/southbridge/intel/bd82x6x/me.h<br>M src/southbridge/intel/bd82x6x/me_8.x.c<br>4 files changed, 16 insertions(+), 12 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/21466/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c<br>index b2e9200..48595ee 100644<br>--- a/src/southbridge/intel/bd82x6x/early_me.c<br>+++ b/src/southbridge/intel/bd82x6x/early_me.c<br>@@ -191,18 +191,22 @@<br>   meDID = did.uma_base | (1 << 28);// | (1 << 23);<br>  pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_ME_H_GS, meDID);<br> <br>-      timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);<br>-   udelay(1100);<br>-<br>      /* Must wait for ME acknowledgement */<br>-       millisec = 0;<br>-        hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;<br>-     while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) {<br>-            udelay(1000);<br>+        if (opmode == ME_HFS_MODE_DISABLED) {<br>+                printk(BIOS_NOTICE, "ME: ME is reporting as disabled, so not waiting for a response.\n");<br>+  } else {<br>+             timestamp_add_now(TS_ME_INFORM_DRAM_WAIT);<br>+           udelay(1100);<br>+                millisec = 0;<br>                 hfs = (pci_read_config32(PCI_DEV(0, 0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;<br>-             millisec++;<br>+          while ((((hfs & 0xf0) >> 4) != ME_HFS_BIOS_DRAM_ACK) && (millisec < 5000)) {<br>+                    udelay(1000);<br>+                        hfs = (pci_read_config32(PCI_DEV(0, b617e32bb99af608b7609583815e876d348025ac0x16, 0), PCI_ME_HFS) & 0xfe000000) >> 24;<br>+                     millisec++;<br>+          }<br>+            timestamp_add_now(TS_ME_INFORM_DRAM_DONE);<br>    }<br>-    timestamp_add_now(TS_ME_INFORM_DRAM_DONE);<br>+<br> <br>      me_fws2 = pci_read_config32(PCI_DEV(0, 0x16, 0), 0x48);<br>       printk(BIOS_NOTICE, "ME: FWS2: 0x%x\n", me_fws2);<br>diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c<br>index 70ba301..433f864 100644<br>--- a/src/southbridge/intel/bd82x6x/me.c<br>+++ b/src/southbridge/intel/bd82x6x/me.c<br>@@ -576,7 +576,7 @@<br>     switch (hfs.operation_mode) {<br>         case ME_HFS_MODE_NORMAL:<br>              break;<br>-       case ME_HFS_MODE_DEBUG:<br>+      case ME_HFS_MODE_DISABLED:<br>    case ME_HFS_MODE_DIS:<br>         case ME_HFS_MODE_OVER_JMPR:<br>   case ME_HFS_MODE_OVER_MEI:<br>diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h<br>index f95a0b4..39bfabb 100644<br>--- a/src/southbridge/intel/bd82x6x/me.h<br>+++ b/src/southbridge/intel/bd82x6x/me.h<br>@@ -49,7 +49,7 @@<br> #define  ME_HFS_ERROR_IMAGE    3<br> #define  ME_HFS_ERROR_DEBUG 4<br> #define  ME_HFS_MODE_NORMAL 0<br>-#define  ME_HFS_MODE_DEBUG  2<br>+#define  ME_HFS_MODE_DISABLED       2<br> #define  ME_HFS_MODE_DIS    3<br> #define  ME_HFS_MODE_OVER_JMPR      4<br> #define  ME_HFS_MODE_OVER_MEI       5<br>diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c<br>index 2e29233..5a9b60a 100644<br>--- a/src/southbridge/intel/bd82x6x/me_8.x.c<br>+++ b/src/southbridge/intel/bd82x6x/me_8.x.c<br>@@ -556,7 +556,7 @@<br>       switch (hfs.operation_mode) {<br>         case ME_HFS_MODE_NORMAL:<br>              break;<br>-       case ME_HFS_MODE_DEBUG:<br>+      case ME_HFS_MODE_DISABLED:<br>    case ME_HFS_MODE_DIS:<br>         case ME_HFS_MODE_OVER_JMPR:<br>   case ME_HFS_MODE_OVER_MEI:<br></pre><p>To view, visit <a href="https://review.coreboot.org/21466">change 21466</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21466"/><meta itemprop=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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa </div>
<div style="display:none"> Gerrit-Change-Number: 21466 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nathaniel Roach <nroach44@gmail.com> </div>