<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21411">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add serialio device config<br><br>Add SerialIO device mode configuration, device mode definition mirrored<br>from FSP.<br><br>Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/chip.c<br>M src/soc/intel/cannonlake/chip.h<br>A src/soc/intel/cannonlake/include/soc/serialio.h<br>3 files changed, 154 insertions(+), 34 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/21411/6</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c<br>index bee2517..3c6451d 100644<br>--- a/src/soc/intel/cannonlake/chip.c<br>+++ b/src/soc/intel/cannonlake/chip.c<br>@@ -24,6 +24,55 @@<br> #include <soc/ramstage.h><br> #include <string.h><br> <br>+static void parse_devicetree(FSP_S_CONFIG *params)<br>+{<br>+ struct device *dev = SA_DEV_ROOT;<br>+ const config_t *config = dev->chip_info;<br>+<br>+ int SerialIoDev[PchSerialIoIndexMAX] = {<br>+ PCH_DEVFN_I2C0,<br>+ PCH_DEVFN_I2C1,<br>+ PCH_DEVFN_I2C2,<br>+ PCH_DEVFN_I2C3,<br>+ PCH_DEVFN_I2C4,<br>+ PCH_DEVFN_I2C5,<br>+ PCH_DEVFN_GSPI0,<br>+ PCH_DEVFN_GSPI1,<br>+ PCH_DEVFN_GSPI2,<br>+ PCH_DEVFN_UART0,<br>+ PCH_DEVFN_UART1,<br>+ PCH_DEVFN_UART2<br>+ };<br>+<br>+ if (!dev) {<br>+ printk(BIOS_ERR, "Could not find root device\n");<br>+ return;<br>+ }<br>+ /* Only disable bus 0 devices. */<br>+ for (dev = dev->bus->children; dev; dev = dev->sibling) {<br>+ for (int i = 0; i < PchSerialIoIndexMAX; i++) {<br>+ if ((dev->path.pci.devfn) == SerialIoDev[i]) {<br>+ if (!dev->enabled) {<br>+ params->SerialIoDevMode[i] =<br>+ PchSerialIoDisabled;<br>+ break;<br>+ } else {<br>+ params->SerialIoDevMode[i] =<br>+ PchSerialIoPci;<br>+ if (config->SerialIoDevMode[i] ==<br>+ PchSerialIoAcpi<br>+ || config->SerialIoDevMode[i] ==<br>+ PchSerialIoHidden)<br>+ params->SerialIoDevMode[i] =<br>+ config->SerialIoDevMode[i];<br>+ break;<br>+ }<br>+<br>+ }<br>+ }<br>+ }<br>+}<br>+<br> void soc_init_pre_device(void *chip_info)<br> {<br> /* Perform silicon specific init. */<br>@@ -36,17 +85,17 @@<br> }<br> <br> static struct device_operations pci_domain_ops = {<br>- .read_resources = &pci_domain_read_resources,<br>- .set_resources = &pci_domain_set_resources,<br>- .scan_bus = &pci_domain_scan_bus,<br>- .ops_pci_bus = &pci_bus_default_ops,<br>+ .read_resources = &pci_domain_read_resources,<br>+ .set_resources = &pci_domain_set_resources,<br>+ .scan_bus = &pci_domain_scan_bus,<br>+ .ops_pci_bus = &pci_bus_default_ops,<br> };<br> <br> static struct device_operations cpu_bus_ops = {<br>- .read_resources = DEVICE_NOOP,<br>- .set_resources = DEVICE_NOOP,<br>+ .read_resources = DEVICE_NOOP,<br>+ .set_resources = DEVICE_NOOP,<br> .enable_resources = DEVICE_NOOP,<br>- .init = DEVICE_NOOP,<br>+ .init = DEVICE_NOOP,<br> };<br> <br> static void soc_enable(device_t dev)<br>@@ -60,8 +109,8 @@<br> <br> struct chip_operations soc_intel_cannonlake_ops = {<br> CHIP_NAME("Intel Cannonlake")<br>- .enable_dev = &soc_enable,<br>- .init = &soc_init_pre_device,<br>+ .enable_dev = &soc_enable,<br>+ .init = &soc_init_pre_device,<br> };<br> <br> /* UPD parameters to be initialized before SiliconInit */<br>@@ -71,6 +120,9 @@<br> FSP_S_CONFIG *params = &supd->FspsConfig;<br> const struct device *dev = SA_DEV_ROOT;<br> const config_t *config = dev->chip_info;<br>+<br>+ /* Parse device tree and disable unused device */<br>+ parse_devicetree(params);<br> <br> /* Set USB OC pin to 0 first */<br> for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) {<br>@@ -88,9 +140,9 @@<br> params->SataMode = config->SataMode;<br> params->SataSalpSupport = config->SataSalpSupport;<br> memcpy(params->SataPortsEnable, config->SataPortsEnable,<br>- sizeof(params->SataPortsEnable));<br>+ sizeof(params->SataPortsEnable));<br> memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,<br>- sizeof(params->SataPortsDevSlp));<br>+ sizeof(params->SataPortsDevSlp));<br> <br> /* Lan */<br> params->PchLanEnable = config->PchLanEnable;<br>@@ -101,18 +153,13 @@<br> <br> /* USB */<br> for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {<br>- params->PortUsb20Enable[i] =<br>- config->usb2_ports[i].enable;<br>- params->Usb2OverCurrentPin[i] =<br>- config->usb2_ports[i].ocpin;<br>- params->Usb2AfePetxiset[i] =<br>- config->usb2_ports[i].pre_emp_bias;<br>- params->Usb2AfeTxiset[i] =<br>- config->usb2_ports[i].tx_bias;<br>+ params->PortUsb20Enable[i] = config->usb2_ports[i].enable;<br>+ params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;<br>+ params->Usb2AfePetxiset[i] = config->usb2_ports[i].pre_emp_bias;<br>+ params->Usb2AfeTxiset[i] = config->usb2_ports[i].tx_bias;<br> params->Usb2AfePredeemp[i] =<br>- config->usb2_ports[i].tx_emp_enable;<br>- params->Usb2AfePehalfbit[i] =<br>- config->usb2_ports[i].pre_emp_bit;<br>+ config->usb2_ports[i].tx_emp_enable;<br>+ params->Usb2AfePehalfbit[i] = config->usb2_ports[i].pre_emp_bit;<br> }<br> <br> for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {<br>@@ -121,12 +168,12 @@<br> if (config->usb3_ports[i].tx_de_emp) {<br> params->Usb3HsioTxDeEmphEnable[i] = 1;<br> params->Usb3HsioTxDeEmph[i] =<br>- config->usb3_ports[i].tx_de_emp;<br>+ config->usb3_ports[i].tx_de_emp;<br> }<br> if (config->usb3_ports[i].tx_downscale_amp) {<br> params->Usb3HsioTxDownscaleAmpEnable[i] = 1;<br> params->Usb3HsioTxDownscaleAmp[i] =<br>- config->usb3_ports[i].tx_downscale_amp;<br>+ config->usb3_ports[i].tx_downscale_amp;<br> }<br> }<br> <br>@@ -150,7 +197,8 @@<br> }<br> <br> /* Mainboard GPIO Configuration */<br>-__attribute__((weak)) void mainboard_silicon_init_params(FSP_S_CONFIG *params)<br>+__attribute__ ((weak))<br>+void mainboard_silicon_init_params(FSP_S_CONFIG *params)<br> {<br> printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);<br> }<br>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h<br>index 0ed41fc..a48b7fa 100644<br>--- a/src/soc/intel/cannonlake/chip.h<br>+++ b/src/soc/intel/cannonlake/chip.h<br>@@ -20,6 +20,8 @@<br> <br> #include <intelblocks/gspi.h><br> #include <stdint.h><br>+#include <soc/pci_devs.h><br>+#include <soc/serialio.h><br> #include <soc/usb.h><br> #include <soc/vr_config.h><br> <br>@@ -39,16 +41,16 @@<br> uint8_t pirqh_routing;<br> <br> /* GPE configuration */<br>- uint32_t gpe0_en_1; /* GPE0_EN_31_0 */<br>- uint32_t gpe0_en_2; /* GPE0_EN_63_32 */<br>- uint32_t gpe0_en_3; /* GPE0_EN_95_64 */<br>- uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */<br>+ uint32_t gpe0_en_1; /* GPE0_EN_31_0 */<br>+ uint32_t gpe0_en_2; /* GPE0_EN_63_32 */<br>+ uint32_t gpe0_en_3; /* GPE0_EN_95_64 */<br>+ uint32_t gpe0_en_4; /* GPE0_EN_127_96 / GPE_STD */<br> <br> /* Gpio group routed to each dword of the GPE0 block. Values are<br> * of the form GPP_[A:G] or GPD. */<br>- uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */<br>- uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */<br>- uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */<br>+ uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */<br>+ uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */<br>+ uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */<br> <br> /* Generic IO decode ranges */<br> uint32_t gen1_dec;<br>@@ -161,8 +163,10 @@<br> uint8_t TcoIrqEnable;<br> <br> enum {<br>- CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */<br>- CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */<br>+ /* FSP handles locking per UPDs */<br>+ CHIPSET_LOCKDOWN_FSP = 0,<br>+ /* coreboot handles locking */<br>+ CHIPSET_LOCKDOWN_COREBOOT,<br> } chipset_lockdown;<br> <br> uint8_t FspSkipMpInit;<br>@@ -194,6 +198,31 @@<br> * 0x02000000 - 32MiB and beyond<br> */<br> uint32_t PrmrrSize;<br>+<br>+ /*<br>+ * SerialIO device mode selection:<br>+ *<br>+ * Device index:<br>+ * PchSerialIoIndexI2C0<br>+ * PchSerialIoIndexI2C1<br>+ * PchSerialIoIndexI2C2<br>+ * PchSerialIoIndexI2C3<br>+ * PchSerialIoIndexI2C4<br>+ * PchSerialIoIndexI2C5<br>+ * PchSerialIoIndexSPI0<br>+ * PchSerialIoIndexSPI1<br>+ * PchSerialIoIndexSPI2<br>+ * PchSerialIoIndexUART0<br>+ * PchSerialIoIndexUART1<br>+ * PchSerialIoIndexUART2<br>+ *<br>+ * Mode select:<br>+ * PchSerialIoDisabled<br>+ * PchSerialIoPci<br>+ * PchSerialIoAcpi<br>+ * PchSerialIoHidden<br>+ */<br>+ uint8_t SerialIoDevMode[PchSerialIoIndexMAX];<br> };<br> <br> typedef struct soc_intel_cannonlake_config config_t;<br>diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h<br>new file mode 100644<br>index 0000000..e152770<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/include/soc/serialio.h<br>@@ -0,0 +1,43 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Google Inc.<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef _SERIALIO_H_<br>+#define _SERIALIO_H_<br>+<br>+typedef enum {<br>+ PchSerialIoDisabled,<br>+ PchSerialIoPci,<br>+ PchSerialIoAcpi,<br>+ PchSerialIoHidden,<br>+} PCH_SERIAL_IO_MODE;<br>+<br>+typedef enum {<br>+ PchSerialIoIndexI2C0,<br>+ PchSerialIoIndexI2C1,<br>+ PchSerialIoIndexI2C2,<br>+ PchSerialIoIndexI2C3,<br>+ PchSerialIoIndexI2C4,<br>+ PchSerialIoIndexI2C5,<br>+ PchSerialIoIndexSPI0,<br>+ PchSerialIoIndexSPI1,<br>+ PchSerialIoIndexSPI2,<br>+ PchSerialIoIndexUART0,<br>+ PchSerialIoIndexUART1,<br>+ PchSerialIoIndexUART2,<br>+ PchSerialIoIndexMAX<br>+} PCH_SERIAL_IO_CONTROLLER;<br>+<br>+#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/21411">change 21411</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21411"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I7009120d69646cf60cb5a622e438ae1eeb6498cf </div>
<div style="display:none"> Gerrit-Change-Number: 21411 </div>
<div style="display:none"> Gerrit-PatchSet: 6 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: AndreX Andraos <andrex.andraos@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: John Zhao <john.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Shaunak Saha <shaunak.saha@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar@intel.com> </div>