<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21412">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add ramstage uart debug support<br><br>Using fixed resources for LPSS uart devices for debugging purpose.<br><br>Change-Id: Ib773e01d5f5358f13297400075d6920793200b88<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/Makefile.inc<br>A src/soc/intel/cannonlake/uart_pch.c<br>2 files changed, 55 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/21412/2</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index eece8f6..66abbe9 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -38,6 +38,7 @@<br> ramstage-y += spi.c<br> ramstage-y += systemagent.c<br> ramstage-$(CONFIG_UART_DEBUG) += uart.c<br>+ramstage-$(CONFIG_UART_DEBUG) += uart_pch.c<br> ramstage-y += vr_config.c<br> <br> postcar-y += memmap.c<br>diff --git a/src/soc/intel/cannonlake/uart_pch.c b/src/soc/intel/cannonlake/uart_pch.c<br>new file mode 100644<br>index 0000000..5aa0416<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/uart_pch.c<br>@@ -0,0 +1,54 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Google Inc.<br>+ * Copyright (C) 2017 Intel Corporation<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <cbmem.h><br>+#include <device/pci.h><br>+#include <intelblocks/uart.h><br>+#include <soc/iomap.h><br>+#include <soc/nvs.h><br>+#include <soc/pci_devs.h><br>+<br>+#if !ENV_SMM<br>+void pch_uart_read_resources(struct device *dev)<br>+{<br>+ pci_dev_read_resources(dev);<br>+<br>+ /* Set the configured UART base address for the debug port */<br>+ if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) {<br>+ struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);<br>+ /* Need to set the base and size for the resource allocator. */<br>+ res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE);<br>+ res->size = UART_DEBUG_BASE_0_SIZE;<br>+ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |<br>+ IORESOURCE_FIXED;<br>+ }<br>+}<br>+#endif<br>+<br>+bool pch_uart_init_debug_controller_on_resume(void)<br>+{<br>+ global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);<br>+<br>+ if (gnvs)<br>+ return !!gnvs->uior;<br>+<br>+ return false;<br>+}<br>+<br>+device_t pch_uart_get_debug_controller(void)<br>+{<br>+ return PCH_DEV_UART2;<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21412">change 21412</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21412"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib773e01d5f5358f13297400075d6920793200b88 </div>
<div style="display:none"> Gerrit-Change-Number: 21412 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Andrex Andraos <andrex.andraos@intel.corp-partner.google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Bora Guvendik <bora.guvendik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: John Zhao <john.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Shaunak Saha <shaunak.saha@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Vaibhav Shankar <vaibhav.shankar@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>