<p>Wisley Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21453">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/soraka: Update DPTF parameters<br><br>Cloned from baseboard/dptf.asl and update the parameters for soraka.<br><br>1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points.<br> CPU: passive point:85, critial point:100<br> TSR0: passive point:55, critial point:65<br> TSR1: passive point:58, critial point:70<br> TSR2: passive point:60, critial point:75<br> TSR3: passive point:60, critial point:75<br><br>2. Set PL1 Max to 7W, and PL1 Min 4.5W<br><br>3. Change sampling period of thermal relationship table (TRT) setting<br> CPU: 5 seconds<br> TSR0: 30 seconds<br> TSR1: 30 seconds<br> TSR2: 8 seconds<br> TSR3: 8 Seconds<br><br>BUG=b:65467566<br>TEST=build, boot on soraka, and verified by thermal team.<br>Signed-off-by: Wisley Chen <wisley.chen@quantatw.com><br><br>Change-Id: I6af93fa358a037df2088213ee4df5e2cfd047590<br>---<br>M src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl<br>1 file changed, 78 insertions(+), 3 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/21453/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl<br>index a9ec742..ac3e4da 100644<br>--- a/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl<br>+++ b/src/mainboard/google/poppy/variants/soraka/include/variant/acpi/dptf.asl<br>@@ -1,7 +1,8 @@<br> /*<br> * This file is part of the coreboot project.<br> *<br>- * Copyright 2017 Google Inc.<br>+ * Copyright (C) 2016 Google Inc.<br>+ * Copyright (C) 2017 Intel Corporation.<br> *<br> * This program is free software; you can redistribute it and/or modify<br> * it under the terms of the GNU General Public License as published by<br>@@ -9,8 +10,82 @@<br> *<br> * This program is distributed in the hope that it will be useful,<br> * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br> * GNU General Public License for more details.<br> */<br> <br>-#include <baseboard/acpi/dptf.asl><br>+#define DPTF_CPU_PASSIVE 85 <br>+#define DPTF_CPU_CRITICAL 100<br>+<br>+#define DPTF_TSR0_SENSOR_ID 1<br>+#define DPTF_TSR0_SENSOR_NAME "Ambient"<br>+#define DPTF_TSR0_PASSIVE 55<br>+#define DPTF_TSR0_CRITICAL 65<br>+<br>+#define DPTF_TSR1_SENSOR_ID 2<br>+#define DPTF_TSR1_SENSOR_NAME "Charger"<br>+#define DPTF_TSR1_PASSIVE 58<br>+#define DPTF_TSR1_CRITICAL 70<br>+<br>+#define DPTF_TSR2_SENSOR_ID 3<br>+#define DPTF_TSR2_SENSOR_NAME "DRAM"<br>+#define DPTF_TSR2_PASSIVE 60<br>+#define DPTF_TSR2_CRITICAL 75<br>+<br>+#define DPTF_TSR3_SENSOR_ID 4<br>+#define DPTF_TSR3_SENSOR_NAME "eMMC"<br>+#define DPTF_TSR3_PASSIVE 60<br>+#define DPTF_TSR3_CRITICAL 75<br>+<br>+#define DPTF_ENABLE_CHARGER<br>+<br>+/* Charger performance states, board-specific values from charger and EC */<br>+Name (CHPS, Package () {<br>+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */<br>+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */<br>+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */<br>+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */<br>+})<br>+<br>+Name (DTRT, Package () {<br>+ /* CPU Throttle Effect on CPU */<br>+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },<br>+<br>+ /* CPU Throttle Effect on Ambient (TSR0) */<br>+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 300, 0, 0, 0, 0 },<br>+<br>+#ifdef DPTF_ENABLE_CHARGER<br>+ /* Charger Throttle Effect on Charger (TSR1) */<br>+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 300, 0, 0, 0, 0 },<br>+#endif<br>+<br>+ /* CPU Throttle Effect on DRAM (TSR2) */<br>+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 80, 0, 0, 0, 0 },<br>+<br>+ /* CPU Throttle Effect on eMMC (TSR3) */<br>+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 80, 0, 0, 0, 0 },<br>+})<br>+<br>+Name (MPPC, Package ()<br>+{<br>+ 0x2, /* Revision */<br>+ Package () { /* Power Limit 1 */<br>+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */<br>+ 4500, /* PowerLimitMinimum */<br>+ 7000, /* PowerLimitMaximum */<br>+ 1000, /* TimeWindowMinimum */<br>+ 1000, /* TimeWindowMaximum */<br>+ 200 /* StepSize */<br>+ },<br>+ Package () { /* Power Limit 2 */<br>+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */<br>+ 15000, /* PowerLimitMinimum */<br>+ 15000, /* PowerLimitMaximum */<br>+ 1000, /* TimeWindowMinimum */<br>+ 1000, /* TimeWindowMaximum */<br>+ 1000 /* StepSize */<br>+ }<br>+})<br>+<br>+/* Include DPTF */<br>+#include <soc/intel/skylake/acpi/dptf/dptf.asl><br></pre><p>To view, visit <a href="https://review.coreboot.org/21453">change 21453</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I6af93fa358a037df2088213ee4df5e2cfd047590 </div>
<div style="display:none"> Gerrit-Change-Number: 21453 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Wisley Chen <wisley.chen@quantatw.com> </div>