<p>Anuj Mittal would like Boon Tiong Teo to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/21436">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/saddlebrook: add support for Saddle Brook<br><br>Saddle Brook is a reference board for Skylake SOC and has DDR4.<br><br>Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e<br>Signed-off-by: Anuj Mittal <anujx.mittal@intel.com><br>Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com><br>---<br>A src/mainboard/intel/saddlebrook/Kconfig<br>A src/mainboard/intel/saddlebrook/Kconfig.name<br>A src/mainboard/intel/saddlebrook/Makefile.inc<br>A src/mainboard/intel/saddlebrook/acpi/ec.asl<br>A src/mainboard/intel/saddlebrook/acpi/mainboard.asl<br>A src/mainboard/intel/saddlebrook/acpi/superio.asl<br>A src/mainboard/intel/saddlebrook/acpi_tables.c<br>A src/mainboard/intel/saddlebrook/board_info.txt<br>A src/mainboard/intel/saddlebrook/bootblock.c<br>A src/mainboard/intel/saddlebrook/cmos.layout<br>A src/mainboard/intel/saddlebrook/devicetree.cb<br>A src/mainboard/intel/saddlebrook/dsdt.asl<br>A src/mainboard/intel/saddlebrook/gpio.h<br>A src/mainboard/intel/saddlebrook/mainboard.c<br>A src/mainboard/intel/saddlebrook/pei_data.c<br>A src/mainboard/intel/saddlebrook/ramstage.c<br>A src/mainboard/intel/saddlebrook/romstage.c<br>A src/mainboard/intel/saddlebrook/smihandler.c<br>A src/mainboard/intel/saddlebrook/spd/Makefile.inc<br>A src/mainboard/intel/saddlebrook/spd/spd.h<br>A src/mainboard/intel/saddlebrook/spd/spd_util.c<br>21 files changed, 1,237 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/21436/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig<br>new file mode 100644<br>index 0000000..fac2a29<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/Kconfig<br>@@ -0,0 +1,52 @@<br>+if BOARD_INTEL_SKLSDLBRK<br>+<br>+config BOARD_SPECIFIC_OPTIONS # dummy<br>+ def_bool y<br>+ select BOARD_ROMSIZE_KB_4096<br>+ select CONSOLE_SERIAL<br>+ select DRIVERS_UART<br>+ select GENERIC_SPD_BIN<br>+ select HAVE_ACPI_RESUME<br>+ select HAVE_ACPI_TABLES<br>+ select HAVE_OPTION_TABLE<br>+ select HAVE_SMI_HANDLER<br>+ select SERIRQ_CONTINUOUS_MODE<br>+ select SKYLAKE_SOC_PCH_H<br>+ select SOC_INTEL_SKYLAKE<br>+ select SUPERIO_NUVOTON_NCT6776<br>+ select SUPERIO_NUVOTON_NCT6776_COM_A<br>+<br>+choice<br>+ prompt "FSP driver"<br>+ default SADDLEBROOK_USES_FSP1_1<br>+<br>+config SADDLEBROOK_USES_FSP1_1<br>+ bool "FSP driver 1.1"<br>+<br>+endchoice<br>+<br>+config IRQ_SLOT_COUNT<br>+ int<br>+ default 18<br>+<br>+config MAINBOARD_DIR<br>+ string<br>+ default "intel/saddlebrook"<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "Skylake Saddle Brook"<br>+<br>+config MAINBOARD_FAMILY<br>+ string<br>+ default "Intel_SaddleBrook"<br>+<br>+config MAX_CPUS<br>+ int<br>+ default 8<br>+<br>+config TPM_PIRQ<br>+ hex<br>+ default 0x18 # GPP_E0_IRQ<br>+<br>+endif<br>diff --git a/src/mainboard/intel/saddlebrook/Kconfig.name b/src/mainboard/intel/saddlebrook/Kconfig.name<br>new file mode 100644<br>index 0000000..c85fb81<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_INTEL_SKLSDLBRK<br>+ bool "Skylake Saddle Brook"<br>diff --git a/src/mainboard/intel/saddlebrook/Makefile.inc b/src/mainboard/intel/saddlebrook/Makefile.inc<br>new file mode 100644<br>index 0000000..305f0e4<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/Makefile.inc<br>@@ -0,0 +1,25 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2013 Google Inc.<br>+## Copyright (C) 2016 Intel Corporation.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+subdirs-y += spd<br>+<br>+bootblock-y += bootblock.c<br>+romstage-y += pei_data.c<br>+<br>+ramstage-y += mainboard.c<br>+ramstage-y += ramstage.c<br>+<br>+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c<br>diff --git a/src/mainboard/intel/saddlebrook/acpi/ec.asl b/src/mainboard/intel/saddlebrook/acpi/ec.asl<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/acpi/ec.asl<br>diff --git a/src/mainboard/intel/saddlebrook/acpi/mainboard.asl b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl<br>new file mode 100644<br>index 0000000..5174eeb<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/acpi/mainboard.asl<br>@@ -0,0 +1,17 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2016 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/gpio.h><br>diff --git a/src/mainboard/intel/saddlebrook/acpi/superio.asl b/src/mainboard/intel/saddlebrook/acpi/superio.asl<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/acpi/superio.asl<br>diff --git a/src/mainboard/intel/saddlebrook/acpi_tables.c b/src/mainboard/intel/saddlebrook/acpi_tables.c<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/acpi_tables.c<br>diff --git a/src/mainboard/intel/saddlebrook/board_info.txt b/src/mainboard/intel/saddlebrook/board_info.txt<br>new file mode 100644<br>index 0000000..d3295d9<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/board_info.txt<br>@@ -0,0 +1,6 @@<br>+Vendor name: Intel<br>+Board name: Saddle Brook Skylake Reference Board<br>+Category: eval<br>+ROM protocol: SPI<br>+ROM socketed: n<br>+Flashrom support: y<br>diff --git a/src/mainboard/intel/saddlebrook/bootblock.c b/src/mainboard/intel/saddlebrook/bootblock.c<br>new file mode 100644<br>index 0000000..4bb2433<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/bootblock.c<br>@@ -0,0 +1,44 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2016 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <bootblock_common.h><br>+#include <soc/gpio.h><br>+#include "gpio.h"<br>+<br>+#if IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776)<br>+#include "superio/nuvoton/common/nuvoton.h"<br>+#include <superio/nuvoton/nct6776/nct6776.h><br>+<br>+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)<br>+#endif<br>+<br>+static void early_config_gpio(void)<br>+{<br>+ /* This is a hack for FSP because it does things in MemoryInit()<br>+ * which it shouldn't do. We have to prepare certain gpios here<br>+ * because of the brokenness in FSP. */<br>+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));<br>+}<br>+<br>+void bootblock_mainboard_init(void)<br>+{<br>+ early_config_gpio();<br>+}<br>+<br>+void bootblock_mainboard_early_init(void)<br>+{<br>+ if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776))<br>+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>+}<br>diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout<br>new file mode 100644<br>index 0000000..e6d8acc<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/cmos.layout<br>@@ -0,0 +1,133 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2007-2008 coresystems GmbH<br>+## Copyright (C) 2016 Intel Corporation.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+# -----------------------------------------------------------------<br>+entries<br>+<br>+#start-bit length config config-ID name<br>+#0 8 r 0 seconds<br>+#8 8 r 0 alarm_seconds<br>+#16 8 r 0 minutes<br>+#24 8 r 0 alarm_minutes<br>+#32 8 r 0 hours<br>+#40 8 r 0 alarm_hours<br>+#48 8 r 0 day_of_week<br>+#56 8 r 0 day_of_month<br>+#64 8 r 0 month<br>+#72 8 r 0 year<br>+# -----------------------------------------------------------------<br>+# Status Register A<br>+#80 4 r 0 rate_select<br>+#84 3 r 0 REF_Clock<br>+#87 1 r 0 UIP<br>+# -----------------------------------------------------------------<br>+# Status Register B<br>+#88 1 r 0 auto_switch_DST<br>+#89 1 r 0 24_hour_mode<br>+#90 1 r 0 binary_values_enable<br>+#91 1 r 0 square-wave_out_enable<br>+#92 1 r 0 update_finished_enable<br>+#93 1 r 0 alarm_interrupt_enable<br>+#94 1 r 0 periodic_interrupt_enable<br>+#95 1 r 0 disable_clock_updates<br>+# -----------------------------------------------------------------<br>+# Status Register C<br>+#96 4 r 0 status_c_rsvd<br>+#100 1 r 0 uf_flag<br>+#101 1 r 0 af_flag<br>+#102 1 r 0 pf_flag<br>+#103 1 r 0 irqf_flag<br>+# -----------------------------------------------------------------<br>+# Status Register D<br>+#104 7 r 0 status_d_rsvd<br>+#111 1 r 0 valid_cmos_ram<br>+# -----------------------------------------------------------------<br>+# Diagnostic Status Register<br>+#112 8 r 0 diag_rsvd1<br>+<br>+# -----------------------------------------------------------------<br>+0 120 r 0 reserved_memory<br>+#120 264 r 0 unused<br>+<br>+# -----------------------------------------------------------------<br>+# RTC_BOOT_BYTE (coreboot hardcoded)<br>+384 1 e 4 boot_option<br>+388 4 h 0 reboot_counter<br>+#390 2 r 0 unused?<br>+<br>+# -----------------------------------------------------------------<br>+# coreboot config options: console<br>+392 3 e 5 baud_rate<br>+395 4 e 6 debug_level<br>+#399 1 r 0 unused<br>+<br>+# coreboot config options: cpu<br>+400 1 e 2 hyper_threading<br>+#401 7 r 0 unused<br>+<br>+# coreboot config options: southbridge<br>+408 1 e 1 nmi<br>+409 2 e 7 power_on_after_fail<br>+#411 5 r 0 unused<br>+<br>+# coreboot config options: bootloader<br>+#Used by ChromeOS:<br>+416 128 r 0 vbnv<br>+#544 440 r 0 unused<br>+<br>+# SandyBridge MRC Scrambler Seed values<br>+896 32 r 0 mrc_scrambler_seed<br>+928 32 r 0 mrc_scrambler_seed_s3<br>+<br>+# coreboot config options: check sums<br>+984 16 h 0 check_sum<br>+#1000 24 r 0 amd_reserved<br>+<br>+# -----------------------------------------------------------------<br>+<br>+enumerations<br>+<br>+#ID value text<br>+1 0 Disable<br>+1 1 Enable<br>+2 0 Enable<br>+2 1 Disable<br>+4 0 Fallback<br>+4 1 Normal<br>+5 0 115200<br>+5 1 57600<br>+5 2 38400<br>+5 3 19200<br>+5 4 9600<br>+5 5 4800<br>+5 6 2400<br>+5 7 1200<br>+6 1 Emergency<br>+6 2 Alert<br>+6 3 Critical<br>+6 4 Error<br>+6 5 Warning<br>+6 6 Notice<br>+6 7 Info<br>+6 8 Debug<br>+6 9 Spew<br>+7 0 Disable<br>+7 1 Enable<br>+7 2 Keep<br>+# -----------------------------------------------------------------<br>+checksums<br>+<br>+checksum 392 415 984<br>diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb<br>new file mode 100644<br>index 0000000..e9fcc60<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/devicetree.cb<br>@@ -0,0 +1,300 @@<br>+chip soc/intel/skylake<br>+<br>+ # Enable deep Sx states<br>+ register "deep_s5_enable_ac" = "0"<br>+ register "deep_s5_enable_dc" = "0"<br>+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"<br>+<br>+ # GPE configuration<br>+ # Note that GPE events called out in ASL code rely on this<br>+ # route. i.e. If this route changes then the affected GPE<br>+ # offset bits also need to be changed.<br>+ register "gpe0_dw0" = "GPP_B"<br>+ register "gpe0_dw1" = "GPP_D"<br>+ register "gpe0_dw2" = "GPP_E"<br>+<br>+ # EC host command range is in 0x800-0x8ff<br>+ register "gen1_dec" = "0x00fc0801"<br>+<br>+ # Enable "Intel Speed Shift Technology"<br>+ register "speed_shift_enable" = "1"<br>+<br>+ # Enable DPTF<br>+ register "dptf_enable" = "1"<br>+<br>+ # FSP Configuration<br>+ register "EnableAzalia" = "1"<br>+ register "DspEnable" = "1"<br>+ register "IoBufferOwnership" = "3"<br>+ register "SmbusEnable" = "1"<br>+ register "ScsEmmcEnabled" = "0"<br>+ register "ScsEmmcHs400Enabled" = "0"<br>+ register "ScsSdCardEnabled" = "0"<br>+ register "InternalGfx" = "1"<br>+ register "SkipExtGfxScan" = "1"<br>+ register "Device4Enable" = "0"<br>+ register "Heci3Enabled" = "0"<br>+<br>+ register "SaGv" = "3"<br>+ register "PmTimerDisabled" = "0"<br>+<br>+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch<br>+ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s<br>+ register "PmConfigSlpS3MinAssert" = "0x02"<br>+<br>+ # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s<br>+ register "PmConfigSlpS4MinAssert" = "0x04"<br>+<br>+ # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s<br>+ register "PmConfigSlpSusMinAssert" = "0x03"<br>+<br>+ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s<br>+ register "PmConfigSlpAMinAssert" = "0x03"<br>+<br>+ # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled<br>+ register "SerialIrqConfigSirqEnable" = "0x01"<br>+ register "SerialIrqConfigSirqMode" = "0x01"<br>+<br>+ # VR Settings Configuration for 5 Domains<br>+ #+----------------+-------+-------+-------------+-------------+-------+<br>+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |<br>+ #+----------------+-------+-------+-------------+-------------+-------+<br>+ #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |<br>+ #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |<br>+ #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |<br>+ #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |<br>+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |<br>+ #| ImonSlope | 0 | 0 | 0 | 0 | 0 |<br>+ #| ImonOffset | 0 | 0 | 0 | 0 | 0 |<br>+ #| IccMax | 7A | 34A | 34A | 35A | 35A |<br>+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |<br>+ #+----------------+-------+-------+-------------+-------------+-------+<br>+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{<br>+ .vr_config_enable = 1, \<br>+ .psi1threshold = 0x50, \<br>+ .psi2threshold = 0x10, \<br>+ .psi3threshold = 0x4, \<br>+ .psi3enable = 1, \<br>+ .psi4enable = 1, \<br>+ .imon_slope = 0x0, \<br>+ .imon_offset = 0x0, \<br>+ .icc_max = 0x1C, \<br>+ .voltage_limit = 0x5F0 \<br>+ }"<br>+<br>+ register "domain_vr_config[VR_IA_CORE]" = "{<br>+ .vr_config_enable = 1, \<br>+ .psi1threshold = 0x50, \<br>+ .psi2threshold = 0x14, \<br>+ .psi3threshold = 0x4, \<br>+ .psi3enable = 1, \<br>+ .psi4enable = 1, \<br>+ .imon_slope = 0x0, \<br>+ .imon_offset = 0x0, \<br>+ .icc_max = 0x88, \<br>+ .voltage_limit = 0x5F0 \<br>+ }"<br>+ register "domain_vr_config[VR_RING]" = "{<br>+ .vr_config_enable = 1, \<br>+ .psi1threshold = 0x50, \<br>+ .psi2threshold = 0x14, \<br>+ .psi3threshold = 0x4, \<br>+ .psi3enable = 1, \<br>+ .psi4enable = 1, \<br>+ .imon_slope = 0x0, \<br>+ .imon_offset = 0x0, \<br>+ .icc_max = 0x88, \<br>+ .voltage_limit = 0x5F0, \<br>+ }"<br>+<br>+ register "domain_vr_config[VR_GT_UNSLICED]" = "{<br>+ .vr_config_enable = 1, \<br>+ .psi1threshold = 0x50, \<br>+ .psi2threshold = 0x14, \<br>+ .psi3threshold = 0x4, \<br>+ .psi3enable = 1, \<br>+ .psi4enable = 1, \<br>+ .imon_slope = 0x0, \<br>+ .imon_offset = 0x0, \<br>+ .icc_max = 0x8C ,\<br>+ .voltage_limit = 0x5F0 \<br>+ }"<br>+<br>+ register "domain_vr_config[VR_GT_SLICED]" = "{<br>+ .vr_config_enable = 1, \<br>+ .psi1threshold = 0x50, \<br>+ .psi2threshold = 0x14, \<br>+ .psi3threshold = 0x4, \<br>+ .psi3enable = 1, \<br>+ .psi4enable = 1, \<br>+ .imon_slope = 0x0, \<br>+ .imon_offset = 0x0, \<br>+ .icc_max = 0x8C, \<br>+ .voltage_limit = 0x5F0 \<br>+ }"<br>+<br>+ register "FspSkipMpInit" = "0"<br>+<br>+ # Enable x1 slot<br>+ register "PcieRpEnable[7]" = "1"<br>+ register "PcieRpClkReqSupport[7]" = "1"<br>+ register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3<br>+<br>+ # Enable x4 slot<br>+ register "PcieRpEnable[8]" = "1"<br>+ register "PcieRpClkReqSupport[8]" = "1"<br>+ register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4<br>+<br>+ # Enable Root port 6 and 13.<br>+ register "PcieRpEnable[5]" = "1"<br>+ register "PcieRpEnable[12]" = "1"<br>+<br>+ # Enable CLKREQ#<br>+ register "PcieRpClkReqSupport[5]" = "1"<br>+ register "PcieRpClkReqSupport[12]" = "1"<br>+<br>+ # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2#<br>+ register "PcieRpClkReqNumber[5]" = "0"<br>+ register "PcieRpClkReqNumber[12]" = "1"<br>+<br>+ register EnableLan = "1"<br>+<br>+ # USB related<br>+ register "SsicPortEnable" = "1"<br>+ register "XdciEnable" = "0"<br>+<br>+ register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG<br>+ register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad<br>+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT<br>+ register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel<br>+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN<br>+ register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel<br>+ register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel<br>+ register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)<br>+ register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb)<br>+ register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK<br>+ register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK<br>+ register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor<br>+ register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn<br>+ register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn<br>+<br>+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG<br>+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN<br>+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex<br>+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM<br>+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK<br>+ register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel<br>+ register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel<br>+ register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn<br>+ register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn<br>+ register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK<br>+<br>+ register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V<br>+<br>+ # Must leave UART0 enabled or SD/eMMC will not work as PCI<br>+<br>+ register "pirqa_routing" = "0x0b"<br>+ register "pirqb_routing" = "0x0a"<br>+ register "pirqc_routing" = "0x0b"<br>+ register "pirqd_routing" = "0x0b"<br>+ register "pirqe_routing" = "0x0b"<br>+ register "pirqf_routing" = "0x0b"<br>+ register "pirqg_routing" = "0x0b"<br>+ register "pirqh_routing" = "0x0b"<br>+<br>+ register "PmTimerDisabled" = "0"<br>+<br>+ register "EnableSata" = "1"<br>+ register "SataSalpSupport" = "1"<br>+ register "SataPortsEnable" = "{ \<br>+ [0] = 1, \<br>+ [1] = 1, \<br>+ [2] = 1, \<br>+ [3] = 1, \<br>+ [4] = 1, \<br>+ [5] = 1, \<br>+ [6] = 1, \<br>+ [7] = 1, \<br>+ }"<br>+ register "SerialIoDevMode" = "{ \<br>+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \<br>+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \<br>+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \<br>+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \<br>+ [PchSerialIoIndexI2C4] = PchSerialIoPci, \<br>+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \<br>+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \<br>+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \<br>+ [PchSerialIoIndexUart0] = PchSerialIoPci, \<br>+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \<br>+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \<br>+ }"<br>+<br>+ # PL2 override 25W<br>+ register "tdp_pl2_override" = "25"<br>+<br>+ # Send an extra VR mailbox command for the PS4 exit issue<br>+ register "SendVrMbxCmd" = "2"<br>+<br>+ # Enable/Disable VMX feature<br>+ register "VmxEnable" = "0"<br>+ # Use default SD card detect GPIO configuration<br>+ #register "sdcard_cd_gpio_default" = "GPP_A7"<br>+<br>+ device cpu_cluster 0 on<br>+ device lapic 0 on end<br>+ end<br>+ device domain 0 on<br>+ device pci 00.0 on end # Host Bridge<br>+ device pci 02.0 on end # Integrated Graphics Device<br>+ device pci 14.0 on end # USB xHCI<br>+ device pci 14.1 off end # USB xDCI (OTG)<br>+ device pci 14.2 on end # Thermal Subsystem<br>+ device pci 15.0 on end # I2C #0<br>+ device pci 15.1 on end # I2C #1<br>+ device pci 15.2 on end # I2C #2<br>+ device pci 15.3 on end # I2C #3<br>+ device pci 16.0 on end # Management Engine Interface 1<br>+ device pci 16.1 off end # Management Engine Interface 2<br>+ device pci 16.2 off end # Management Engine IDE-R<br>+ device pci 16.3 off end # Management Engine KT Redirection<br>+ device pci 16.4 off end # Management Engine Interface 3<br>+ device pci 17.0 on end # SATA<br>+ device pci 19.0 on end # UART #2<br>+ device pci 19.1 on end # I2C #5<br>+ device pci 19.2 on end # I2C #4<br>+ device pci 1c.0 on end # PCI Express Port 1<br>+ device pci 1c.1 off end # PCI Express Port 2<br>+ device pci 1c.2 off end # PCI Express Port 3<br>+ device pci 1c.3 off end # PCI Express Port 4<br>+ device pci 1c.4 off end # PCI Express Port 5<br>+ device pci 1c.5 off end # PCI Express Port 6<br>+ device pci 1c.6 off end # PCI Express Port 7<br>+ device pci 1c.7 off end # PCI Express Port 8<br>+ device pci 1d.0 off end # PCI Express Port 9<br>+ device pci 1d.1 off end # PCI Express Port 10<br>+ device pci 1d.2 off end # PCI Express Port 11<br>+ device pci 1d.3 off end # PCI Express Port 12<br>+ device pci 1e.0 on end # UART #0<br>+ device pci 1e.1 on end # UART #1<br>+ device pci 1e.2 on end # GSPI #0<br>+ device pci 1e.3 on end # GSPI #1<br>+ device pci 1e.4 off end # eMMC<br>+ device pci 1e.5 off end # SDIO<br>+ device pci 1e.6 off end # SDCard<br>+ device pci 1f.0 on<br>+ #chip drivers/pc80/tpm<br>+ # device pnp 0c31.0 on end<br>+ #end<br>+ #chip ec/google/chromeec<br>+ # device pnp 0c09.0 on end<br>+ #end<br>+ end # LPC Interface<br>+ device pci 1f.1 on end # P2SB<br>+ device pci 1f.2 on end # Power Management Controller<br>+ device pci 1f.3 on end # Intel HDA<br>+ device pci 1f.4 on end # SMBus<br>+ device pci 1f.5 on end # PCH SPI<br>+ device pci 1f.6 on end # GbE<br>+ end<br>+end<br>diff --git a/src/mainboard/intel/saddlebrook/dsdt.asl b/src/mainboard/intel/saddlebrook/dsdt.asl<br>new file mode 100644<br>index 0000000..45d9a85<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/dsdt.asl<br>@@ -0,0 +1,49 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2015 Google Inc.<br>+ * Copyright (C) 2016 Intel Corporation<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+DefinitionBlock(<br>+ "dsdt.aml",<br>+ "DSDT",<br>+ 0x05, // DSDT revision: ACPI v5.0<br>+ "COREv4", // OEM id<br>+ "COREBOOT", // OEM table id<br>+ 0x20110725 // OEM revision<br>+)<br>+{<br>+ // Some generic macros<br>+ #include <soc/intel/skylake/acpi/platform.asl><br>+<br>+ // global NVS and variables<br>+ #include <soc/intel/skylake/acpi/globalnvs.asl><br>+<br>+ // CPU<br>+ #include <soc/intel/skylake/acpi/cpu.asl><br>+<br>+ Scope (\_SB) {<br>+ Device (PCI0)<br>+ {<br>+ #include <soc/intel/skylake/acpi/systemagent.asl><br>+ #include <soc/intel/skylake/acpi/pch.asl><br>+ }<br>+ }<br>+<br>+ // Chipset specific sleep states<br>+ #include <soc/intel/skylake/acpi/sleepstates.asl><br>+<br>+ // Mainboard specific<br>+ #include "acpi/mainboard.asl"<br>+}<br>diff --git a/src/mainboard/intel/saddlebrook/gpio.h b/src/mainboard/intel/saddlebrook/gpio.h<br>new file mode 100644<br>index 0000000..83e3759<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/gpio.h<br>@@ -0,0 +1,276 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2013 Google Inc.<br>+ * Copyright (C) 2015 Intel Corporation<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef MAINBOARD_GPIO_H<br>+#define MAINBOARD_GPIO_H<br>+<br>+#include <soc/gpe.h><br>+#include <soc/gpio.h><br>+<br>+/* EC in RW */<br>+#define GPIO_EC_IN_RW GPP_C6<br>+<br>+/* BIOS Flash Write Protect */<br>+#define GPIO_PCH_WP GPP_C23<br>+<br>+/* Memory configuration board straps */<br>+#define GPIO_MEM_CONFIG_0 GPP_C12<br>+#define GPIO_MEM_CONFIG_1 GPP_C13<br>+#define GPIO_MEM_CONFIG_2 GPP_C14<br>+#define GPIO_MEM_CONFIG_3 GPP_C15<br>+<br>+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */<br>+#define GPE_EC_WAKE GPE0_LAN_WAK<br>+<br>+/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */<br>+#define GPE_WLAN_WAKE GPE0_DW0_16<br>+<br>+/* Input device interrupt configuration */<br>+#define TOUCHPAD_INT_L GPP_B3_IRQ<br>+#define TOUCHSCREEN_INT_L GPP_E7_IRQ<br>+#define MIC_INT_L GPP_F10_IRQ<br>+<br>+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */<br>+#define EC_SCI_GPI GPE0_DW2_16<br>+#define EC_SMI_GPI GPP_E15<br>+<br>+#ifndef __ACPI__<br>+/* Pad configuration in ramstage. */<br>+static const struct pad_config gpio_table[] = {<br>+/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),<br>+/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),<br>+/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),<br>+/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),<br>+/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),<br>+/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),<br>+/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),<br>+/* PIRQA# */ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),<br>+/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),<br>+/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),<br>+/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),<br>+/* EC_HID_INT */ PAD_CFG_NF(GPP_A11, NONE, DEEP, NF1),<br>+/* ISH_KB_PROX_INT */ PAD_CFG_GPI(GPP_A12, NONE, DEEP),<br>+/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),<br>+/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),<br>+/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),<br>+/* SD_1P8_SEL */<br>+/* SD_PWR_EN */<br>+/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),<br>+/* ISH_GP1 */ /* GPP_A19 */<br>+/* GYRO_DRDY */<br>+/* FLIP_ACCEL_INT */<br>+/* GYRO_INT */<br>+/* ISH_GP5 */ /* GPP_A23 */<br>+<br>+/* CORE_VID0 */ /* GPP_B0 */<br>+/* CORE_VID1 */ /* GPP_B1 */<br>+/* HSJ_MIC_DET */<br>+/* TRACKPAD_INT */ PAD_CFG_GPO(GPP_B3, 1, DEEP),<br>+/* BT_RF_KILL */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1),<br>+/* SRCCLKREQ0# */ /* GPP_B5 */<br>+/* WIFI_CLK_REQ */<br>+/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),<br>+/* SRCCLKREQ3# */ /* GPP_B8 */<br>+/* SSD_CLK_REQ */<br>+/* SRCCLKREQ5# */ /* GPP_B10 */<br>+/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),<br>+/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),<br>+/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),<br>+/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1),<br>+/* GSPI0_CS# */ /* GPP_B15 */<br>+/* WLAN_PCIE_WAKE */<br>+/* SSD_PCIE_WAKE */ PAD_CFG_GPO(GPP_B17, 1, DEEP),<br>+/* GSPI0_MOSI */ /* GPP_B18 */<br>+/* CCODEC_SPI_CS */<br>+/* CODEC_SPI_CLK */<br>+/* CODEC_SPI_MISO */<br>+/* CODEC_SPI_MOSI */<br>+/* SM1ALERT# */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF1),<br>+<br>+/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),<br>+/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),<br>+/* SMBALERT# */ PAD_CFG_NF(GPP_C2, 20K_PD, DEEP, NF1),<br>+/* M2_WWAN_PWREN */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),<br>+/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),<br>+/* SML0ALERT# */ /* GPP_C5 */<br>+/* EC_IN_RW */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1),<br>+/* USB_CTL */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),<br>+/* UART0_RXD */ /* GPP_C8 */<br>+/* UART0_TXD */ /* GPP_C9 */<br>+/* NFC_RST* */<br>+/* EN_PP3300_KEPLER */<br>+/* PCH_MEM_CFG0 */<br>+/* PCH_MEM_CFG1 */<br>+/* PCH_MEM_CFG2 */<br>+/* PCH_MEM_CFG3 */<br>+/* I2C0_SDA */<br>+/* I2C0_SCL */<br>+/* I2C1_SDA */<br>+/* I2C1_SCL */<br>+/* GD_UART2_RXD */<br>+/* GD_UART2_TXD */<br>+/* TCH_PNL_PWREN */<br>+/* SPI_WP_STATUS */<br>+<br>+/* ITCH_SPI_CS */ /* GPP_D0 */<br>+/* ITCH_SPI_CLK */ /* GPP_D1 */<br>+/* ITCH_SPI_MISO_1 */ /* GPP_D2 */<br>+/* ITCH_SPI_MISO_0 */ /* GPP_D3 */<br>+/* CAM_FLASH_STROBE */<br>+/* EN_PP3300_DX_EMMC */<br>+/* EN_PP1800_DX_EMMC */<br>+/* SH_I2C1_SDA */<br>+/* SH_I2C1_SCL */<br>+/* TBD */<br>+/* USB_A0_ILIM_SEL */<br>+/* USB_A1_ILIM_SEL */<br>+/* EN_PP3300_DX_CAM */<br>+/* EN_PP1800_DX_AUDIO */<br>+/* ISH_UART0_TXD */ /* GPP_D14 */<br>+/* ISH_UART0_RTS */ /* GPP_D15 */<br>+/* ISH_UART0_CTS */ /* GPP_D16 */<br>+/* DMIC_CLK_1 */<br>+/* DMIC_DATA_1 */<br>+/* DMIC_CLK_0 */<br>+/* DMIC_DATA_0 */<br>+/* ITCH_SPI_D2 */ /* GPP_D21 */<br>+/* ITCH_SPI_D3 */ /* GPP_D22 */<br>+/* I2S_MCLK */<br>+<br>+/* SPI_TPM_IRQ */ PAD_CFG_NF(GPP_E0, NONE, DEEP, NF1),<br>+/* SATAXPCIE1 */ /* GPP_E1 */<br>+/* SSD_PEDET */<br>+/* CPU_GP0 */<br>+/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),<br>+/* SATA_DEVSLP1 */ /* GPP_E5 */<br>+/* SATA_DEVSLP2 */ /* GPP_E6 */<br>+/* TCH_PNL_INTR* */<br>+/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),<br>+/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),<br>+/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),<br>+/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),<br>+/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),<br>+<br>+/* I2S2_SCLK */<br>+/* I2S2_SFRM */<br>+/* I2S2_TXD */ PAD_CFG_GPO(GPP_F2, 0, DEEP),<br>+/* I2S2_RXD */<br>+/* I2C2_SDA */ /* GPP_F4 */<br>+/* I2C2_SCL */ /* GPP_F5 */<br>+/* I2C3_SDA */ /* GPP_F6 */<br>+/* I2C3_SCL */ /* GPP_F7 */<br>+/* I2C4_SDA */<br>+/* I2C4_SDA */<br>+/* AUDIO_IRQ */<br>+/* I2C5_SCL */ /* GPP_F11 */<br>+/* EMMC_CMD */ PAD_CFG_GPI(GPP_F12, NONE, DEEP),<br>+/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),<br>+/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),<br>+/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),<br>+/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),<br>+/* EMMC_DATA4 */ PAD_CFG_GPO(GPP_F17, 1, DEEP),<br>+/* EMMC_DATA5 */ PAD_CFG_GPO(GPP_F18, 1, DEEP),<br>+/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),<br>+/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),<br>+/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),<br>+/* EMMC_CLK */ PAD_CFG_GPO(GPP_F22, 1, DEEP),<br>+ /* GPP_F23 */<br>+<br>+/* SD_CMD */ /* GPP_G0 */<br>+/* SD_DATA0 */<br>+/* SD_DATA1 */<br>+/* SD_DATA2 */<br>+/* SD_DATA3 */<br>+/* SD_CD# */<br>+/* SD_CLK */<br>+/* SD_WP */<br>+/* TBD */ PAD_CFG_GPO(GPP_G8, 1, DEEP),<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */ PAD_CFG_GPI(GPP_G23, NONE, DEEP),<br>+<br>+/* SD_CMD */ /* GPP_H0 */<br>+/* SD_DATA0 */<br>+/* SD_DATA1 */<br>+/* SD_DATA2 */<br>+/* SD_DATA3 */<br>+/* SD_CD# */<br>+/* SD_CLK */<br>+/* SD_WP */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */<br>+/* TBD */ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),<br>+/* TBD */ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1),<br>+/* TBD */ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),<br>+/* TBD */ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),<br>+/* TBD */<br>+<br>+/* SD_CMD */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1),<br>+/* SD_CMD */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1),<br>+/* SD_CMD */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1),<br>+/* SD_CMD */ PAD_CFG_NF(GPP_I3, NONE, DEEP, NF1),<br>+/* SD_CMD */ PAD_CFG_NF(GPP_I4, NONE, DEEP, NF1),<br>+/* SD_CMD */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1),<br>+/* SD_CMD */ PAD_CFG_NF(GPP_I6, NONE, DEEP, NF1),<br>+/* SD_CMD */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1),<br>+/* SD_CMD */ PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1),<br>+/* SD_CMD */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1),<br>+/* SD_CMD */ PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1),<br>+<br>+/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),<br>+/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),<br>+/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),<br>+/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),<br>+/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),<br>+/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),<br>+/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),<br>+ /* GPD7 */<br>+/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),<br>+/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1),<br>+/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),<br>+/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),<br>+};<br>+<br>+/* Early pad configuration in romstage. */<br>+static const struct pad_config early_gpio_table[] = {<br>+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */<br>+/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */<br>+};<br>+<br>+#endif<br>+<br>+#endif<br>diff --git a/src/mainboard/intel/saddlebrook/mainboard.c b/src/mainboard/intel/saddlebrook/mainboard.c<br>new file mode 100644<br>index 0000000..07d3e8a<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/mainboard.c<br>@@ -0,0 +1,41 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2013 Google Inc.<br>+ * Copyright (C) 2016 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/acpi.h><br>+#include <console/console.h><br>+#include <device/device.h><br>+#include <gpio.h><br>+#include <stdlib.h><br>+#include <string.h><br>+#include <soc/nhlt.h><br>+<br>+static void mainboard_init(device_t dev)<br>+{<br>+}<br>+<br>+/*<br>+ * mainboard_enable is executed as first thing after<br>+ * enumerate_buses().<br>+ */<br>+static void mainboard_enable(device_t dev)<br>+{<br>+ dev->ops->init = mainboard_init;<br>+}<br>+<br>+struct chip_operations mainboard_ops = {<br>+ .enable_dev = mainboard_enable,<br>+};<br>diff --git a/src/mainboard/intel/saddlebrook/pei_data.c b/src/mainboard/intel/saddlebrook/pei_data.c<br>new file mode 100644<br>index 0000000..0d5acc2<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/pei_data.c<br>@@ -0,0 +1,29 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <stdint.h><br>+#include <string.h><br>+#include <soc/pei_data.h><br>+#include <soc/pei_wrapper.h><br>+#include "spd/spd.h"<br>+<br>+void mainboard_fill_pei_data(struct pei_data *pei_data)<br>+{<br>+ mainboard_fill_dq_map_data(&pei_data->dq_map);<br>+ mainboard_fill_dqs_map_data(&pei_data->dqs_map);<br>+ mainboard_fill_rcomp_res_data(&pei_data->RcompResistor);<br>+ mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget);<br>+}<br>diff --git a/src/mainboard/intel/saddlebrook/ramstage.c b/src/mainboard/intel/saddlebrook/ramstage.c<br>new file mode 100644<br>index 0000000..42477e6<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/ramstage.c<br>@@ -0,0 +1,24 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016 Intel Corporation<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/ramstage.h><br>+#include "gpio.h"<br>+<br>+void mainboard_silicon_init_params(SILICON_INIT_UPD *params)<br>+{<br>+ /* Configure pads prior to SiliconInit() in case there's any<br>+ * dependencies during hardware initialization. */<br>+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));<br>+}<br>diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c<br>new file mode 100644<br>index 0000000..5850ca1<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/romstage.c<br>@@ -0,0 +1,90 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2010 coresystems GmbH<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <cbfs.h><br>+#include <console/console.h><br>+#include <fsp/api.h><br>+#include <string.h><br>+#include <soc/gpio.h><br>+#include <soc/pei_data.h><br>+#include <soc/pei_wrapper.h><br>+#include <soc/pm.h><br>+#include <soc/romstage.h><br>+#include "spd/spd.h"<br>+#include <spd_bin.h><br>+#include <superio/nuvoton/common/nuvoton.h><br>+#include <superio/nuvoton/nct6776/nct6776.h><br>+<br>+#include <lib.h><br>+<br>+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)<br>+<br>+void car_mainboard_pre_console_init(void)<br>+{<br>+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>+}<br>+<br>+void mainboard_romstage_entry(struct romstage_params *params)<br>+{<br>+ post_code(0x31);<br>+ /* Fill out PEI DATA */<br>+ mainboard_fill_pei_data(params->pei_data);<br>+ romstage_common(params);<br>+<br>+}<br>+<br>+void mainboard_memory_init_params(<br>+ struct romstage_params *params,<br>+ MEMORY_INIT_UPD *memory_params)<br>+{<br>+ struct spd_block blk = {<br>+ .addr_map = { 0x50, 0x51, 0x52, 0x53, },<br>+ };<br>+<br>+ get_spd_smbus(&blk);<br>+ dump_spd_info(&blk);<br>+ printk(BIOS_SPEW, "spd block length: 0x%08x\n",blk.len);<br>+<br>+ memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0];<br>+ memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[2];<br>+ printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",<br>+ memory_params->MemorySpdPtr00);<br>+ printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",<br>+ memory_params->MemorySpdPtr10);<br>+<br>+ /*<br>+ * Configure the DQ/DQS settings if required. In general the settings<br>+ * should be set in the FSP flash image and should not need to be<br>+ * changed.<br>+ */<br>+ memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0],<br>+ sizeof(params->pei_data->dq_map[0]));<br>+ memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1],<br>+ sizeof(params->pei_data->dq_map[1]));<br>+ memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0],<br>+ sizeof(params->pei_data->dqs_map[0]));<br>+ memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1],<br>+ sizeof(params->pei_data->dqs_map[1]));<br>+ memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor,<br>+ sizeof(params->pei_data->RcompResistor));<br>+ memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget,<br>+ sizeof(params->pei_data->RcompTarget));<br>+<br>+ /* update spd length*/<br>+ memory_params->MemorySpdDataLen = blk.len;<br>+ memory_params->DqPinsInterleaved = TRUE;<br>+}<br>diff --git a/src/mainboard/intel/saddlebrook/smihandler.c b/src/mainboard/intel/saddlebrook/smihandler.c<br>new file mode 100644<br>index 0000000..dcfb884<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/smihandler.c<br>@@ -0,0 +1,46 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008-2009 coresystems GmbH<br>+ * Copyright (C) 2016 Intel Corp.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/acpi.h><br>+#include <arch/io.h><br>+#include <console/console.h><br>+#include <cpu/x86/smm.h><br>+#include <elog.h><br>+#include <soc/iomap.h><br>+#include <soc/nvs.h><br>+#include <soc/pm.h><br>+#include <soc/smm.h><br>+#include "gpio.h"<br>+<br>+int mainboard_io_trap_handler(int smif)<br>+{<br>+ switch (smif) {<br>+ case 0x99:<br>+ printk(BIOS_DEBUG, "Sample\n");<br>+ smm_get_gnvs()->smif = 0;<br>+ break;<br>+ default:<br>+ return 0;<br>+ }<br>+<br>+ /* On success, the IO Trap Handler returns 0<br>+ * On failure, the IO Trap Handler returns a value != 0<br>+ *<br>+ * For now, we force the return value to 0 and log all traps to<br>+ * see what's going on.<br>+ */<br>+ return 1;<br>+}<br>diff --git a/src/mainboard/intel/saddlebrook/spd/Makefile.inc b/src/mainboard/intel/saddlebrook/spd/Makefile.inc<br>new file mode 100644<br>index 0000000..721736d<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/spd/Makefile.inc<br>@@ -0,0 +1,17 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2014 Google Inc.<br>+## Copyright (C) 2015 Intel Corporation.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+romstage-y += spd_util.c<br>diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h<br>new file mode 100644<br>index 0000000..a5f1af3<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/spd/spd.h<br>@@ -0,0 +1,27 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef MAINBOARD_SPD_H<br>+#define MAINBOARD_SPD_H<br>+<br>+#define RCOMP_TARGET_PARAMS 0x5<br>+<br>+void mainboard_fill_dq_map_data(void *dq_map_ptr);<br>+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);<br>+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);<br>+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);<br>+<br>+#endif<br>diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c<br>new file mode 100644<br>index 0000000..69137fc<br>--- /dev/null<br>+++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c<br>@@ -0,0 +1,59 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+#include <arch/byteorder.h><br>+#include <cbfs.h><br>+#include <console/console.h><br>+#include <stdint.h><br>+#include <string.h><br>+#include <soc/pei_data.h><br>+#include <soc/pei_wrapper.h><br>+#include "spd.h"<br>+<br>+void mainboard_fill_dq_map_data(void *dq_map_ptr)<br>+{<br>+ /* DQ byte map */<br>+ const u8 dq_map[2][12] = {<br>+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,<br>+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },<br>+ { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,<br>+ 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };<br>+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));<br>+}<br>+<br>+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)<br>+{<br>+ /* DQS CPU<>DRAM map */<br>+ const u8 dqs_map[2][8] = {<br>+ { 0, 1, 3, 2, 4, 5, 6, 7 },<br>+ { 1, 0, 4, 5, 2, 3, 6, 7 } };<br>+ memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));<br>+}<br>+<br>+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)<br>+{<br>+ /* Rcomp resistor */<br>+ const u16 RcompResistor[3] = { 121, 81, 100 };<br>+ memcpy(rcomp_ptr, RcompResistor,<br>+ sizeof(RcompResistor));<br>+}<br>+<br>+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)<br>+{<br>+ /* Rcomp target */<br>+ static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {<br>+ 100, 40, 20, 20, 26 };<br>+<br>+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21436">change 21436</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21436"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e </div>
<div style="display:none"> Gerrit-Change-Number: 21436 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Anuj Mittal <anujx.mittal@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Boon Tiong Teo <boon.tiong.teo@intel.com> </div>