<p>Philipp Ammann has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21421">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/intel/d525mw: Initial commit<br><br>The Intel D525MW is very close to the D510MO. This commit is just a<br>copy of the D510MO with the name replaced.<br><br>Change-Id: I3510879edc4542589d1e6754bc2e11ae2723e2ac<br>Signed-off-by: Philipp Ammann <trilean@users.noreply.github.com><br>---<br>A src/mainboard/intel/d525mw/Kconfig<br>A src/mainboard/intel/d525mw/Kconfig.name<br>A src/mainboard/intel/d525mw/Makefile.inc<br>A src/mainboard/intel/d525mw/acpi/ec.asl<br>A src/mainboard/intel/d525mw/acpi/ich7_pci_irqs.asl<br>A src/mainboard/intel/d525mw/acpi/pineview_pci_irqs.asl<br>A src/mainboard/intel/d525mw/acpi/platform.asl<br>A src/mainboard/intel/d525mw/acpi/superio.asl<br>A src/mainboard/intel/d525mw/acpi_tables.c<br>A src/mainboard/intel/d525mw/board_info.txt<br>A src/mainboard/intel/d525mw/cmos.default<br>A src/mainboard/intel/d525mw/cmos.layout<br>A src/mainboard/intel/d525mw/cstates.c<br>A src/mainboard/intel/d525mw/devicetree.cb<br>A src/mainboard/intel/d525mw/dsdt.asl<br>A src/mainboard/intel/d525mw/gpio.c<br>A src/mainboard/intel/d525mw/hda_verb.c<br>A src/mainboard/intel/d525mw/mainboard.c<br>A src/mainboard/intel/d525mw/romstage.c<br>19 files changed, 848 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/21421/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/d525mw/Kconfig b/src/mainboard/intel/d525mw/Kconfig<br>new file mode 100644<br>index 0000000..4f3c998<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/Kconfig<br>@@ -0,0 +1,48 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com><br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+if BOARD_INTEL_D525MW<br>+<br>+config BOARD_SPECIFIC_OPTIONS<br>+ def_bool y<br>+ select CPU_INTEL_SOCKET_FCBGA559<br>+ select NORTHBRIDGE_INTEL_PINEVIEW<br>+ select SOUTHBRIDGE_INTEL_I82801GX<br>+ select SUPERIO_WINBOND_W83627THG<br>+ select HAVE_ACPI_TABLES<br>+ select HAVE_ACPI_RESUME<br>+ select BOARD_ROMSIZE_KB_1024<br>+ select MAINBOARD_HAS_NATIVE_VGA_INIT<br>+ select INTEL_INT15<br>+ select HAVE_OPTION_TABLE<br>+ select HAVE_CMOS_DEFAULT<br>+<br>+config MAX_CPUS<br>+ int<br>+ default 4<br>+<br>+config MMCONF_BASE_ADDRESS<br>+ hex<br>+ default 0xe0000000<br>+<br>+config MAINBOARD_DIR<br>+ string<br>+ default intel/d525mw<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "D525MW"<br>+<br>+endif # BOARD_INTEL_D525MW<br>diff --git a/src/mainboard/intel/d525mw/Kconfig.name b/src/mainboard/intel/d525mw/Kconfig.name<br>new file mode 100644<br>index 0000000..6fdb942<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_INTEL_D525MW<br>+ bool "D525MW"<br>diff --git a/src/mainboard/intel/d525mw/Makefile.inc b/src/mainboard/intel/d525mw/Makefile.inc<br>new file mode 100644<br>index 0000000..f3d7e76<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/Makefile.inc<br>@@ -0,0 +1,2 @@<br>+ramstage-y += cstates.c<br>+romstage-y += gpio.c<br>diff --git a/src/mainboard/intel/d525mw/acpi/ec.asl b/src/mainboard/intel/d525mw/acpi/ec.asl<br>new file mode 100644<br>index 0000000..31eb392<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/acpi/ec.asl<br>@@ -0,0 +1 @@<br>+/* Dummy file - No license required. */<br>diff --git a/src/mainboard/intel/d525mw/acpi/ich7_pci_irqs.asl b/src/mainboard/intel/d525mw/acpi/ich7_pci_irqs.asl<br>new file mode 100644<br>index 0000000..debf4b1<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/acpi/ich7_pci_irqs.asl<br>@@ -0,0 +1,35 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* This is board specific information:<br>+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH7<br>+ */<br>+<br>+If (PICM) {<br>+ Return (Package() {<br>+ Package() { 0x0000ffff, 0, 0, 22},<br>+ Package() { 0x0000ffff, 1, 0, 20},<br>+ Package() { 0x0000ffff, 2, 0, 17},<br>+ Package() { 0x0000ffff, 3, 0, 16},<br>+ })<br>+} Else {<br>+ Return (Package() {<br>+ Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},<br>+ Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},<br>+ Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},<br>+ Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},<br>+ })<br>+}<br>diff --git a/src/mainboard/intel/d525mw/acpi/pineview_pci_irqs.asl b/src/mainboard/intel/d525mw/acpi/pineview_pci_irqs.asl<br>new file mode 100644<br>index 0000000..3fa6fdb<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/acpi/pineview_pci_irqs.asl<br>@@ -0,0 +1,72 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+/* This is board specific information: IRQ routing for pineview */<br>+/* FIXME: EHCI controller not working yet */<br>+<br>+/* PCI Interrupt Routing */<br>+Method(_PRT)<br>+{<br>+ If (PICM) {<br>+ Return (Package() {<br>+ /* Internal GFX */<br>+ Package() { 0x0002ffff, 0, 0, 16 },<br>+ /* High Definition Audio 0:1b.0 */<br>+ Package() { 0x001bffff, 0, 0, 22 },<br>+ /* PCIe Root Ports 0:1c.x */<br>+ Package() { 0x001cffff, 0, 0, 17 },<br>+ Package() { 0x001cffff, 1, 0, 16 },<br>+ Package() { 0x001cffff, 2, 0, 18 },<br>+ Package() { 0x001cffff, 3, 0, 19 },<br>+ /* USB and EHCI 0:1d.x */<br>+ Package() { 0x001dffff, 0, 0, 23 },<br>+ Package() { 0x001dffff, 1, 0, 19 },<br>+ Package() { 0x001dffff, 2, 0, 18 },<br>+ Package() { 0x001dffff, 3, 0, 16 },<br>+ Package() { 0x001dffff, 0, 0, 23 },<br>+ /* PCI 0:1e.0 */<br>+ Package() { 0x001effff, 0, 0, 22 },<br>+ /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */<br>+ Package() { 0x001fffff, 1, 0, 19 },<br>+ Package() { 0x001fffff, 1, 0, 19 },<br>+ Package() { 0x001fffff, 1, 0, 19 },<br>+ })<br>+ } Else {<br>+ Return (Package() {<br>+ /* Internal GFX */<br>+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },<br>+ /* High Definition Audio 0:1b.0 */<br>+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },<br>+ /* PCIe Root Ports 0:1c.x */<br>+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },<br>+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },<br>+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },<br>+ /* USB and EHCI 0:1d.x */<br>+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },<br>+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },<br>+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },<br>+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },<br>+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },<br>+ /* PCI 0:1e.0 */<br>+ Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 },<br>+ /* LPC/SATA/SMBUS 0:1f.2, 0:1f.3 */<br>+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },<br>+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },<br>+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },<br>+ })<br>+ }<br>+}<br>diff --git a/src/mainboard/intel/d525mw/acpi/platform.asl b/src/mainboard/intel/d525mw/acpi/platform.asl<br>new file mode 100644<br>index 0000000..6c92a4e<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/acpi/platform.asl<br>@@ -0,0 +1,28 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+Method(_PIC, 1)<br>+{<br>+ /* Remember the OS' IRQ routing choice. */<br>+ Store(Arg0, PICM)<br>+}<br>+<br>+/* SMI I/O Trap */<br>+Method(TRAP, 1, Serialized)<br>+{<br>+ Store (Arg0, SMIF) /* SMI Function */<br>+ Store (0, TRP0) /* Generate trap */<br>+ Return (SMIF) /* Return value of SMI handler */<br>+}<br>diff --git a/src/mainboard/intel/d525mw/acpi/superio.asl b/src/mainboard/intel/d525mw/acpi/superio.asl<br>new file mode 100644<br>index 0000000..31eb392<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/acpi/superio.asl<br>@@ -0,0 +1 @@<br>+/* Dummy file - No license required. */<br>diff --git a/src/mainboard/intel/d525mw/acpi_tables.c b/src/mainboard/intel/d525mw/acpi_tables.c<br>new file mode 100644<br>index 0000000..92688bf<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/acpi_tables.c<br>@@ -0,0 +1,21 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <types.h><br>+#include <southbridge/intel/i82801gx/nvs.h><br>+<br>+void acpi_create_gnvs(global_nvs_t *gnvs)<br>+{<br>+}<br>diff --git a/src/mainboard/intel/d525mw/board_info.txt b/src/mainboard/intel/d525mw/board_info.txt<br>new file mode 100644<br>index 0000000..e5b3ca9<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/board_info.txt<br>@@ -0,0 +1,5 @@<br>+Category: desktop<br>+Board URL: http://ark.intel.com/products/48952/Intel-Desktop-Board-D525MW<br>+ROM package: SOIC-8<br>+ROM protocol: SPI<br>+ROM socketed: n<br>diff --git a/src/mainboard/intel/d525mw/cmos.default b/src/mainboard/intel/d525mw/cmos.default<br>new file mode 100644<br>index 0000000..488aa37<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/cmos.default<br>@@ -0,0 +1,6 @@<br>+boot_option=Fallback<br>+baud_rate=115200<br>+debug_level=Spew<br>+power_on_after_fail=Disable<br>+nmi=Enable<br>+gfx_uma_size=8M<br>diff --git a/src/mainboard/intel/d525mw/cmos.layout b/src/mainboard/intel/d525mw/cmos.layout<br>new file mode 100644<br>index 0000000..3e96412<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/cmos.layout<br>@@ -0,0 +1,98 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2007-2008 coresystems GmbH<br>+## Copyright (C) 2014 Vladimir Serbinenko<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+# -----------------------------------------------------------------<br>+entries<br>+<br>+<br>+# -----------------------------------------------------------------<br>+0 120 r 0 reserved_memory<br>+#120 264 r 0 unused<br>+<br>+# -----------------------------------------------------------------<br>+# RTC_BOOT_BYTE (coreboot hardcoded)<br>+384 1 e 4 boot_option<br>+388 4 h 0 reboot_counter<br>+#390 2 r 0 unused?<br>+<br>+# -----------------------------------------------------------------<br>+# coreboot config options: console<br>+392 3 e 5 baud_rate<br>+395 4 e 6 debug_level<br>+#399 1 r 0 unused<br>+<br>+#400 8 r 0 reserved for century byte<br>+<br>+# coreboot config options: southbridge<br>+408 1 e 1 nmi<br>+409 2 e 7 power_on_after_fail<br>+<br>+# coreboot config options: bootloader<br>+416 512 s 0 boot_devices<br>+<br>+# coreboot config options: cpu<br>+944 1 e 2 hyper_threading<br>+#945 7 r 0 unused<br>+<br>+# coreboot config options: northbridge<br>+952 3 e 11 gfx_uma_size<br>+<br>+# coreboot config options: check sums<br>+984 16 h 0 check_sum<br>+<br>+# -----------------------------------------------------------------<br>+<br>+enumerations<br>+<br>+#ID value text<br>+1 0 Disable<br>+1 1 Enable<br>+2 0 Enable<br>+2 1 Disable<br>+4 0 Fallback<br>+4 1 Normal<br>+5 0 115200<br>+5 1 57600<br>+5 2 38400<br>+5 3 19200<br>+5 4 9600<br>+5 5 4800<br>+5 6 2400<br>+5 7 1200<br>+6 1 Emergency<br>+6 2 Alert<br>+6 3 Critical<br>+6 4 Error<br>+6 5 Warning<br>+6 6 Notice<br>+6 7 Info<br>+6 8 Debug<br>+6 9 Spew<br>+7 0 Disable<br>+7 1 Enable<br>+7 2 Keep<br>+11 0 8M<br>+11 1 16M<br>+11 2 32M<br>+11 3 48M<br>+11 4 64M<br>+11 5 128M<br>+11 6 256M<br>+<br>+# -----------------------------------------------------------------<br>+checksums<br>+<br>+checksum 392 983 984<br>diff --git a/src/mainboard/intel/d525mw/cstates.c b/src/mainboard/intel/d525mw/cstates.c<br>new file mode 100644<br>index 0000000..b7eb6df<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/cstates.c<br>@@ -0,0 +1,22 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/device.h><br>+#include <arch/x86/include/arch/acpigen.h><br>+<br>+int get_cst_entries(acpi_cstate_t **entries)<br>+{<br>+ return 0;<br>+}<br>diff --git a/src/mainboard/intel/d525mw/devicetree.cb b/src/mainboard/intel/d525mw/devicetree.cb<br>new file mode 100644<br>index 0000000..c5b885f<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/devicetree.cb<br>@@ -0,0 +1,101 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com><br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; either version 2 of the License, or<br>+# (at your option) any later version.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+chip northbridge/intel/pineview # Northbridge<br>+ register "gfx.use_spread_spectrum_clock" = "0"<br>+ register "use_crt" = "1"<br>+ register "use_lvds" = "0"<br>+<br>+ device cpu_cluster 0 on # APIC cluster<br>+ chip cpu/intel/socket_FCBGA559 # CPU<br>+ device lapic 0 on end # APIC<br>+ end<br>+ end<br>+ device domain 0 on # PCI domain<br>+ device pci 0.0 on end # Host Bridge<br>+ device pci 1.0 off end # PEG<br>+ device pci 2.0 on end # Integrated graphics controller<br>+ device pci 2.1 on end # Integrated graphics controller 2<br>+ chip southbridge/intel/i82801gx # Southbridge<br>+ register "pirqa_routing" = "0x0b"<br>+ register "pirqb_routing" = "0x0b"<br>+ register "pirqc_routing" = "0x0b"<br>+ register "pirqd_routing" = "0x0b"<br>+ register "pirqe_routing" = "0x0b"<br>+ register "pirqf_routing" = "0x0b"<br>+ register "pirqg_routing" = "0x0b"<br>+ register "pirqh_routing" = "0x0b"<br>+ register "sata_ahci" = "0x1"<br>+ register "sata_ports_implemented" = "0x3"<br>+ register "gpe0_en" = "0x20000040"<br>+<br>+ device pci 1b.0 on end # Audio<br>+ device pci 1c.0 on # PCIe 1<br>+ device pci 0.0 on end # NIC<br>+ end<br>+ device pci 1c.1 on end # PCIe 2<br>+ device pci 1c.2 on end # PCIe 3<br>+ device pci 1c.3 on end # PCIe 4<br>+ device pci 1d.0 on end # USB<br>+ device pci 1d.1 on end # USB<br>+ device pci 1d.2 on end # USB<br>+ device pci 1d.3 on end # USB<br>+ device pci 1d.7 on end # USB<br>+ device pci 1e.0 on end # PCI bridge<br>+ device pci 1f.0 on # ISA bridge<br>+ chip superio/winbond/w83627thg # Super I/O<br>+ device pnp 4e.0 off end # Floppy<br>+ device pnp 4e.1 on # Parallel port<br>+ io 0x60 = 0x378<br>+ irq 0x70 = 7<br>+ drq 0x74 = 4<br>+ end<br>+ device pnp 4e.2 on # COM1<br>+ io 0x60 = 0x3f8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 4e.3 on # COM2<br>+ io 0x60 = 0x2f8<br>+ irq 0x70 = 3<br>+ irq 0xf1 = 0<br>+ end<br>+ device pnp 4e.5 on # PS/2 keyboard / mouse<br>+ io 0x60 = 0x60<br>+ io 0x62 = 0x64<br>+ irq 0x70 = 1 # PS/2 keyboard interrupt<br>+ irq 0x72 = 12 # PS/2 mouse interrupt<br>+ irq 0xf0 = 0x80<br>+ end<br>+ device pnp 4e.6 off end<br>+ device pnp 4e.7 off end<br>+ device pnp 4e.8 off end<br>+ device pnp 4e.9 off end<br>+ device pnp 4e.a off end # ACPI<br>+ device pnp 4e.b on # HWM<br>+ io 0x60 = 0x290<br>+ irq 0x70 = 0<br>+ end<br>+ end<br>+ end<br>+ device pci 1f.1 off end<br>+ device pci 1f.2 on end # SATA<br>+ device pci 1f.3 on end # SMbus<br>+ device pci 1f.4 off end<br>+ device pci 1f.5 off end<br>+ device pci 1f.6 off end<br>+ end<br>+ end<br>+end<br>diff --git a/src/mainboard/intel/d525mw/dsdt.asl b/src/mainboard/intel/d525mw/dsdt.asl<br>new file mode 100644<br>index 0000000..a7788bd<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/dsdt.asl<br>@@ -0,0 +1,41 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+DefinitionBlock(<br>+ "dsdt.aml",<br>+ "DSDT",<br>+ 0x02, // DSDT revision: ACPI v2.0<br>+ "COREv4", // OEM id<br>+ "COREBOOT", // OEM table id<br>+ 0x20090419 // OEM revision<br>+)<br>+{<br>+ #include "acpi/platform.asl"<br>+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl><br>+<br>+ #include <cpu/intel/common/acpi/cpu.asl><br>+<br>+ Scope (\_SB) {<br>+ Device (PCI0)<br>+ {<br>+ #include <northbridge/intel/pineview/acpi/pineview.asl><br>+ #include <southbridge/intel/i82801gx/acpi/ich7.asl><br>+ }<br>+ }<br>+<br>+ /* Chipset specific sleep states */<br>+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl><br>+}<br>diff --git a/src/mainboard/intel/d525mw/gpio.c b/src/mainboard/intel/d525mw/gpio.c<br>new file mode 100644<br>index 0000000..81e23ba<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/gpio.c<br>@@ -0,0 +1,125 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2016 Arthur Heymans <arthur@aheymans.xyz><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <southbridge/intel/common/gpio.h><br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_mode = {<br>+ .gpio0 = GPIO_MODE_GPIO,<br>+ .gpio6 = GPIO_MODE_GPIO,<br>+ .gpio7 = GPIO_MODE_GPIO,<br>+ .gpio8 = GPIO_MODE_GPIO,<br>+ .gpio9 = GPIO_MODE_GPIO,<br>+ .gpio10 = GPIO_MODE_GPIO,<br>+ .gpio12 = GPIO_MODE_GPIO,<br>+ .gpio13 = GPIO_MODE_GPIO,<br>+ .gpio14 = GPIO_MODE_GPIO,<br>+ .gpio15 = GPIO_MODE_GPIO,<br>+ .gpio16 = GPIO_MODE_GPIO,<br>+ .gpio19 = GPIO_MODE_GPIO,<br>+ .gpio20 = GPIO_MODE_GPIO,<br>+ .gpio21 = GPIO_MODE_GPIO,<br>+ .gpio22 = GPIO_MODE_GPIO,<br>+ .gpio23 = GPIO_MODE_GPIO,<br>+ .gpio24 = GPIO_MODE_GPIO,<br>+ .gpio25 = GPIO_MODE_GPIO,<br>+ .gpio26 = GPIO_MODE_GPIO,<br>+ .gpio27 = GPIO_MODE_GPIO,<br>+ .gpio28 = GPIO_MODE_GPIO,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_direction = {<br>+ .gpio0 = GPIO_DIR_INPUT,<br>+ .gpio6 = GPIO_DIR_OUTPUT,<br>+ .gpio7 = GPIO_DIR_OUTPUT,<br>+ .gpio8 = GPIO_DIR_OUTPUT,<br>+ .gpio9 = GPIO_DIR_OUTPUT,<br>+ .gpio10 = GPIO_DIR_OUTPUT,<br>+ .gpio12 = GPIO_DIR_OUTPUT,<br>+ .gpio13 = GPIO_DIR_INPUT,<br>+ .gpio14 = GPIO_DIR_INPUT,<br>+ .gpio15 = GPIO_DIR_INPUT,<br>+ .gpio16 = GPIO_DIR_INPUT,<br>+ .gpio19 = GPIO_DIR_INPUT,<br>+ .gpio20 = GPIO_DIR_OUTPUT,<br>+ .gpio21 = GPIO_DIR_INPUT,<br>+ .gpio22 = GPIO_DIR_INPUT,<br>+ .gpio23 = GPIO_DIR_INPUT,<br>+ .gpio24 = GPIO_DIR_OUTPUT,<br>+ .gpio25 = GPIO_DIR_OUTPUT,<br>+ .gpio26 = GPIO_DIR_OUTPUT,<br>+ .gpio27 = GPIO_DIR_OUTPUT,<br>+ .gpio28 = GPIO_DIR_OUTPUT,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_level = {<br>+ .gpio6 = GPIO_LEVEL_HIGH,<br>+ .gpio7 = GPIO_LEVEL_LOW,<br>+ .gpio8 = GPIO_LEVEL_LOW,<br>+ .gpio9 = GPIO_LEVEL_LOW,<br>+ .gpio10 = GPIO_LEVEL_LOW,<br>+ .gpio12 = GPIO_LEVEL_LOW,<br>+ .gpio20 = GPIO_LEVEL_LOW,<br>+ .gpio24 = GPIO_LEVEL_LOW,<br>+ .gpio25 = GPIO_LEVEL_LOW,<br>+ .gpio26 = GPIO_LEVEL_HIGH,<br>+ .gpio27 = GPIO_LEVEL_HIGH,<br>+ .gpio28 = GPIO_LEVEL_LOW,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_invert = {<br>+ .gpio13 = GPIO_INVERT,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_blink = {<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_mode = {<br>+ .gpio33 = GPIO_MODE_GPIO,<br>+ .gpio34 = GPIO_MODE_GPIO,<br>+ .gpio35 = GPIO_MODE_GPIO,<br>+ .gpio36 = GPIO_MODE_GPIO,<br>+ .gpio37 = GPIO_MODE_GPIO,<br>+ .gpio38 = GPIO_MODE_GPIO,<br>+ .gpio39 = GPIO_MODE_GPIO,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_direction = {<br>+ .gpio33 = GPIO_DIR_INPUT,<br>+ .gpio34 = GPIO_DIR_INPUT,<br>+ .gpio35 = GPIO_DIR_INPUT,<br>+ .gpio36 = GPIO_DIR_INPUT,<br>+ .gpio37 = GPIO_DIR_INPUT,<br>+ .gpio38 = GPIO_DIR_INPUT,<br>+ .gpio39 = GPIO_DIR_OUTPUT,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_level = {<br>+ .gpio39 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+const struct pch_gpio_map mainboard_gpio_map = {<br>+ .set1 = {<br>+ .mode = &pch_gpio_set1_mode,<br>+ .direction = &pch_gpio_set1_direction,<br>+ .level = &pch_gpio_set1_level,<br>+ .blink = &pch_gpio_set1_blink,<br>+ .invert = &pch_gpio_set1_invert,<br>+ },<br>+ .set2 = {<br>+ .mode = &pch_gpio_set2_mode,<br>+ .direction = &pch_gpio_set2_direction,<br>+ .level = &pch_gpio_set2_level,<br>+ },<br>+};<br>diff --git a/src/mainboard/intel/d525mw/hda_verb.c b/src/mainboard/intel/d525mw/hda_verb.c<br>new file mode 100644<br>index 0000000..a0dba38<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/hda_verb.c<br>@@ -0,0 +1,39 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/azalia_device.h><br>+<br>+const u32 cim_verb_data[] = {<br>+ /* coreboot specific header */<br>+ 0x10ec0662,<br>+ 0x8086d618, // Subsystem ID<br>+ 0x0000000a, // Number of entries<br>+<br>+ /* Pin Widget Verb Table */<br>+ AZALIA_PIN_CFG(0, 0x14, 0x01014410),<br>+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),<br>+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),<br>+ AZALIA_PIN_CFG(0, 0x18, 0x01a19840),<br>+ AZALIA_PIN_CFG(0, 0x19, 0x02a19841),<br>+ AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),<br>+ AZALIA_PIN_CFG(0, 0x1b, 0x02214420),<br>+ AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),<br>+ AZALIA_PIN_CFG(0, 0x1d, 0x4015c603),<br>+ AZALIA_PIN_CFG(0, 0x1e, 0x99430130),<br>+};<br>+<br>+const u32 pc_beep_verbs[] = {<br>+};<br>+AZALIA_ARRAY_SIZES;<br>diff --git a/src/mainboard/intel/d525mw/mainboard.c b/src/mainboard/intel/d525mw/mainboard.c<br>new file mode 100644<br>index 0000000..4f0f32b<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/mainboard.c<br>@@ -0,0 +1,31 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/device.h><br>+#include <device/pci_def.h><br>+#include <device/pci_ops.h><br>+#include <pc80/mc146818rtc.h><br>+#include <device/pci.h><br>+#include <drivers/intel/gma/int15.h><br>+<br>+static void mainboard_enable(device_t dev)<br>+{<br>+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,<br>+ GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0);<br>+}<br>+<br>+struct chip_operations mainboard_ops = {<br>+ .enable_dev = mainboard_enable,<br>+};<br>diff --git a/src/mainboard/intel/d525mw/romstage.c b/src/mainboard/intel/d525mw/romstage.c<br>new file mode 100644<br>index 0000000..44f203f<br>--- /dev/null<br>+++ b/src/mainboard/intel/d525mw/romstage.c<br>@@ -0,0 +1,170 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <stdint.h><br>+#include <stdlib.h><br>+#include <device/pci_def.h><br>+#include <arch/io.h><br>+#include <device/pnp_def.h><br>+#include <console/console.h><br>+#include <southbridge/intel/i82801gx/i82801gx.h><br>+#include <southbridge/intel/common/gpio.h><br>+#include <northbridge/intel/pineview/raminit.h><br>+#include <northbridge/intel/pineview/pineview.h><br>+#include <cpu/x86/bist.h><br>+#include <cpu/intel/romstage.h><br>+#include <cpu/x86/lapic.h><br>+#include <superio/winbond/w83627thg/w83627thg.h><br>+#include <superio/winbond/common/winbond.h><br>+#include <lib.h><br>+#include <arch/stages.h><br>+#include <cbmem.h><br>+#include <romstage_handoff.h><br>+#include <timestamp.h><br>+<br>+#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)<br>+#define SUPERIO_DEV PNP_DEV(0x4e, 0)<br>+<br>+<br>+/* Early mainboard specific GPIO setup */<br>+static void mb_gpio_init(void)<br>+{<br>+ device_t dev;<br>+<br>+ /* Southbridge GPIOs. */<br>+ dev = PCI_DEV(0x0, 0x1f, 0x0);<br>+<br>+ /* Set the value for GPIO base address register and enable GPIO. */<br>+ pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1));<br>+ pci_write_config8(dev, GPIO_CNTL, 0x10);<br>+<br>+ setup_pch_gpios(&mainboard_gpio_map);<br>+}<br>+<br>+static void nm10_enable_lpc(void)<br>+{<br>+ /* Disable Serial IRQ */<br>+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00);<br>+ /* Decode range */<br>+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80,<br>+ pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x80) | 0x0010);<br>+ pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN,<br>+ CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN |<br>+ COMB_LPC_EN);<br>+<br>+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291);<br>+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c);<br>+}<br>+<br>+static void rcba_config(void)<br>+{<br>+ /* Set up virtual channel 0 */<br>+ RCBA32(0x0014) = 0x80000001;<br>+ RCBA32(0x001c) = 0x03128010;<br>+<br>+ /* Device 1f interrupt pin register */<br>+ RCBA32(0x3100) = 0x00042210;<br>+ RCBA32(0x3108) = 0x10004321;<br>+<br>+ RCBA32(0x3104) = 0x00002100;<br>+<br>+ /* PCIe Interrupts */<br>+ RCBA32(0x310c) = 0x00214321;<br>+ /* HD Audio Interrupt */<br>+ RCBA32(0x3110) = 0x00000001;<br>+<br>+ /* dev irq route register */<br>+ RCBA16(0x3140) = 0x0132;<br>+ RCBA16(0x3142) = 0x0146;<br>+ RCBA16(0x3144) = 0x0237;<br>+ RCBA16(0x3146) = 0x3201;<br>+ RCBA16(0x3148) = 0x0146;<br>+<br>+ /* Enable IOAPIC */<br>+ RCBA8(0x31ff) = 0x03;<br>+<br>+ RCBA32(0x3418) = 0x003000e2;<br>+ RCBA32(0x3418) |= 1;<br>+}<br>+<br>+void mainboard_romstage_entry(unsigned long bist)<br>+{<br>+ const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };<br>+ const u8 clockgen_block[13] = { 0x61, 0xd9, 0xfe, 0xff, 0xff, 0x00,<br>+ 0x00, 0x01, 0x03, 0x25, 0x83, 0x17,<br>+ 0x0d };<br>+ int cbmem_was_initted;<br>+ int s3resume = 0;<br>+ int boot_path;<br>+<br>+ timestamp_init(get_initial_timestamp());<br>+ timestamp_add_now(TS_START_ROMSTAGE);<br>+<br>+ if (bist == 0)<br>+ enable_lapic();<br>+<br>+ /* Disable watchdog timer */<br>+ RCBA32(0x3410) = RCBA32(0x3410) | 0x20;<br>+<br>+ /* Set southbridge and Super I/O GPIOs. */<br>+ mb_gpio_init();<br>+<br>+ nm10_enable_lpc();<br>+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>+ console_init();<br>+<br>+ report_bist_failure(bist);<br>+ enable_smbus();<br>+<br>+ smbus_block_write(0x69, 0, 13, clockgen_block);<br>+<br>+ pineview_early_initialization();<br>+<br>+ post_code(0x30);<br>+<br>+ s3resume = southbridge_detect_s3_resume();<br>+<br>+ if (s3resume) {<br>+ boot_path = BOOT_PATH_RESUME;<br>+ } else {<br>+ if (MCHBAR32(0xf14) & (1 << 8)) /* HOT RESET */<br>+ boot_path = BOOT_PATH_RESET;<br>+ else<br>+ boot_path = BOOT_PATH_NORMAL;<br>+ }<br>+<br>+ printk(BIOS_DEBUG, "Initializing memory\n");<br>+ timestamp_add_now(TS_BEFORE_INITRAM);<br>+ sdram_initialize(boot_path, spd_addrmap);<br>+ timestamp_add_now(TS_AFTER_INITRAM);<br>+ printk(BIOS_DEBUG, "Memory initialized\n");<br>+<br>+ post_code(0x31);<br>+<br>+ quick_ram_check();<br>+<br>+ rcba_config();<br>+<br>+ cbmem_was_initted = !cbmem_recovery(s3resume);<br>+<br>+ if (!cbmem_was_initted && s3resume) {<br>+ /* Failed S3 resume, reset to come up cleanly */<br>+ outb(0x6, 0xcf9);<br>+ halt();<br>+ }<br>+<br>+ romstage_handoff_init(s3resume);<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/21421">change 21421</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21421"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3510879edc4542589d1e6754bc2e11ae2723e2ac </div>
<div style="display:none"> Gerrit-Change-Number: 21421 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Philipp Ammann </div>