<p>Felix Singer has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21428">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/asrock/h67m-itx: Initial commit<br><br>Change-Id: I67c72ea36ec8bead9123606bee4cdd7b36068de9<br>---<br>A src/mainboard/asrock/h67m-itx/Kconfig<br>A src/mainboard/asrock/h67m-itx/Kconfig.name<br>A src/mainboard/asrock/h67m-itx/Makefile.inc<br>A src/mainboard/asrock/h67m-itx/acpi/ec.asl<br>A src/mainboard/asrock/h67m-itx/acpi/platform.asl<br>A src/mainboard/asrock/h67m-itx/acpi/superio.asl<br>A src/mainboard/asrock/h67m-itx/acpi_tables.c<br>A src/mainboard/asrock/h67m-itx/board_info.txt<br>A src/mainboard/asrock/h67m-itx/devicetree.cb<br>A src/mainboard/asrock/h67m-itx/dsdt.asl<br>A src/mainboard/asrock/h67m-itx/early_southbridge.c<br>A src/mainboard/asrock/h67m-itx/gnvs.c<br>A src/mainboard/asrock/h67m-itx/gpio.c<br>A src/mainboard/asrock/h67m-itx/hda_verb.c<br>A src/mainboard/asrock/h67m-itx/mainboard.c<br>A src/mainboard/asrock/h67m-itx/romstage.c<br>16 files changed, 835 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/21428/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/asrock/h67m-itx/Kconfig b/src/mainboard/asrock/h67m-itx/Kconfig<br>new file mode 100644<br>index 0000000..7c21c33<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/Kconfig<br>@@ -0,0 +1,59 @@<br>+if BOARD_ASROCK_H67M_ITX<br>+<br>+config BOARD_SPECIFIC_OPTIONS # dummy<br>+ def_bool y<br>+ select BOARD_ROMSIZE_KB_8192<br>+ select CPU_INTEL_SOCKET_LGA1155<br>+ select HAVE_ACPI_RESUME<br>+ select HAVE_ACPI_TABLES<br>+ select INTEL_INT15<br>+ select NORTHBRIDGE_INTEL_SANDYBRIDGE<br>+ select SANDYBRIDGE_IVYBRIDGE_LVDS<br>+ select SERIRQ_CONTINUOUS_MODE<br>+ select SOUTHBRIDGE_INTEL_BD82X6X<br>+ select USE_NATIVE_RAMINIT<br>+<br>+config HAVE_IFD_BIN<br>+ bool<br>+ default n<br>+<br>+config HAVE_ME_BIN<br>+ bool<br>+ default n<br>+<br>+config MAINBOARD_DIR<br>+ string<br>+ default asrock/h67m-itx<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "H67M-ITX"<br>+<br>+config VGA_BIOS_FILE<br>+ string<br>+ default "pci8086,0102.rom"<br>+<br>+config VGA_BIOS_ID<br>+ string<br>+ default "8086,0102"<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID<br>+ hex<br>+ default 0x1c4a<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID<br>+ hex<br>+ default 0x1849<br>+<br>+config DRAM_RESET_GATE_GPIO # FIXME: check this<br>+ int<br>+ default 60<br>+<br>+config MAX_CPUS<br>+ int<br>+ default 8<br>+<br>+config USBDEBUG_HCD_INDEX # FIXME: check this<br>+ int<br>+ default 2<br>+endif<br>diff --git a/src/mainboard/asrock/h67m-itx/Kconfig.name b/src/mainboard/asrock/h67m-itx/Kconfig.name<br>new file mode 100644<br>index 0000000..fe4617a<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_ASROCK_H67M_ITX<br>+ bool "H67M-ITX"<br>diff --git a/src/mainboard/asrock/h67m-itx/Makefile.inc b/src/mainboard/asrock/h67m-itx/Makefile.inc<br>new file mode 100644<br>index 0000000..6064cea<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/Makefile.inc<br>@@ -0,0 +1,3 @@<br>+romstage-y += early_southbridge.c<br>+romstage-y += gpio.c<br>+ramstage-y += gnvs.c<br>diff --git a/src/mainboard/asrock/h67m-itx/acpi/ec.asl b/src/mainboard/asrock/h67m-itx/acpi/ec.asl<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/acpi/ec.asl<br>diff --git a/src/mainboard/asrock/h67m-itx/acpi/platform.asl b/src/mainboard/asrock/h67m-itx/acpi/platform.asl<br>new file mode 100644<br>index 0000000..0222986<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/acpi/platform.asl<br>@@ -0,0 +1,8 @@<br>+Method(_WAK,1)<br>+{<br>+ Return(Package(){0,0})<br>+}<br>+<br>+Method(_PTS,1)<br>+{<br>+}<br>diff --git a/src/mainboard/asrock/h67m-itx/acpi/superio.asl b/src/mainboard/asrock/h67m-itx/acpi/superio.asl<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/acpi/superio.asl<br>diff --git a/src/mainboard/asrock/h67m-itx/acpi_tables.c b/src/mainboard/asrock/h67m-itx/acpi_tables.c<br>new file mode 100644<br>index 0000000..2997587<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/acpi_tables.c<br>@@ -0,0 +1 @@<br>+/* dummy */<br>diff --git a/src/mainboard/asrock/h67m-itx/board_info.txt b/src/mainboard/asrock/h67m-itx/board_info.txt<br>new file mode 100644<br>index 0000000..f6eaf20<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/board_info.txt<br>@@ -0,0 +1,6 @@<br>+Category: desktop<br>+ROM package: DIP-8<br>+ROM protocol: SPI<br>+ROM socketed: y<br>+Flashrom support: n<br>+Release year: 2011<br>diff --git a/src/mainboard/asrock/h67m-itx/devicetree.cb b/src/mainboard/asrock/h67m-itx/devicetree.cb<br>new file mode 100644<br>index 0000000..0effb77<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/devicetree.cb<br>@@ -0,0 +1,110 @@<br>+chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did<br>+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"<br>+ register "gfx.link_frequency_270_mhz" = "0"<br>+ register "gfx.ndid" = "3"<br>+ register "gfx.use_spread_spectrum_clock" = "0"<br>+ register "gpu_cpu_backlight" = "0x00000000"<br>+ register "gpu_dp_b_hotplug" = "0"<br>+ register "gpu_dp_c_hotplug" = "0"<br>+ register "gpu_dp_d_hotplug" = "0"<br>+ register "gpu_panel_port_select" = "0"<br>+ register "gpu_panel_power_backlight_off_delay" = "0"<br>+ register "gpu_panel_power_backlight_on_delay" = "0"<br>+ register "gpu_panel_power_cycle_delay" = "0"<br>+ register "gpu_panel_power_down_delay" = "0"<br>+ register "gpu_panel_power_up_delay" = "0"<br>+ register "gpu_pch_backlight" = "0x00000000"<br>+ device cpu_cluster 0x0 on<br>+ chip cpu/intel/socket_rPGA989<br>+ device lapic 0x0 on<br>+ end<br>+ end<br>+ chip cpu/intel/model_206ax # FIXME: check all registers<br>+ register "c1_acpower" = "1"<br>+ register "c1_battery" = "1"<br>+ register "c2_acpower" = "3"<br>+ register "c2_battery" = "3"<br>+ register "c3_acpower" = "5"<br>+ register "c3_battery" = "5"<br>+ device lapic 0xacac off<br>+ end<br>+ end<br>+ end<br>+ device domain 0x0 on<br>+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH<br>+ register "c2_latency" = "0x0065"<br>+ register "docking_supported" = "0"<br>+ register "gen1_dec" = "0x000c0291"<br>+ register "gen2_dec" = "0x000c0241"<br>+ register "gen3_dec" = "0x000c0251"<br>+ register "gen4_dec" = "0x00000000"<br>+ register "p_cnt_throttling_supported" = "0"<br>+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"<br>+ register "pcie_port_coalesce" = "1"<br>+ register "sata_interface_speed_support" = "0x3"<br>+ register "sata_port_map" = "0x1f"<br>+ device pci 16.0 on # Management Engine Interface 1<br>+ subsystemid 0x1849 0x1c3a<br>+ end<br>+ device pci 16.1 off # Management Engine Interface 2<br>+ end<br>+ device pci 16.2 off # Management Engine IDE-R<br>+ end<br>+ device pci 16.3 off # Management Engine KT<br>+ end<br>+ device pci 19.0 off # Intel Gigabit Ethernet<br>+ end<br>+ device pci 1a.0 on # USB2 EHCI #2<br>+ subsystemid 0x1849 0x1c2d<br>+ end<br>+ device pci 1b.0 on # High Definition Audio Audio controller<br>+ subsystemid 0x1849 0x1892<br>+ end<br>+ device pci 1c.0 on # PCIe Port #1<br>+ subsystemid 0x1849 0x1c10<br>+ end<br>+ device pci 1c.1 off # PCIe Port #2<br>+ end<br>+ device pci 1c.2 off # PCIe Port #3<br>+ end<br>+ device pci 1c.3 on # PCIe Port #4<br>+ subsystemid 0x1849 0x1c16<br>+ end<br>+ device pci 1c.4 off # PCIe Port #5<br>+ end<br>+ device pci 1c.5 on # PCIe Port #6<br>+ subsystemid 0x1849 0x1c1a<br>+ end<br>+ device pci 1c.6 off # PCIe Port #7<br>+ end<br>+ device pci 1c.7 off # PCIe Port #8<br>+ end<br>+ device pci 1d.0 on # USB2 EHCI #1<br>+ subsystemid 0x1849 0x1c26<br>+ end<br>+ device pci 1e.0 off # PCI bridge<br>+ end<br>+ device pci 1f.0 on # LPC bridge PCI-LPC bridge<br>+ subsystemid 0x1849 0x1c4a<br>+ end<br>+ device pci 1f.2 on # SATA Controller 1<br>+ subsystemid 0x1849 0x1c02<br>+ end<br>+ device pci 1f.3 on # SMBus<br>+ subsystemid 0x1849 0x1c22<br>+ end<br>+ device pci 1f.5 off # SATA Controller 2<br>+ end<br>+ device pci 1f.6 off # Thermal<br>+ end<br>+ end<br>+ device pci 00.0 on # Host bridge Host bridge<br>+ subsystemid 0x1849 0x0100<br>+ end<br>+ device pci 01.0 off # PCIe Bridge for discrete graphics<br>+ end<br>+ device pci 02.0 on # Internal graphics VGA controller<br>+ subsystemid 0x1849 0x0102<br>+ end<br>+ end<br>+end<br>diff --git a/src/mainboard/asrock/h67m-itx/dsdt.asl b/src/mainboard/asrock/h67m-itx/dsdt.asl<br>new file mode 100644<br>index 0000000..3b7fb7e<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/dsdt.asl<br>@@ -0,0 +1,30 @@<br>+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB<br>+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB<br>+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0<br>+DefinitionBlock(<br>+ "dsdt.aml",<br>+ "DSDT",<br>+ 0x03, // DSDT revision: ACPI v3.0<br>+ "COREv4", // OEM id<br>+ "COREBOOT", // OEM table id<br>+ 0x20141018 // OEM revision<br>+)<br>+{<br>+ // Some generic macros<br>+ #include "acpi/platform.asl"<br>+ #include <cpu/intel/model_206ax/acpi/cpu.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/platform.asl><br>+ /* global NVS and variables. */<br>+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl><br>+<br>+ Scope (\_SB) {<br>+ Device (PCI0)<br>+ {<br>+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl><br>+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/pch.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl><br>+ }<br>+ }<br>+}<br>diff --git a/src/mainboard/asrock/h67m-itx/early_southbridge.c b/src/mainboard/asrock/h67m-itx/early_southbridge.c<br>new file mode 100644<br>index 0000000..1ec9ca7<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/early_southbridge.c<br>@@ -0,0 +1,69 @@<br>+#include <stdint.h><br>+#include <string.h><br>+#include <lib.h><br>+#include <timestamp.h><br>+#include <arch/byteorder.h><br>+#include <arch/io.h><br>+#include <device/pci_def.h><br>+#include <device/pnp_def.h><br>+#include <cpu/x86/lapic.h><br>+#include <arch/acpi.h><br>+#include <console/console.h><br>+#include "northbridge/intel/sandybridge/sandybridge.h"<br>+#include "northbridge/intel/sandybridge/raminit_native.h"<br>+#include "southbridge/intel/bd82x6x/pch.h"<br>+#include <southbridge/intel/common/gpio.h><br>+#include <arch/cpu.h><br>+#include <cpu/x86/msr.h><br>+<br>+void pch_enable_lpc(void)<br>+{<br>+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1401);<br>+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291);<br>+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0241);<br>+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0251);<br>+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);<br>+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);<br>+}<br>+<br>+void rcba_config(void)<br>+{<br>+ /* Disable devices. */<br>+ RCBA32(0x3414) = 0x00000000;<br>+ RCBA32(0x3418) = 0x00000000;<br>+<br>+}<br>+<br>+const struct southbridge_usb_port mainboard_usb_ports[] = {<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+ {1, 0, -1},<br>+};<br>+<br>+void mainboard_early_init(int s3resume)<br>+{<br>+}<br>+<br>+void mainboard_config_superio(void)<br>+{<br>+}<br>+<br>+/* FIXME: Put proper SPD map here. */<br>+void mainboard_get_spd(spd_raw_data *spd, bool id_only)<br>+{<br>+ read_spd(&spd[0], 0x50, id_only);<br>+ read_spd(&spd[1], 0x51, id_only);<br>+ read_spd(&spd[2], 0x52, id_only);<br>+ read_spd(&spd[3], 0x53, id_only);<br>+}<br>diff --git a/src/mainboard/asrock/h67m-itx/gnvs.c b/src/mainboard/asrock/h67m-itx/gnvs.c<br>new file mode 100644<br>index 0000000..37cd5c9<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/gnvs.c<br>@@ -0,0 +1,19 @@<br>+#include <southbridge/intel/bd82x6x/nvs.h><br>+<br>+/* FIXME: check this function. */<br>+void acpi_create_gnvs(global_nvs_t *gnvs)<br>+{<br>+ /* Disable USB ports in S3 by default */<br>+ gnvs->s3u0 = 0;<br>+ gnvs->s3u1 = 0;<br>+<br>+ /* Disable USB ports in S5 by default */<br>+ gnvs->s5u0 = 0;<br>+ gnvs->s5u1 = 0;<br>+<br>+ // the lid is open by default.<br>+ gnvs->lids = 1;<br>+<br>+ gnvs->tcrt = 100;<br>+ gnvs->tpsv = 90;<br>+}<br>diff --git a/src/mainboard/asrock/h67m-itx/gpio.c b/src/mainboard/asrock/h67m-itx/gpio.c<br>new file mode 100644<br>index 0000000..92e69dd<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/gpio.c<br>@@ -0,0 +1,433 @@<br>+#include <southbridge/intel/common/gpio.h><br>+const struct pch_gpio_set1 pch_gpio_set1_mode = {<br>+ .gpio0 = GPIO_MODE_GPIO,<br>+ .gpio1 = GPIO_MODE_GPIO,<br>+ .gpio2 = GPIO_MODE_NATIVE,<br>+ .gpio3 = GPIO_MODE_NATIVE,<br>+ .gpio4 = GPIO_MODE_NATIVE,<br>+ .gpio5 = GPIO_MODE_NATIVE,<br>+ .gpio6 = GPIO_MODE_GPIO,<br>+ .gpio7 = GPIO_MODE_GPIO,<br>+ .gpio8 = GPIO_MODE_GPIO,<br>+ .gpio9 = GPIO_MODE_NATIVE,<br>+ .gpio10 = GPIO_MODE_NATIVE,<br>+ .gpio11 = GPIO_MODE_NATIVE,<br>+ .gpio12 = GPIO_MODE_GPIO,<br>+ .gpio13 = GPIO_MODE_GPIO,<br>+ .gpio14 = GPIO_MODE_NATIVE,<br>+ .gpio15 = GPIO_MODE_GPIO,<br>+ .gpio16 = GPIO_MODE_GPIO,<br>+ .gpio17 = GPIO_MODE_GPIO,<br>+ .gpio18 = GPIO_MODE_NATIVE,<br>+ .gpio19 = GPIO_MODE_NATIVE,<br>+ .gpio20 = GPIO_MODE_NATIVE,<br>+ .gpio21 = GPIO_MODE_NATIVE,<br>+ .gpio22 = GPIO_MODE_NATIVE,<br>+ .gpio23 = GPIO_MODE_NATIVE,<br>+ .gpio24 = GPIO_MODE_GPIO,<br>+ .gpio25 = GPIO_MODE_NATIVE,<br>+ .gpio26 = GPIO_MODE_NATIVE,<br>+ .gpio27 = GPIO_MODE_GPIO,<br>+ .gpio28 = GPIO_MODE_GPIO,<br>+ .gpio29 = GPIO_MODE_GPIO,<br>+ .gpio30 = GPIO_MODE_NATIVE,<br>+ .gpio31 = GPIO_MODE_GPIO,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_direction = {<br>+ .gpio0 = GPIO_DIR_INPUT,<br>+ .gpio1 = GPIO_DIR_INPUT,<br>+ .gpio2 = GPIO_DIR_OUTPUT,<br>+ .gpio3 = GPIO_DIR_OUTPUT,<br>+ .gpio4 = GPIO_DIR_OUTPUT,<br>+ .gpio5 = GPIO_DIR_OUTPUT,<br>+ .gpio6 = GPIO_DIR_INPUT,<br>+ .gpio7 = GPIO_DIR_INPUT,<br>+ .gpio8 = GPIO_DIR_OUTPUT,<br>+ .gpio9 = GPIO_DIR_INPUT,<br>+ .gpio10 = GPIO_DIR_INPUT,<br>+ .gpio11 = GPIO_DIR_INPUT,<br>+ .gpio12 = GPIO_DIR_INPUT,<br>+ .gpio13 = GPIO_DIR_INPUT,<br>+ .gpio14 = GPIO_DIR_INPUT,<br>+ .gpio15 = GPIO_DIR_OUTPUT,<br>+ .gpio16 = GPIO_DIR_INPUT,<br>+ .gpio17 = GPIO_DIR_INPUT,<br>+ .gpio18 = GPIO_DIR_INPUT,<br>+ .gpio19 = GPIO_DIR_INPUT,<br>+ .gpio20 = GPIO_DIR_INPUT,<br>+ .gpio21 = GPIO_DIR_INPUT,<br>+ .gpio22 = GPIO_DIR_OUTPUT,<br>+ .gpio23 = GPIO_DIR_INPUT,<br>+ .gpio24 = GPIO_DIR_OUTPUT,<br>+ .gpio25 = GPIO_DIR_INPUT,<br>+ .gpio26 = GPIO_DIR_INPUT,<br>+ .gpio27 = GPIO_DIR_INPUT,<br>+ .gpio28 = GPIO_DIR_OUTPUT,<br>+ .gpio29 = GPIO_DIR_OUTPUT,<br>+ .gpio30 = GPIO_DIR_OUTPUT,<br>+ .gpio31 = GPIO_DIR_INPUT,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_level = {<br>+ .gpio0 = GPIO_LEVEL_HIGH,<br>+ .gpio1 = GPIO_LEVEL_HIGH,<br>+ .gpio2 = GPIO_LEVEL_HIGH,<br>+ .gpio3 = GPIO_LEVEL_HIGH,<br>+ .gpio4 = GPIO_LEVEL_HIGH,<br>+ .gpio5 = GPIO_LEVEL_HIGH,<br>+ .gpio6 = GPIO_LEVEL_HIGH,<br>+ .gpio7 = GPIO_LEVEL_LOW,<br>+ .gpio8 = GPIO_LEVEL_HIGH,<br>+ .gpio9 = GPIO_LEVEL_HIGH,<br>+ .gpio10 = GPIO_LEVEL_HIGH,<br>+ .gpio11 = GPIO_LEVEL_HIGH,<br>+ .gpio12 = GPIO_LEVEL_HIGH,<br>+ .gpio13 = GPIO_LEVEL_HIGH,<br>+ .gpio14 = GPIO_LEVEL_HIGH,<br>+ .gpio15 = GPIO_LEVEL_LOW,<br>+ .gpio16 = GPIO_LEVEL_LOW,<br>+ .gpio17 = GPIO_LEVEL_HIGH,<br>+ .gpio18 = GPIO_LEVEL_LOW,<br>+ .gpio19 = GPIO_LEVEL_LOW,<br>+ .gpio20 = GPIO_LEVEL_LOW,<br>+ .gpio21 = GPIO_LEVEL_HIGH,<br>+ .gpio22 = GPIO_LEVEL_HIGH,<br>+ .gpio23 = GPIO_LEVEL_HIGH,<br>+ .gpio24 = GPIO_LEVEL_LOW,<br>+ .gpio25 = GPIO_LEVEL_LOW,<br>+ .gpio26 = GPIO_LEVEL_LOW,<br>+ .gpio27 = GPIO_LEVEL_HIGH,<br>+ .gpio28 = GPIO_LEVEL_LOW,<br>+ .gpio29 = GPIO_LEVEL_HIGH,<br>+ .gpio30 = GPIO_LEVEL_HIGH,<br>+ .gpio31 = GPIO_LEVEL_LOW,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_reset = {<br>+ .gpio0 = GPIO_RESET_PWROK,<br>+ .gpio1 = GPIO_RESET_PWROK,<br>+ .gpio2 = GPIO_RESET_PWROK,<br>+ .gpio3 = GPIO_RESET_PWROK,<br>+ .gpio4 = GPIO_RESET_PWROK,<br>+ .gpio5 = GPIO_RESET_PWROK,<br>+ .gpio6 = GPIO_RESET_PWROK,<br>+ .gpio7 = GPIO_RESET_PWROK,<br>+ .gpio8 = GPIO_RESET_PWROK,<br>+ .gpio9 = GPIO_RESET_PWROK,<br>+ .gpio10 = GPIO_RESET_PWROK,<br>+ .gpio11 = GPIO_RESET_PWROK,<br>+ .gpio12 = GPIO_RESET_PWROK,<br>+ .gpio13 = GPIO_RESET_PWROK,<br>+ .gpio14 = GPIO_RESET_PWROK,<br>+ .gpio15 = GPIO_RESET_PWROK,<br>+ .gpio16 = GPIO_RESET_PWROK,<br>+ .gpio17 = GPIO_RESET_PWROK,<br>+ .gpio18 = GPIO_RESET_PWROK,<br>+ .gpio19 = GPIO_RESET_PWROK,<br>+ .gpio20 = GPIO_RESET_PWROK,<br>+ .gpio21 = GPIO_RESET_PWROK,<br>+ .gpio22 = GPIO_RESET_PWROK,<br>+ .gpio23 = GPIO_RESET_PWROK,<br>+ .gpio24 = GPIO_RESET_PWROK,<br>+ .gpio25 = GPIO_RESET_PWROK,<br>+ .gpio26 = GPIO_RESET_PWROK,<br>+ .gpio27 = GPIO_RESET_PWROK,<br>+ .gpio28 = GPIO_RESET_PWROK,<br>+ .gpio29 = GPIO_RESET_PWROK,<br>+ .gpio30 = GPIO_RESET_PWROK,<br>+ .gpio31 = GPIO_RESET_PWROK,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_invert = {<br>+ .gpio0 = GPIO_NO_INVERT,<br>+ .gpio1 = GPIO_NO_INVERT,<br>+ .gpio2 = GPIO_NO_INVERT,<br>+ .gpio3 = GPIO_NO_INVERT,<br>+ .gpio4 = GPIO_NO_INVERT,<br>+ .gpio5 = GPIO_NO_INVERT,<br>+ .gpio6 = GPIO_NO_INVERT,<br>+ .gpio7 = GPIO_NO_INVERT,<br>+ .gpio8 = GPIO_NO_INVERT,<br>+ .gpio9 = GPIO_NO_INVERT,<br>+ .gpio10 = GPIO_NO_INVERT,<br>+ .gpio11 = GPIO_NO_INVERT,<br>+ .gpio12 = GPIO_INVERT,<br>+ .gpio13 = GPIO_INVERT,<br>+ .gpio14 = GPIO_NO_INVERT,<br>+ .gpio15 = GPIO_NO_INVERT,<br>+ .gpio16 = GPIO_NO_INVERT,<br>+ .gpio17 = GPIO_NO_INVERT,<br>+ .gpio18 = GPIO_NO_INVERT,<br>+ .gpio19 = GPIO_NO_INVERT,<br>+ .gpio20 = GPIO_NO_INVERT,<br>+ .gpio21 = GPIO_NO_INVERT,<br>+ .gpio22 = GPIO_NO_INVERT,<br>+ .gpio23 = GPIO_NO_INVERT,<br>+ .gpio24 = GPIO_NO_INVERT,<br>+ .gpio25 = GPIO_NO_INVERT,<br>+ .gpio26 = GPIO_NO_INVERT,<br>+ .gpio27 = GPIO_NO_INVERT,<br>+ .gpio28 = GPIO_NO_INVERT,<br>+ .gpio29 = GPIO_NO_INVERT,<br>+ .gpio30 = GPIO_NO_INVERT,<br>+ .gpio31 = GPIO_NO_INVERT,<br>+};<br>+<br>+const struct pch_gpio_set1 pch_gpio_set1_blink = {<br>+ .gpio0 = GPIO_NO_BLINK,<br>+ .gpio1 = GPIO_NO_BLINK,<br>+ .gpio2 = GPIO_NO_BLINK,<br>+ .gpio3 = GPIO_NO_BLINK,<br>+ .gpio4 = GPIO_NO_BLINK,<br>+ .gpio5 = GPIO_NO_BLINK,<br>+ .gpio6 = GPIO_NO_BLINK,<br>+ .gpio7 = GPIO_NO_BLINK,<br>+ .gpio8 = GPIO_NO_BLINK,<br>+ .gpio9 = GPIO_NO_BLINK,<br>+ .gpio10 = GPIO_NO_BLINK,<br>+ .gpio11 = GPIO_NO_BLINK,<br>+ .gpio12 = GPIO_NO_BLINK,<br>+ .gpio13 = GPIO_NO_BLINK,<br>+ .gpio14 = GPIO_NO_BLINK,<br>+ .gpio15 = GPIO_NO_BLINK,<br>+ .gpio16 = GPIO_NO_BLINK,<br>+ .gpio17 = GPIO_NO_BLINK,<br>+ .gpio18 = GPIO_BLINK,<br>+ .gpio19 = GPIO_NO_BLINK,<br>+ .gpio20 = GPIO_NO_BLINK,<br>+ .gpio21 = GPIO_NO_BLINK,<br>+ .gpio22 = GPIO_NO_BLINK,<br>+ .gpio23 = GPIO_NO_BLINK,<br>+ .gpio24 = GPIO_NO_BLINK,<br>+ .gpio25 = GPIO_NO_BLINK,<br>+ .gpio26 = GPIO_NO_BLINK,<br>+ .gpio27 = GPIO_NO_BLINK,<br>+ .gpio28 = GPIO_NO_BLINK,<br>+ .gpio29 = GPIO_NO_BLINK,<br>+ .gpio30 = GPIO_NO_BLINK,<br>+ .gpio31 = GPIO_NO_BLINK,<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_mode = {<br>+ .gpio32 = GPIO_MODE_GPIO,<br>+ .gpio33 = GPIO_MODE_GPIO,<br>+ .gpio34 = GPIO_MODE_GPIO,<br>+ .gpio35 = GPIO_MODE_GPIO,<br>+ .gpio36 = GPIO_MODE_NATIVE,<br>+ .gpio37 = GPIO_MODE_NATIVE,<br>+ .gpio38 = GPIO_MODE_NATIVE,<br>+ .gpio39 = GPIO_MODE_NATIVE,<br>+ .gpio40 = GPIO_MODE_NATIVE,<br>+ .gpio41 = GPIO_MODE_NATIVE,<br>+ .gpio42 = GPIO_MODE_NATIVE,<br>+ .gpio43 = GPIO_MODE_NATIVE,<br>+ .gpio44 = GPIO_MODE_NATIVE,<br>+ .gpio45 = GPIO_MODE_NATIVE,<br>+ .gpio46 = GPIO_MODE_NATIVE,<br>+ .gpio47 = GPIO_MODE_NATIVE,<br>+ .gpio48 = GPIO_MODE_NATIVE,<br>+ .gpio49 = GPIO_MODE_GPIO,<br>+ .gpio50 = GPIO_MODE_NATIVE,<br>+ .gpio51 = GPIO_MODE_NATIVE,<br>+ .gpio52 = GPIO_MODE_NATIVE,<br>+ .gpio53 = GPIO_MODE_NATIVE,<br>+ .gpio54 = GPIO_MODE_NATIVE,<br>+ .gpio55 = GPIO_MODE_NATIVE,<br>+ .gpio56 = GPIO_MODE_NATIVE,<br>+ .gpio57 = GPIO_MODE_GPIO,<br>+ .gpio58 = GPIO_MODE_NATIVE,<br>+ .gpio59 = GPIO_MODE_NATIVE,<br>+ .gpio60 = GPIO_MODE_NATIVE,<br>+ .gpio61 = GPIO_MODE_NATIVE,<br>+ .gpio62 = GPIO_MODE_NATIVE,<br>+ .gpio63 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_direction = {<br>+ .gpio32 = GPIO_DIR_OUTPUT,<br>+ .gpio33 = GPIO_DIR_OUTPUT,<br>+ .gpio34 = GPIO_DIR_INPUT,<br>+ .gpio35 = GPIO_DIR_OUTPUT,<br>+ .gpio36 = GPIO_DIR_INPUT,<br>+ .gpio37 = GPIO_DIR_INPUT,<br>+ .gpio38 = GPIO_DIR_OUTPUT,<br>+ .gpio39 = GPIO_DIR_OUTPUT,<br>+ .gpio40 = GPIO_DIR_INPUT,<br>+ .gpio41 = GPIO_DIR_INPUT,<br>+ .gpio42 = GPIO_DIR_INPUT,<br>+ .gpio43 = GPIO_DIR_INPUT,<br>+ .gpio44 = GPIO_DIR_INPUT,<br>+ .gpio45 = GPIO_DIR_INPUT,<br>+ .gpio46 = GPIO_DIR_INPUT,<br>+ .gpio47 = GPIO_DIR_INPUT,<br>+ .gpio48 = GPIO_DIR_OUTPUT,<br>+ .gpio49 = GPIO_DIR_INPUT,<br>+ .gpio50 = GPIO_DIR_INPUT,<br>+ .gpio51 = GPIO_DIR_OUTPUT,<br>+ .gpio52 = GPIO_DIR_INPUT,<br>+ .gpio53 = GPIO_DIR_OUTPUT,<br>+ .gpio54 = GPIO_DIR_INPUT,<br>+ .gpio55 = GPIO_DIR_OUTPUT,<br>+ .gpio56 = GPIO_DIR_INPUT,<br>+ .gpio57 = GPIO_DIR_INPUT,<br>+ .gpio58 = GPIO_DIR_INPUT,<br>+ .gpio59 = GPIO_DIR_INPUT,<br>+ .gpio60 = GPIO_DIR_INPUT,<br>+ .gpio61 = GPIO_DIR_OUTPUT,<br>+ .gpio62 = GPIO_DIR_OUTPUT,<br>+ .gpio63 = GPIO_DIR_OUTPUT,<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_level = {<br>+ .gpio32 = GPIO_LEVEL_HIGH,<br>+ .gpio33 = GPIO_LEVEL_HIGH,<br>+ .gpio34 = GPIO_LEVEL_HIGH,<br>+ .gpio35 = GPIO_LEVEL_LOW,<br>+ .gpio36 = GPIO_LEVEL_LOW,<br>+ .gpio37 = GPIO_LEVEL_LOW,<br>+ .gpio38 = GPIO_LEVEL_LOW,<br>+ .gpio39 = GPIO_LEVEL_LOW,<br>+ .gpio40 = GPIO_LEVEL_HIGH,<br>+ .gpio41 = GPIO_LEVEL_HIGH,<br>+ .gpio42 = GPIO_LEVEL_HIGH,<br>+ .gpio43 = GPIO_LEVEL_HIGH,<br>+ .gpio44 = GPIO_LEVEL_HIGH,<br>+ .gpio45 = GPIO_LEVEL_HIGH,<br>+ .gpio46 = GPIO_LEVEL_HIGH,<br>+ .gpio47 = GPIO_LEVEL_LOW,<br>+ .gpio48 = GPIO_LEVEL_LOW,<br>+ .gpio49 = GPIO_LEVEL_LOW,<br>+ .gpio50 = GPIO_LEVEL_HIGH,<br>+ .gpio51 = GPIO_LEVEL_HIGH,<br>+ .gpio52 = GPIO_LEVEL_HIGH,<br>+ .gpio53 = GPIO_LEVEL_HIGH,<br>+ .gpio54 = GPIO_LEVEL_HIGH,<br>+ .gpio55 = GPIO_LEVEL_HIGH,<br>+ .gpio56 = GPIO_LEVEL_LOW,<br>+ .gpio57 = GPIO_LEVEL_LOW,<br>+ .gpio58 = GPIO_LEVEL_HIGH,<br>+ .gpio59 = GPIO_LEVEL_HIGH,<br>+ .gpio60 = GPIO_LEVEL_HIGH,<br>+ .gpio61 = GPIO_LEVEL_HIGH,<br>+ .gpio62 = GPIO_LEVEL_LOW,<br>+ .gpio63 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+const struct pch_gpio_set2 pch_gpio_set2_reset = {<br>+ .gpio32 = GPIO_RESET_PWROK,<br>+ .gpio33 = GPIO_RESET_PWROK,<br>+ .gpio34 = GPIO_RESET_PWROK,<br>+ .gpio35 = GPIO_RESET_PWROK,<br>+ .gpio36 = GPIO_RESET_PWROK,<br>+ .gpio37 = GPIO_RESET_PWROK,<br>+ .gpio38 = GPIO_RESET_PWROK,<br>+ .gpio39 = GPIO_RESET_PWROK,<br>+ .gpio40 = GPIO_RESET_PWROK,<br>+ .gpio41 = GPIO_RESET_PWROK,<br>+ .gpio42 = GPIO_RESET_PWROK,<br>+ .gpio43 = GPIO_RESET_PWROK,<br>+ .gpio44 = GPIO_RESET_PWROK,<br>+ .gpio45 = GPIO_RESET_PWROK,<br>+ .gpio46 = GPIO_RESET_PWROK,<br>+ .gpio47 = GPIO_RESET_PWROK,<br>+ .gpio48 = GPIO_RESET_PWROK,<br>+ .gpio49 = GPIO_RESET_PWROK,<br>+ .gpio50 = GPIO_RESET_PWROK,<br>+ .gpio51 = GPIO_RESET_PWROK,<br>+ .gpio52 = GPIO_RESET_PWROK,<br>+ .gpio53 = GPIO_RESET_PWROK,<br>+ .gpio54 = GPIO_RESET_PWROK,<br>+ .gpio55 = GPIO_RESET_PWROK,<br>+ .gpio56 = GPIO_RESET_PWROK,<br>+ .gpio57 = GPIO_RESET_PWROK,<br>+ .gpio58 = GPIO_RESET_PWROK,<br>+ .gpio59 = GPIO_RESET_PWROK,<br>+ .gpio60 = GPIO_RESET_PWROK,<br>+ .gpio61 = GPIO_RESET_PWROK,<br>+ .gpio62 = GPIO_RESET_PWROK,<br>+ .gpio63 = GPIO_RESET_PWROK,<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_mode = {<br>+ .gpio64 = GPIO_MODE_NATIVE,<br>+ .gpio65 = GPIO_MODE_NATIVE,<br>+ .gpio66 = GPIO_MODE_NATIVE,<br>+ .gpio67 = GPIO_MODE_NATIVE,<br>+ .gpio68 = GPIO_MODE_GPIO,<br>+ .gpio69 = GPIO_MODE_GPIO,<br>+ .gpio70 = GPIO_MODE_NATIVE,<br>+ .gpio71 = GPIO_MODE_NATIVE,<br>+ .gpio72 = GPIO_MODE_GPIO,<br>+ .gpio73 = GPIO_MODE_NATIVE,<br>+ .gpio74 = GPIO_MODE_NATIVE,<br>+ .gpio75 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_direction = {<br>+ .gpio64 = GPIO_DIR_OUTPUT,<br>+ .gpio65 = GPIO_DIR_OUTPUT,<br>+ .gpio66 = GPIO_DIR_OUTPUT,<br>+ .gpio67 = GPIO_DIR_OUTPUT,<br>+ .gpio68 = GPIO_DIR_INPUT,<br>+ .gpio69 = GPIO_DIR_INPUT,<br>+ .gpio70 = GPIO_DIR_INPUT,<br>+ .gpio71 = GPIO_DIR_INPUT,<br>+ .gpio72 = GPIO_DIR_INPUT,<br>+ .gpio73 = GPIO_DIR_INPUT,<br>+ .gpio74 = GPIO_DIR_INPUT,<br>+ .gpio75 = GPIO_DIR_INPUT,<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_level = {<br>+ .gpio64 = GPIO_LEVEL_HIGH,<br>+ .gpio65 = GPIO_LEVEL_HIGH,<br>+ .gpio66 = GPIO_LEVEL_HIGH,<br>+ .gpio67 = GPIO_LEVEL_HIGH,<br>+ .gpio68 = GPIO_LEVEL_HIGH,<br>+ .gpio69 = GPIO_LEVEL_HIGH,<br>+ .gpio70 = GPIO_LEVEL_HIGH,<br>+ .gpio71 = GPIO_LEVEL_HIGH,<br>+ .gpio72 = GPIO_LEVEL_HIGH,<br>+ .gpio73 = GPIO_LEVEL_LOW,<br>+ .gpio74 = GPIO_LEVEL_HIGH,<br>+ .gpio75 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+const struct pch_gpio_set3 pch_gpio_set3_reset = {<br>+ .gpio64 = GPIO_RESET_PWROK,<br>+ .gpio65 = GPIO_RESET_PWROK,<br>+ .gpio66 = GPIO_RESET_PWROK,<br>+ .gpio67 = GPIO_RESET_PWROK,<br>+ .gpio68 = GPIO_RESET_PWROK,<br>+ .gpio69 = GPIO_RESET_PWROK,<br>+ .gpio70 = GPIO_RESET_PWROK,<br>+ .gpio71 = GPIO_RESET_PWROK,<br>+ .gpio72 = GPIO_RESET_PWROK,<br>+ .gpio73 = GPIO_RESET_PWROK,<br>+ .gpio74 = GPIO_RESET_PWROK,<br>+ .gpio75 = GPIO_RESET_PWROK,<br>+};<br>+<br>+const struct pch_gpio_map mainboard_gpio_map = {<br>+ .set1 = {<br>+ .mode = &pch_gpio_set1_mode,<br>+ .direction = &pch_gpio_set1_direction,<br>+ .level = &pch_gpio_set1_level,<br>+ .blink = &pch_gpio_set1_blink,<br>+ .invert = &pch_gpio_set1_invert,<br>+ .reset = &pch_gpio_set1_reset,<br>+ },<br>+ .set2 = {<br>+ .mode = &pch_gpio_set2_mode,<br>+ .direction = &pch_gpio_set2_direction,<br>+ .level = &pch_gpio_set2_level,<br>+ .reset = &pch_gpio_set2_reset,<br>+ },<br>+ .set3 = {<br>+ .mode = &pch_gpio_set3_mode,<br>+ .direction = &pch_gpio_set3_direction,<br>+ .level = &pch_gpio_set3_level,<br>+ .reset = &pch_gpio_set3_reset,<br>+ },<br>+};<br>diff --git a/src/mainboard/asrock/h67m-itx/hda_verb.c b/src/mainboard/asrock/h67m-itx/hda_verb.c<br>new file mode 100644<br>index 0000000..6e130a9<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/hda_verb.c<br>@@ -0,0 +1,71 @@<br>+#include <device/azalia_device.h><br>+<br>+const u32 cim_verb_data[] = {<br>+ 0x10ec0892, /* Codec Vendor / Device ID: Realtek */<br>+ 0x18491892, /* Subsystem ID */<br>+<br>+ 0x0000000f, /* Number of 4 dword sets */<br>+ /* NID 0x01: Subsystem ID. */<br>+ AZALIA_SUBVENDOR(0x0, 0x18491892),<br>+<br>+ /* NID 0x11. */<br>+ AZALIA_PIN_CFG(0x0, 0x11, 0x411111f0),<br>+<br>+ /* NID 0x12. */<br>+ AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0),<br>+<br>+ /* NID 0x14. */<br>+ AZALIA_PIN_CFG(0x0, 0x14, 0x01014010),<br>+<br>+ /* NID 0x15. */<br>+ AZALIA_PIN_CFG(0x0, 0x15, 0x01011012),<br>+<br>+ /* NID 0x16. */<br>+ AZALIA_PIN_CFG(0x0, 0x16, 0x01016011),<br>+<br>+ /* NID 0x17. */<br>+ AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0),<br>+<br>+ /* NID 0x18. */<br>+ AZALIA_PIN_CFG(0x0, 0x18, 0x01a19840),<br>+<br>+ /* NID 0x19. */<br>+ AZALIA_PIN_CFG(0x0, 0x19, 0x02a19950),<br>+<br>+ /* NID 0x1a. */<br>+ AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f),<br>+<br>+ /* NID 0x1b. */<br>+ AZALIA_PIN_CFG(0x0, 0x1b, 0x02214120),<br>+<br>+ /* NID 0x1c. */<br>+ AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0),<br>+<br>+ /* NID 0x1d. */<br>+ AZALIA_PIN_CFG(0x0, 0x1d, 0x4005e601),<br>+<br>+ /* NID 0x1e. */<br>+ AZALIA_PIN_CFG(0x0, 0x1e, 0x01452130),<br>+<br>+ /* NID 0x1f. */<br>+ AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0),<br>+ 0x80862805, /* Codec Vendor / Device ID: Intel */<br>+ 0x80860101, /* Subsystem ID */<br>+<br>+ 0x00000004, /* Number of 4 dword sets */<br>+ /* NID 0x01: Subsystem ID. */<br>+ AZALIA_SUBVENDOR(0x3, 0x80860101),<br>+<br>+ /* NID 0x05. */<br>+ AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),<br>+<br>+ /* NID 0x06. */<br>+ AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),<br>+<br>+ /* NID 0x07. */<br>+ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030),<br>+};<br>+<br>+const u32 pc_beep_verbs[0] = { };<br>+<br>+AZALIA_ARRAY_SIZES;<br>diff --git a/src/mainboard/asrock/h67m-itx/mainboard.c b/src/mainboard/asrock/h67m-itx/mainboard.c<br>new file mode 100644<br>index 0000000..d534fa5<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/mainboard.c<br>@@ -0,0 +1,23 @@<br>+#include <device/device.h><br>+#include <drivers/intel/gma/int15.h><br>+#include <southbridge/intel/bd82x6x/pch.h><br>+<br>+static void mainboard_init(device_t dev)<br>+{<br>+ RCBA32(0x38c8) = 0x00000000;<br>+ RCBA32(0x38c4) = 0x00000000;<br>+}<br>+<br>+static void mainboard_enable(device_t dev)<br>+{<br>+ dev->ops->init = mainboard_init;<br>+<br>+ /* FIXME: fix those values */<br>+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,<br>+ GMA_INT15_PANEL_FIT_DEFAULT,<br>+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);<br>+}<br>+<br>+struct chip_operations mainboard_ops = {<br>+ .enable_dev = mainboard_enable,<br>+};<br>diff --git a/src/mainboard/asrock/h67m-itx/romstage.c b/src/mainboard/asrock/h67m-itx/romstage.c<br>new file mode 100644<br>index 0000000..2997587<br>--- /dev/null<br>+++ b/src/mainboard/asrock/h67m-itx/romstage.c<br>@@ -0,0 +1 @@<br>+/* dummy */<br></pre><p>To view, visit <a href="https://review.coreboot.org/21428">change 21428</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21428"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I67c72ea36ec8bead9123606bee4cdd7b36068de9 </div>
<div style="display:none"> Gerrit-Change-Number: 21428 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Felix Singer <singer.felix@t-online.de> </div>