<p>Rizwan Qureshi has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21401">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Add config for Enbaling PCIe AER<br><br>Add a config for enabling/disabling Advanced Error Reporting feature<br>for PCIe root ports.<br><br>BUG=b:64798078<br>TEST="lspci" shows that AER is enabled in the capabilities list.<br><br>Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a<br>Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com><br>---<br>M src/soc/intel/skylake/chip.h<br>M src/soc/intel/skylake/chip_fsp20.c<br>2 files changed, 4 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/21401/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h<br>index beb5a7a..45f3f99 100644<br>--- a/src/soc/intel/skylake/chip.h<br>+++ b/src/soc/intel/skylake/chip.h<br>@@ -173,6 +173,7 @@<br>        u8 PcieRpEnable[CONFIG_MAX_ROOT_PORTS];<br>       u8 PcieRpClkReqSupport[CONFIG_MAX_ROOT_PORTS];<br>        u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS];<br>+        u8 PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];<br> <br>    /* USB related */<br>     struct usb2_port_config usb2_ports[16];<br>diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c<br>index aa612ed..adf8772 100644<br>--- a/src/soc/intel/skylake/chip_fsp20.c<br>+++ b/src/soc/intel/skylake/chip_fsp20.c<br>@@ -166,6 +166,9 @@<br>                sizeof(params->PcieRpClkReqSupport));<br>       memcpy(params->PcieRpClkReqNumber, config->PcieRpClkReqNumber,<br>         sizeof(params->PcieRpClkReqNumber));<br>+       memcpy(params->PcieRpAdvancedErrorReporting,<br>+              config->PcieRpAdvancedErrorReporting,<br>+                     sizeof(params->PcieRpAdvancedErrorReporting));<br> <br>  /* disable Legacy PME */<br>      memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci));<br></pre><p>To view, visit <a href="https://review.coreboot.org/21401">change 21401</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21401"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a </div>
<div style="display:none"> Gerrit-Change-Number: 21401 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>