<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21370">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/braswell: Add I2C clock config options<br><br>Cherry-pick from Chromium commit e3c1ec2.<br><br>This change includes<br>- FSP config parameters to configure I2C clock speed.<br>- Options are 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz and default is 400Khz.<br><br>Original-Change-Id: Iab2bf3997102908583078f5f1d185d6c66561390<br>Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com><br>Original-Tested-by: Kenji Chen <kenji.chen@intel.com><br>Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org><br><br>Change-Id: Ifae3ba4262cb3cc6416ce5054614ed7765e22c25<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/braswell/chip.c<br>M src/soc/intel/braswell/chip.h<br>2 files changed, 14 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/21370/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c<br>index 4d7b906..91cb384 100644<br>--- a/src/soc/intel/braswell/chip.c<br>+++ b/src/soc/intel/braswell/chip.c<br>@@ -162,6 +162,13 @@<br>    params->ISPEnable = config->ISPEnable;<br>  params->ISPPciDevConfig = config->ISPPciDevConfig;<br>      params->PcdSdDetectChk = config->PcdSdDetectChk;<br>+       params->I2C0Frequency = config->I2C0Frequency;<br>+ params->I2C1Frequency = config->I2C1Frequency;<br>+ params->I2C2Frequency = config->I2C2Frequency;<br>+ params->I2C3Frequency = config->I2C3Frequency;<br>+ params->I2C4Frequency = config->I2C4Frequency;<br>+ params->I2C5Frequency = config->I2C5Frequency;<br>+ params->I2C6Frequency = config->I2C6Frequency;<br> }<br> <br> void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,<br>diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h<br>index 8c3f143..c661bb4 100644<br>--- a/src/soc/intel/braswell/chip.h<br>+++ b/src/soc/intel/braswell/chip.h<br>@@ -161,6 +161,13 @@<br>    UINT8  ISPEnable;<br>     UINT8  ISPPciDevConfig;<br>       UINT8  PcdSdDetectChk; /*Enable\Disable SD Card Detect Simulation*/<br>+  UINT8  I2C0Frequency;  /* 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz */<br>+        UINT8  I2C1Frequency;<br>+        UINT8  I2C2Frequency;<br>+        UINT8  I2C3Frequency;<br>+        UINT8  I2C4Frequency;<br>+        UINT8  I2C5Frequency;<br>+        UINT8  I2C6Frequency;<br> };<br> <br> extern struct chip_operations soc_intel_braswell_ops;<br></pre><p>To view, visit <a href="https://review.coreboot.org/21370">change 21370</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21370"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifae3ba4262cb3cc6416ce5054614ed7765e22c25 </div>
<div style="display:none"> Gerrit-Change-Number: 21370 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>