<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21372">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/braswell: Add USB2 phy setting override<br><br>Adapted from Chromium commit 9756af8.<br><br>Create hook function to override USB2 phy setting from board level.<br><br>Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e<br>Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org><br>Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com><br><br>Change-Id: If2ac687f6fc44e4c022a72eea7f08cb6385f0380<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/soc/intel/braswell/chip.c<br>M src/soc/intel/braswell/include/soc/ramstage.h<br>2 files changed, 6 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21372/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c<br>index e0c1a51..afa90c3 100644<br>--- a/src/soc/intel/braswell/chip.c<br>+++ b/src/soc/intel/braswell/chip.c<br>@@ -81,6 +81,10 @@<br>   }<br> }<br> <br>+__attribute__((weak)) void board_silicon_USB2_override(SILICON_INIT_UPD *params)<br>+{<br>+}<br>+<br> void soc_silicon_init_params(SILICON_INIT_UPD *params)<br> {<br>   device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));<br>@@ -170,6 +174,7 @@<br>   params->I2C5Frequency = config->I2C5Frequency;<br>  params->I2C6Frequency = config->I2C6Frequency;<br> <br>+      board_silicon_USB2_override(params);<br> }<br> <br> void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,<br>diff --git a/src/soc/intel/braswell/include/soc/ramstage.h b/src/soc/intel/braswell/include/soc/ramstage.h<br>index 8f5f9a5..c566201 100644<br>--- a/src/soc/intel/braswell/include/soc/ramstage.h<br>+++ b/src/soc/intel/braswell/include/soc/ramstage.h<br>@@ -101,6 +101,7 @@<br> void southcluster_enable_dev(device_t dev);<br> void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index);<br> int SocStepping(void);<br>+void board_silicon_USB2_override(SILICON_INIT_UPD *params);<br> <br> extern struct pci_operations soc_pci_ops;<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21372">change 21372</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21372"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: If2ac687f6fc44e4c022a72eea7f08cb6385f0380 </div>
<div style="display:none"> Gerrit-Change-Number: 21372 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>