<p>Keith Hui has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21375">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">cpu/intel/car/cache_as_ram.inc: Remove superfluous code<br><br>Remove CAR testing code currently blocked out by #if. Newer CAR code<br>don't even do it anymore.<br><br>Remove Hyperthreading related code that is not even working according to<br>Kyösti Mälkki.<br><br>Do not set %ebp before and switch directly to stack returned by<br>romstage_main().<br><br>Remove an unneeded 4-byte gap in CAR stack.<br><br>Fix the ROM XIP area caching strategy; should be WRPROT.<br><br>Clarify the purpose of various logic in the file.<br><br>Change-Id: I27e329a7b667ce4405fe07a637edbc6b5be22f2d<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>---<br>M src/cpu/intel/car/cache_as_ram.inc<br>1 file changed, 23 insertions(+), 154 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/21375/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc<br>index ac17571..d208cee 100644<br>--- a/src/cpu/intel/car/cache_as_ram.inc<br>+++ b/src/cpu/intel/car/cache_as_ram.inc<br>@@ -22,88 +22,10 @@<br> #include <cpu/x86/lapic_def.h><br> #include <cpu/x86/post_code.h><br> <br>-#define CacheSize CONFIG_DCACHE_RAM_SIZE<br>-#define CacheBase (0xd0000 - CacheSize)<br>-<br> /* Save the BIST result. */<br> movl %eax, %ebp<br> <br> CacheAsRam:<br>- /* Check whether the processor has HT capability. */<br>- movl $01, %eax<br>- cpuid<br>- btl $28, %edx<br>- jnc NotHtProcessor<br>- bswapl %ebx<br>- cmpb $01, %bh<br>- jbe NotHtProcessor<br>-<br>- /*<br>- * It is a HT processor. Send SIPI to the other logical processor<br>- * within this processor so that the CAR related common system<br>- * registers are programmed accordingly.<br>- */<br>-<br>- /*<br>- * Use some register that is common to both logical processors<br>- * as semaphore. Refer Appendix B, Vol.3.<br>- */<br>- xorl %eax, %eax<br>- xorl %edx, %edx<br>- movl $MTRR_FIX_64K_00000, %ecx<br>- wrmsr<br>-<br>- /*<br>- * Figure out the logical AP's APIC ID; the following logic will<br>- * work only for processors with 2 threads.<br>- * Refer to Vol 3. Table 7-1 for details about this logic.<br>- */<br>- movl $0xFEE00020, %esi<br>- movl (%esi), %ebx<br>- andl $0xFF000000, %ebx<br>- bswapl %ebx<br>- btl $0, %ebx<br>- jnc LogicalAP0<br>- andb $0xFE, %bl<br>- jmp Send_SIPI<br>-LogicalAP0:<br>- orb $0x01, %bl<br>-Send_SIPI:<br>- bswapl %ebx /* EBX - logical AP's APIC ID. */<br>-<br>- /*<br>- * Fill up the IPI command registers in the Local APIC mapped to<br>- * default address and issue SIPI to the other logical processor<br>- * within this processor die.<br>- */<br>-Retry_SIPI:<br>- movl %ebx, %eax<br>- movl $0xFEE00310, %esi<br>- movl %eax, (%esi)<br>-<br>- /* SIPI vector - F900:0000 */<br>- movl $0x000006F9, %eax<br>- movl $0xFEE00300, %esi<br>- movl %eax, (%esi)<br>-<br>- movl $0x30, %ecx<br>-SIPI_Delay:<br>- pause<br>- decl %ecx<br>- jnz SIPI_Delay<br>-<br>- movl (%esi), %eax<br>- andl $0x00001000, %eax<br>- jnz Retry_SIPI<br>-<br>- /* Wait for the Logical AP to complete initialization. */<br>-LogicalAP_SIPINotdone:<br>- movl $MTRR_FIX_64K_00000, %ecx<br>- rdmsr<br>- orl %eax, %eax<br>- jz LogicalAP_SIPINotdone<br>-<br>-NotHtProcessor:<br> /* Set the default memory type and enable fixed and variable MTRRs. */<br> movl $MTRR_DEF_TYPE_MSR, %ecx<br> xorl %edx, %edx<br>@@ -203,32 +125,29 @@<br> */<br> .endm<br> <br>-#if CacheSize > 0x10000<br>+#if CONFIG_DCACHE_RAM_SIZE > 0x10000<br> #error Invalid CAR size, must be at most 64k.<br> #endif<br>-#if CacheSize < 0x1000<br>+#if CONFIG_DCACHE_RAM_SIZE < 0x1000<br> #error Invalid CAR size, must be at least 4k. This is a processor limitation.<br> #endif<br>-#if (CacheSize & (0x1000 - 1))<br>+#if (CONFIG_DCACHE_RAM_SIZE & (0x1000 - 1))<br> #error Invalid CAR size, is not a multiple of 4k. This is a processor limitation.<br> #endif<br> <br>-#if CacheSize > 0x8000<br>+#if CONFIG_DCACHE_RAM_SIZE > 0x8000<br> /* Enable caching for 32K-64K using fixed MTRR. */<br> movl $MTRR_FIX_4K_C0000, %ecx<br>- simplemask CacheSize, 0x8000<br>+ simplemask CONFIG_DCACHE_RAM_SIZE, 0x8000<br> wrmsr<br> #endif<br> <br> /* Enable caching for 0-32K using fixed MTRR. */<br> movl $MTRR_FIX_4K_C8000, %ecx<br>- simplemask CacheSize, 0<br>+ simplemask CONFIG_DCACHE_RAM_SIZE, 0<br> wrmsr<br> <br>- /*<br>- * Enable write base caching so we can do execute in place (XIP)<br>- * on the flash ROM.<br>- */<br>+ /* Enable cache for our code in Flash because we do XIP here. */<br> movl $MTRR_PHYS_BASE(1), %ecx<br> xorl %edx, %edx<br> /*<br>@@ -237,7 +156,7 @@<br> */<br> movl $copy_and_run, %eax<br> andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax<br>- orl $MTRR_TYPE_WRBACK, %eax<br>+ orl $MTRR_TYPE_WRPROT, %eax<br> wrmsr<br> <br> movl $MTRR_PHYS_MASK(1), %ecx<br>@@ -250,77 +169,31 @@<br> andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax<br> movl %eax, %cr0<br> <br>- /* Read the range with lodsl. */<br>- movl $CacheBase, %esi<br>+ /* Read the CAR region. This will also fill up the cache.<br>+ * IMPORTANT: This step is mandatory.<br>+ */<br>+ movl $CONFIG_DCACHE_RAM_BASE, %esi<br> cld<br>- movl $(CacheSize >> 2), %ecx<br>+ movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx<br> rep lodsl<br> <br>- /* Clear the range. */<br>- movl $CacheBase, %edi<br>- movl $(CacheSize >> 2), %ecx<br>+ /* Clear the CAR region. */<br>+ movl $CONFIG_DCACHE_RAM_BASE, %edi<br>+ movl $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx<br> xorl %eax, %eax<br> rep stosl<br> <br>-#if 0<br>- /* Check the cache as ram. */<br>- movl $CacheBase, %esi<br>- movl $(CacheSize >> 2), %ecx<br>-.xin1:<br>- movl %esi, %eax<br>- movl %eax, (%esi)<br>- decl %ecx<br>- je .xout1<br>- add $4, %esi<br>- jmp .xin1<br>-.xout1:<br>-<br>- movl $CacheBase, %esi<br>- // movl $(CacheSize >> 2), %ecx<br>- movl $4, %ecx<br>-.xin1x:<br>- movl %esi, %eax<br>-<br>- movl $0x4000, %edx<br>- movb %ah, %al<br>-.testx1:<br>- outb %al, $0x80<br>- decl %edx<br>- jnz .testx1<br>-<br>- movl (%esi), %eax<br>- cmpb 0xff, %al<br>- je .xin2 /* Don't show. */<br>-<br>- movl $0x4000, %edx<br>-.testx2:<br>- outb %al, $0x80<br>- decl %edx<br>- jnz .testx2<br>-<br>-.xin2:<br>- decl %ecx<br>- je .xout1x<br>- add $4, %esi<br>- jmp .xin1x<br>-.xout1x:<br>-#endif<br>-<br>- movl $(CacheBase + CacheSize - 4), %eax<br>+ movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE), %eax<br> movl %eax, %esp<br> lout:<br> /* Restore the BIST result. */<br> movl %ebp, %eax<br> <br>- /* We need to set EBP? No need. */<br>- movl %esp, %ebp<br> pushl %eax /* BIST */<br> call romstage_main<br> <br>- /* Save return value from romstage_main. It contains the stack to use<br>- * after cache-as-ram is torn down.<br>- */<br>- movl %eax, %ebx<br>+ /* Setup stack as indicated by return value from romstage_main(). */<br>+ movl %eax, %esp<br> <br> /* We don't need CAR from now on. */<br> <br>@@ -329,7 +202,7 @@<br> orl $CR0_CacheDisable, %eax<br> movl %eax, %cr0<br> <br>- /* Clear sth. */<br>+ /* Clear the fixed MTRR we used. */<br> movl $MTRR_FIX_4K_C8000, %ecx<br> xorl %edx, %edx<br> xorl %eax, %eax<br>@@ -341,12 +214,12 @@<br> #endif<br> <br> /*<br>- * Set the default memory type and disable fixed<br>- * and enable variable MTRRs.<br>+ * Enable variable and disable fixed MTRRs.<br>+ * Default memory type will be UC.<br> */<br> movl $MTRR_DEF_TYPE_MSR, %ecx<br> xorl %edx, %edx<br>- movl $MTRR_DEF_TYPE_EN, %eax /* Enable variable and disable fixed MTRRs. */<br>+ movl $MTRR_DEF_TYPE_EN, %eax<br> wrmsr<br> <br> /* Enable cache. */<br>@@ -357,10 +230,6 @@<br> __main:<br> post_code(POST_PREPARE_RAMSTAGE)<br> cld /* Clear direction flag. */<br>-<br>- /* Setup stack as indicated by return value from romstage_main(). */<br>- movl %ebx, %esp<br>- movl %esp, %ebp<br> call copy_and_run<br> <br> .Lhlt:<br></pre><p>To view, visit <a href="https://review.coreboot.org/21375">change 21375</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I27e329a7b667ce4405fe07a637edbc6b5be22f2d </div>
<div style="display:none"> Gerrit-Change-Number: 21375 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>