<p>Matt DeVillier has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21368">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">vc/intel/fsp/fsp1_1/braswell: Update FspUpdVpd.h to v 1.1.7.0<br><br>Cherry-pick from Chromium 414024e.<br><br>Update the FSP 1.1 header to version 1.1.7.0, required for<br>susequent Chromium cherry-picks and to-be-merged Braswell CrOS devices.<br><br>As this header update doesn't shift offsets, only adds new fields<br>in previously unused/reserved space, it should not negatively impact<br>existing boards built against the older header version.<br><br>Original-Change-Id: Ic378b3c10769c10d8e47c8c76b8e397ddb9ce020<br>Original-Signed-off-by: Martin Roth <martinroth@google.com><br>Original-Reviewed-by: Hannah Williams <hannah.williams@intel.com><br>Original-Reviewed-by: Stefan Reinauer <reinauer@google.com><br>Original-Tested-by: Martin Roth <martinroth@chromium.org><br><br>Change-Id: Id33d41dee998cfa033264a98dfee40e2d8feead8<br>Signed-off-by: Matt DeVillier <matt.devillier@gmail.com><br>---<br>M src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h<br>1 file changed, 81 insertions(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/21368/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h<br>index 61673c6..1ae1d03 100644<br>--- a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h<br>+++ b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h<br>@@ -1,6 +1,6 @@<br> /** @file<br> <br>-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR><br>+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR><br> <br> Redistribution and use in source and binary forms, with or without modification,<br> are permitted provided that the following conditions are met:<br>@@ -193,8 +193,43 @@<br> **/<br> UINT8 PcdCaMirrorEn;<br> /** Offset 0x0043<br>+ DDR3 Auto Self Refresh<br>+ Enable/Disable DDR3 Auto Self Refresh<br> **/<br>- UINT8 ReservedMemoryInitUpd[189];<br>+ UINT8 PcdDdr3AutoSelfRefreshEnable;<br>+/** Offset 0x0044<br>+ Disable Auto Detect Dram for LPDDR3 memory<br>+ To Enable/Disable AutoDetectDram<br>+**/<br>+ UINT8 PcdDisableAutoDetectDram;<br>+/** Offset 0x0045<br>+ Dram Width<br>+ Select Dram Width<br>+**/<br>+ UINT8 PcdDramWidth;<br>+/** Offset 0x0046<br>+ Dual Rank Enable<br>+ To Enable/Disable DualRankDram<br>+**/<br>+ UINT8 PcdDualRankDram;<br>+/** Offset 0x0047<br>+ Dram Density<br>+ Select Dram Density<br>+**/<br>+ UINT8 PcdDramDensity;<br>+/** Offset 0x0048<br>+ Channel 0 RX ODT Limit For Rx Power Training<br>+ Select RX ODT Limit for Channel 0<br>+**/<br>+ UINT8 PcdRxOdtLimitChannel0;<br>+/** Offset 0x0049<br>+ Channel 1 RX ODT Limit For Rx Power Training<br>+ Select RX ODT Limit for Channel 1<br>+**/<br>+ UINT8 PcdRxOdtLimitChannel1;<br>+/** Offset 0x004A<br>+**/<br>+ UINT8 ReservedMemoryInitUpd[182];<br> } MEMORY_INIT_UPD;<br> <br> typedef struct {<br>@@ -441,8 +476,8 @@<br> **/<br> UINT8 PcdTurboMode;<br> /** Offset 0x0161<br>- Pnp-Power & Performance<br>- select Pnp type<br>+ Pnp Setting Type<br>+ Select Pnp type<br> **/<br> UINT8 PcdPnpSettings;<br> /** Offset 0x0162<br>@@ -452,7 +487,46 @@<br> UINT8 PcdSdDetectChk;<br> /** Offset 0x0163<br> **/<br>- UINT8 ReservedSiliconInitUpd[411];<br>+ UINT8 I2C0Frequency;<br>+/** Offset 0x0164<br>+**/<br>+ UINT8 I2C1Frequency;<br>+/** Offset 0x0165<br>+**/<br>+ UINT8 I2C2Frequency;<br>+/** Offset 0x0166<br>+**/<br>+ UINT8 I2C3Frequency;<br>+/** Offset 0x0167<br>+**/<br>+ UINT8 I2C4Frequency;<br>+/** Offset 0x0168<br>+**/<br>+ UINT8 I2C5Frequency;<br>+/** Offset 0x0169<br>+**/<br>+ UINT8 I2C6Frequency;<br>+/** Offset 0x016A<br>+**/<br>+ UINT8 D0Usb2Port0PerPortRXISet;<br>+/** Offset 0x016B<br>+**/<br>+ UINT8 D0Usb2Port1PerPortRXISet;<br>+/** Offset 0x016C<br>+**/<br>+ UINT8 D0Usb2Port2PerPortRXISet;<br>+/** Offset 0x016D<br>+**/<br>+ UINT8 D0Usb2Port3PerPortRXISet;<br>+/** Offset 0x016E<br>+**/<br>+ UINT8 D0Usb2Port4PerPortRXISet;<br>+/** Offset 0x016F<br>+**/<br>+ UINT8 D0VnnBump100mV;<br>+/** Offset 0x170<br>+**/<br>+ UINT8 ReservedSiliconInitUpd[398];<br> } SILICON_INIT_UPD;<br> <br> #define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */<br>@@ -484,13 +558,13 @@<br> /** Offset 0x0100<br> **/<br> SILICON_INIT_UPD SiliconInitUpd;<br>-/** Offset 0x02FE<br>+/** Offset 0x0305<br> **/<br> UINT16 PcdRegionTerminator;<br> } UPD_DATA_REGION;<br> <br> #define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */<br>-#define FSP_IMAGE_REV 0x01010100<br>+#define FSP_IMAGE_REV 0x01010700<br> <br> typedef struct _VPD_DATA_REGION {<br> /** Offset 0x0000<br></pre><p>To view, visit <a href="https://review.coreboot.org/21368">change 21368</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id33d41dee998cfa033264a98dfee40e2d8feead8 </div>
<div style="display:none"> Gerrit-Change-Number: 21368 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Matt DeVillier <matt.devillier@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>