<p>Damien Zammit has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21362">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">agesa/f15tn/gcccar.inc: Remove altmacro dependence<br><br>This patch removes .altmacro dependence for the f15tn platform,<br>and also compiles with both clang and gcc<br><br>NEEDS TESTING<br><br>Change-Id: I3cf3f117f0f56e45f9008f787618800584de6c46<br>Signed-off-by: Damien Zammit <damien@zamaudio.com><br>---<br>M src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S<br>M src/vendorcode/amd/agesa/f15tn/gcccar.inc<br>2 files changed, 1,607 insertions(+), 1,598 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/21362/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S<br>index c1e7ab7..dd27b7b 100644<br>--- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S<br>+++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S<br>@@ -26,7 +26,7 @@<br> *<br> */<br> <br>-.include "src/vendorcode/amd/agesa/f15tn/gcccar.inc"<br>+#include "vendorcode/amd/agesa/f15tn/gcccar.inc"<br> <br> .code32<br> .align 4<br>@@ -62,14 +62,14 @@<br> wrmsr<br> /* Clear the CR0.CD bit */<br> movl %cr0, %eax /* Make sure cache is enabled for all APs */<br>- btr $CR0_CD, %eax<br>- btr $CR0_NW, %eax<br>+ btr $CR0_CD_BIT, %eax<br>+ btr $CR0_NW_BIT, %eax<br> mov %eax, %cr0 /* Write back to CR0 */<br> jmp 1f /* .else */<br> 0:<br> movl %cr0, %eax /* Make sure cache is disabled for all APs */<br>- bts $CR0_CD, %eax /* Disable cache */<br>- bts $CR0_NW, %eax<br>+ bts $CR0_CD_BIT, %eax /* Disable cache */<br>+ bts $CR0_NW_BIT, %eax<br> movl %eax, %cr0 /* Write back to CR0 */<br> 1: /* .endif */<br> <br>diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc<br>index 7ac9613..a2b01fa 100644<br>--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc<br>+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc<br>@@ -24,177 +24,187 @@<br> * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS<br> * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.<br> *<br>+ * Modified in 2017 to remove altmacro dependence - Damien Zammit <damien@zamaudio.com> <br> */<br> <br>-/******************************************************************************<br>-* AMD Generic Encapsulated Software Architecture<br>-*<br>-* $Workfile:: GccCar.inc $Revision:: 32932 $<br>-*<br>-* Description: GccCar.inc - AGESA cache-as-RAM setup Include File for GCC complier<br>-*<br>-******************************************************************************/<br>+/* Hack local labels to be hardcoded numeric labels */<br>+#define node_core_exit 1000<br>+#define fam10_enable_stack_hook_exit 1001<br>+#define fam10_disable_stack_hook_exit 1002<br>+#define node_core_f10_exit 1003<br>+#define node_core_f10_AP 1004<br>+#define fam12_enable_stack_hook_exit 1005<br>+#define fam12_disable_stack_hook_exit 1006<br>+#define node_core_f12_exit 1007<br>+#define fam14_enable_stack_hook_exit 1008<br>+#define fam14_disable_stack_hook_exit 1009<br>+#define node_core_f14_exit 1010<br>+#define fam15_enable_stack_hook_exit 1011<br>+#define fam15_disable_stack_hook_exit 1012<br>+#define fam15_disable_stack_remote_read_exit 1013<br>+#define node_core_f15_exit 1014<br>+#define node_core_f15_AP 1015<br>+#define node_core_f15_shared 1016<br>+#define node_core_f15_AP_not_TN 1017<br>+#define SetupStack 1018<br>+#define Real16bMode 1019<br>+#define Protected32Mode 1020<br>+#define ClearTheStack 1021<br> <br>-.altmacro<br>-<br>-BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */<br>-BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */<br>-CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */<br>-CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */<br>-CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */<br>+#define BSP_STACK_BASE_ADDR 0x30000 /* Base address for primary cores stack */<br>+#define BSP_STACK_SIZE 0x10000 /* 64KB for BSP core */<br>+#define CORE0_STACK_BASE_ADDR 0x80000 /* Base address for primary cores stack */<br>+#define CORE0_STACK_SIZE 0x4000 /* 16KB for primary cores */<br>+#define CORE1_STACK_BASE_ADDR 0x40000 /* Base address for AP cores */<br> <br> #ifdef __x86_64__<br>-CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */<br>+#define CORE1_STACK_SIZE 0x2000 /* 8KB for each AP cores */<br> #else<br>-CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */<br>+#define CORE1_STACK_SIZE 0x1000 /* 4KB for each AP cores */<br> #endif<br> <br>-APIC_BASE_ADDRESS = 0x0000001B<br>- APIC_BSC = 8 /* Boot Strap Core */<br>+#define APIC_BASE_ADDRESS 0x0000001B<br>+#define APIC_BSC 8 /* Boot Strap Core */<br> <br>-APIC_MSG_REG = 0x380 # Location of BSC message<br>- APIC_MSG = 0x00DE00AD # Message data<br>-APIC_CMD_LO_REG = 0x300 # APIC command low<br>-APIC_CMD_HI_REG = 0x310 # APIC command high<br>- CMD_REG_TO_READ_DATA = 0x00000338 # APIC command for remote read of APIC_MSG_REG<br>- REMOTE_READ_STS = 0x00030000 # Remote read status mask<br>- REMOTE_DELIVERY_PEND = 0x00010000 # Remote read is pending<br>- REMOTE_DELIVERY_DONE = 0x00020000 # Remote read is complete<br>- DELIVERY_STS_BIT = 12 #Delivery status valid bit<br>-APIC_ID_REG = 0x0020 # Local APIC ID offset<br>- APIC20_APICID = 24<br>-APIC_REMOTE_READ_REG = 0x00C0 # Remote read offset<br>+#define APIC_MSG_REG 0x380 // Location of BSC message<br>+#define APIC_MSG 0x00DE00AD // Message data<br>+#define APIC_CMD_LO_REG 0x300 // APIC command low<br>+#define APIC_CMD_HI_REG 0x310 // APIC command high<br>+#define CMD_REG_TO_READ_DATA 0x00000338 // APIC command for remote read of APIC_MSG_REG<br>+#define REMOTE_READ_STS 0x00030000 // Remote read status mask<br>+#define REMOTE_DELIVERY_PEND 0x00010000 // Remote read is pending<br>+#define REMOTE_DELIVERY_DONE 0x00020000 // Remote read is complete<br>+#define DELIVERY_STS_BIT 12 //Delivery status valid bit<br>+#define APIC_ID_REG 0x0020 // Local APIC ID offset<br>+#define APIC20_APICID 24<br>+#define APIC_REMOTE_READ_REG 0x00C0 // Remote read offset<br> <br>-# Flags can only run from bits 31 to 24. Bits 23:0 are in use.<br>-AMD_CU_NEED_TO_WAIT = 31<br>-AMD_CU_SEND_INVD_MSG = 30<br>-AMD_CU_RESTORE_ES = 29<br>+// Flags can only run from bits 31 to 24. Bits 23:0 are in use.<br>+#define AMD_CU_NEED_TO_WAIT 31<br>+#define AMD_CU_SEND_INVD_MSG 30<br>+#define AMD_CU_RESTORE_ES 29<br> <br>-AMD_MTRR_VARIABLE_BASE0 = 0x0200<br>-AMD_MTRR_VARIABLE_BASE6 = 0x020C<br>-AMD_MTRR_VARIABLE_BASE7 = 0x020E<br>- VMTRR_VALID = 11<br>- MTRR_TYPE_WB = 0x06<br>- MTRR_TYPE_WP = 0x05<br>- MTRR_TYPE_WT = 0x04<br>- MTRR_TYPE_UC = 0x00<br>-AMD_MTRR_VARIABLE_MASK7 = 0x020F<br>-AMD_MTRR_FIX64k_00000 = 0x0250<br>-AMD_MTRR_FIX16k_80000 = 0x0258<br>-AMD_MTRR_FIX16k_A0000 = 0x0259<br>-AMD_MTRR_FIX4k_C0000 = 0x0268<br>-AMD_MTRR_FIX4k_C8000 = 0x0269<br>-AMD_MTRR_FIX4k_D0000 = 0x026A<br>-AMD_MTRR_FIX4k_D8000 = 0x026B<br>-AMD_MTRR_FIX4k_E0000 = 0x026C<br>-AMD_MTRR_FIX4k_E8000 = 0x026D<br>-AMD_MTRR_FIX4k_F0000 = 0x026E<br>-AMD_MTRR_FIX4k_F8000 = 0x026F<br>+#define AMD_MTRR_VARIABLE_BASE0 0x0200<br>+#define AMD_MTRR_VARIABLE_BASE6 0x020C<br>+#define AMD_MTRR_VARIABLE_BASE7 0x020E<br>+#define VMTRR_VALID 11<br>+#define MTRR_TYPE_WB 0x06<br>+#define MTRR_TYPE_WP 0x05<br>+#define MTRR_TYPE_WT 0x04<br>+#define MTRR_TYPE_UC 0x00<br>+#define AMD_MTRR_VARIABLE_MASK7 0x020F<br>+#define AMD_MTRR_FIX64k_00000 0x0250<br>+#define AMD_MTRR_FIX16k_80000 0x0258<br>+#define AMD_MTRR_FIX16k_A0000 0x0259<br>+#define AMD_MTRR_FIX4k_C0000 0x0268<br>+#define AMD_MTRR_FIX4k_C8000 0x0269<br>+#define AMD_MTRR_FIX4k_D0000 0x026A<br>+#define AMD_MTRR_FIX4k_D8000 0x026B<br>+#define AMD_MTRR_FIX4k_E0000 0x026C<br>+#define AMD_MTRR_FIX4k_E8000 0x026D<br>+#define AMD_MTRR_FIX4k_F0000 0x026E<br>+#define AMD_MTRR_FIX4k_F8000 0x026F<br> <br> /* Reproduced from AGESA.h */<br>-AMD_AP_MTRR_FIX64k_00000 = 0x00000250<br>-AMD_AP_MTRR_FIX16k_80000 = 0x00000258<br>-AMD_AP_MTRR_FIX16k_A0000 = 0x00000259<br>-AMD_AP_MTRR_FIX4k_C0000 = 0x00000268<br>-AMD_AP_MTRR_FIX4k_C8000 = 0x00000269<br>-AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A<br>-AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B<br>-AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C<br>-AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D<br>-AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E<br>-AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F<br>-CPU_LIST_TERMINAL = 0xFFFFFFFF<br>+#define AMD_AP_MTRR_FIX64k_00000 0x00000250<br>+#define AMD_AP_MTRR_FIX16k_80000 0x00000258<br>+#define AMD_AP_MTRR_FIX16k_A0000 0x00000259<br>+#define AMD_AP_MTRR_FIX4k_C0000 0x00000268<br>+#define AMD_AP_MTRR_FIX4k_C8000 0x00000269<br>+#define AMD_AP_MTRR_FIX4k_D0000 0x0000026A<br>+#define AMD_AP_MTRR_FIX4k_D8000 0x0000026B<br>+#define AMD_AP_MTRR_FIX4k_E0000 0x0000026C<br>+#define AMD_AP_MTRR_FIX4k_E8000 0x0000026D<br>+#define AMD_AP_MTRR_FIX4k_F0000 0x0000026E<br>+#define AMD_AP_MTRR_FIX4k_F8000 0x0000026F<br>+#define CPU_LIST_TERMINAL 0xFFFFFFFF<br> <br>-AMD_MTRR_DEFTYPE = 0x02FF<br>- WB_DRAM_TYPE = 0x1E /* MemType - memory type */<br>- MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */<br>- MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */<br>+#define AMD_MTRR_DEFTYPE 0x02FF<br>+#define WB_DRAM_TYPE 0x1E /* MemType - memory type */<br>+#define MTRR_DEF_TYPE_EN 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */<br>+#define MTRR_DEF_TYPE_FIX_EN 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */<br> <br>-HWCR = 0x0C0010015 /* Hardware Configuration */<br>- INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */<br>+#define HWCR 0x0C0010015 /* Hardware Configuration */<br>+#define INVD_WBINVD 0x04 /* INVD to WBINVD conversion */<br>+#define IORR_BASE 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */<br>+#define TOP_MEM 0x0C001001A /* Top of Memory */<br>+#define TOP_MEM2 0x0C001001D /* Top of Memory2 */<br> <br>-IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */<br>- /* uses 16h - 19h */<br>-TOP_MEM = 0x0C001001A /* Top of Memory */<br>-TOP_MEM2 = 0x0C001001D /* Top of Memory2 */<br>+#define LS_CFG 0x0C0011020 /* Load-Store Configuration */<br>+#define DIS_SS 28 /* Family 10h,12h,15h:Disable Streng Store functionality */<br>+#define DIS_STREAM_ST 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */<br> <br>-LS_CFG = 0x0C0011020 /* Load-Store Configuration */<br>- DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */<br>- DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */<br>+#define IC_CFG 0x0C0011021 /* Instruction Cache Config Register */<br>+#define IC_DIS_SPEC_TLB_RLD 9 /* Disable speculative TLB reloads */<br>+#define DIS_IND 14 /* Family 10-14h:Disable Indirect Branch Predictor */<br>+#define DIS_I_CACHE 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */<br> <br>-IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */<br>- IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */<br>- DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */<br>- DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */<br>+#define DC_CFG 0x0C0011022 /* Data Cache Configuration */<br>+#define DC_DIS_SPEC_TLB_RLD 4 /* Disable speculative TLB reloads */<br>+#define DIS_CLR_WBTOL2_SMC_HIT 8 /* self modifying code check buffer bit */<br>+#define DIS_HW_PF 13 /* Hardware prefetches bit */<br> <br>-DC_CFG = 0x0C0011022 /* Data Cache Configuration */<br>- DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */<br>- DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */<br>- DIS_HW_PF = 13 /* Hardware prefetches bit */<br>+#define CU_CFG 0x0C0011023 /* Family 15h: Combined Unit Configuration */<br>+#define L2_WAY_LOCK_EN 23 /* L2WayLock - L2 way lock enable */<br>+#define L2_FIRST_LOCKED_WAY 19 /* L2FirstLockedWay - first L2 way lockedh */<br>+#define L2_FIRST_LOCKED_WAY_OR_MASK 0x000780000<br> <br>-CU_CFG = 0x0C0011023 /* Family 15h: Combined Unit Configuration */<br>- L2_WAY_LOCK_EN = 23 /* L2WayLock - L2 way lock enable */<br>- L2_FIRST_LOCKED_WAY = 19 /* L2FirstLockedWay - first L2 way lockedh */<br>- L2_FIRST_LOCKED_WAY_OR_MASK = 0x000780000<br>+#define DE_CFG 0x0C0011029 /* Decode Configuration */<br>+#define CL_FLUSH_SERIALIZE 23 /* Family 12h,15h: CL Flush Serialization */<br> <br>-DE_CFG = 0x0C0011029 /* Decode Configuration */<br>- CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */<br>+#define BU_CFG2 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */<br>+#define CU_CFG2 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */<br>+#define F10_CL_LINES_TO_NB_DIS 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */<br>+#define IC_DIS_SPEC_TLB_WR 35 /* IcDisSpecTlbWr - ITLB speculative writes */<br> <br>-BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */<br>-CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */<br>- F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */<br>- IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */<br>+#define CU_CFG3 0x0C001102B /* Combined Unit Configuration 3 */<br>+#define COMBINE_CR0_CD 49 /* Combine CR0.CD for both cores of a compute unit */<br> <br>-CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */<br>- COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */<br>-<br>-CR0_PE = 0 # Protection Enable<br>-CR0_NW = 29 # Not Write-through<br>-CR0_CD = 30 # Cache Disable<br>-CR0_PG = 31 # Paging Enable<br>+#define CR0_PE_BIT 0 // Protection Enable<br>+#define CR0_NW_BIT 29 // Not Write-through<br>+#define CR0_CD_BIT 30 // Cache Disable<br>+#define CR0_PG_BIT 31 // Paging Enable<br> <br> /* CPUID Functions */<br>+#define CPUID_MODEL 1<br>+#define AMD_CPUID_FMF 0x80000001 /* Family Model Features information */<br>+#define AMD_CPUID_L2Cache 0X80000006 /* L2/L3 cache info */<br>+#define AMD_CPUID_APIC 0x80000008 /* Long Mode and APIC info., core count */<br>+#define APIC_ID_CORE_ID_SIZE 12 /* ApicIdCoreIdSize bit position */<br> <br>-CPUID_MODEL = 1<br>-AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */<br>-AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */<br>-AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */<br>- APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */<br>+#define NB_CFG 0x0C001001F /* Northbridge Configuration Register */<br>+#define INIT_APIC_ID_CPU_ID_LO 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */<br>+#define ENABLE_CF8_EXT_CFG 46 /* EnableCf8ExtCfg - enable CF8 extended configuration cycles */<br> <br>-NB_CFG = 0x0C001001F /* Northbridge Configuration Register */<br>- INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */<br>- ENABLE_CF8_EXT_CFG = 46 /* EnableCf8ExtCfg - enable CF8 extended configuration cycles */<br>+#define MTRR_SYS_CFG 0x0C0010010 /* System Configuration Register */<br>+#define CHX_TO_DIRTY_DIS 16 /* ChxToDirtyDis Change to dirty disable */<br>+#define SYS_UC_LOCK_EN 17 /* SysUcLockEn System lock command enable */<br>+#define MTRR_FIX_DRAM_EN 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */<br>+#define MTRR_FIX_DRAM_MOD_EN 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */<br>+#define MTRR_VAR_DRAM_EN 20 /* MtrrVarDramEn MTRR variable DRAM enable */<br>+#define MTRR_TOM2_EN 21 /* MtrrTom2En MTRR top of memory 2 enable */<br> <br>-MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */<br>- CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */<br>- SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */<br>- MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */<br>- MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */<br>- MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */<br>- MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */<br>+#define PERF_CONTROL3 0x0C0010003 /* Performance event control three */<br>+#define PERF_CONTROL3_RESERVE_L 0x00200000 /* Preserve the reserved bits */<br>+#define PERF_CONTROL3_RESERVE_H 0x0FCF0 /* Preserve the reserved bits */<br>+#define CONFIG_EVENT_L 0x0F0E2 /* All cores with level detection */<br>+#define CONFIG_EVENT_H 4 /* Increment count by number of event occured in clock cycle */<br>+#define EVENT_ENABLE 22 /* Enable the event */<br>+#define PERF_COUNTER3 0x0C0010007 /* Performance event counter three */<br> <br>-PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */<br>- PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */<br>- PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */<br>- CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */<br>- CONFIG_EVENT_H = 4 /* Increment count by number of event */<br>- /* occured in clock cycle */<br>- EVENT_ENABLE = 22 /* Enable the event */<br>-PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */<br>+#define FUNC_3 3<br>+#define MCA_NB_CFG 0x44 /* MCA NB Configuration */<br>+#define CPU_ERR_DIS 6 /* CPU error response disable */<br>+#define PRODUCT_INFO_REG1 0x1FC /* Product Information Register 1 */<br> <br>-FUNC_3 = 3<br>-MCA_NB_CFG = 0x44 /* MCA NB Configuration */<br>-CPU_ERR_DIS = 6 /* CPU error response disable */<br>-PRODUCT_INFO_REG1 = 0x1FC /* Product Information Register 1 */<br>-<br>-# Local use flags, in upper most byte if ESI<br>-FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized<br>-FLAG_STACK_REENTRY = 25 # Signals that the environment has made a re-entry (2nd) call to set up the stack<br>-FLAG_IS_PRIMARY = 26 # Signals that this core is the primary within the comoute unit<br>-FLAG_CORE_NOT_IDENTIFIED = 27 # Signals that the cores/compute units of the installed processor is not recognized<br>-FLAG_FORCE_32K_STACK = 28 # Signals that to force 32KB stack size for BSP core<br>-CR0_MASK = ((1 << CR0_CD) | (1 << CR0_NW))<br>-MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))<br>+// Local use flags, in upper most byte if ESI<br>+#define FLAG_UNKNOWN_FAMILY 24 // Signals that the family// of the installed processor is not recognized<br>+#define FLAG_STACK_REENTRY 25 // Signals that the environment has made a re-entry (2nd) call to set up the stack<br>+#define FLAG_IS_PRIMARY 26 // Signals that this core is the primary within the comoute unit<br>+#define FLAG_CORE_NOT_IDENTIFIED 27 // Signals that the cores/compute units of the installed processor is not recognized<br>+#define FLAG_FORCE_32K_STACK 28 // Signals that to force 32KB stack size for BSP core<br>+#define CR0_MASK ((1 << CR0_CD_BIT) | (1 << CR0_NW_BIT))<br>+#define MSR_MASK ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))<br> <br> /****************************************************************************<br> *<br>@@ -224,8 +234,1247 @@<br> .endm<br> <br> .macro MAKE_EXT_PCI_ADDR Seg, Bus, Dev, Func, Offset<br>- mov $(1 << 31 | (Seg) << 28 | (((Offset) & (0x0F00)) >> 8) << 24 | (Bus) << 16 | (Dev) << 11 | (Func) << 8) | ((Offset) & (0xFC)), %eax<br>+ mov $((1 << 31 | (\Seg) << 28 | (((\Offset) & (0x0F00)) >> 8) << 24 | (\Bus) << 16 | (\Dev) << 11 | (\Func) << 8) | ((\Offset) & (0xFC))), %eax<br> .endm<br>+/****************************************************************************<br>+*<br>+* GET_NODE_ID_CORE_ID Macro - Stackless<br>+*<br>+* Read family specific values to determine the node and core<br>+* numbers for the core executing this code.<br>+*<br>+* Inputs:<br>+* none<br>+* Outputs:<br>+* SI[7:0] = Core# (0..N, relative to node)<br>+* SI[15:8]= Node# (0..N)<br>+* SI[23:16]= reserved<br>+* SI[24]= flag: 1=Family Unrecognized<br>+* SI[25]= flag: 1=Interface re-entry call<br>+* SI[26]= flag: 1=Core is primary of compute unit<br>+* SI[31:27]= reserved, =0<br>+****************************************************************************/<br>+.macro GET_NODE_ID_CORE_ID<br>+ //LOCAL node_core_exit<br>+<br>+ mov $-1, %si<br>+ GET_NODE_ID_CORE_ID_F10<br>+ GET_NODE_ID_CORE_ID_F12<br>+ GET_NODE_ID_CORE_ID_F14<br>+ GET_NODE_ID_CORE_ID_F15<br>+ /*<br>+ * Check for unrecognized Family<br>+ */<br>+ cmp $-1, %si // Has family (node/core) already been discovered?<br>+ jnz node_core_exit // Br if yes<br>+<br>+ mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi // No, Set error code, Only let BSP continue<br>+<br>+ mov $APIC_BASE_ADDRESS, %ecx // MSR:0000_001B<br>+ _RDMSR<br>+ bt $APIC_BSC, %eax // Is this the BSC?<br>+ jc node_core_exit // Br if yes<br>+ hlt // Kill APs<br>+node_core_exit:<br>+<br>+.endm<br>+<br>+/****************************************************************************<br>+* Family 10h MACROS<br>+*<br>+* AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless<br>+*<br>+* Set any family specific controls needed to enable the use of<br>+* cache as general storage before main memory is available.<br>+*<br>+* Inputs:<br>+* ESI - node//, core#, flags from GET_NODE_ID_CORE_ID<br>+* Outputs:<br>+* none<br>+*<br>+* Family 10h requirements (BKDG section 2.3.3):<br>+* * Paging disabled<br>+* * MSRC001_0015[INVDWBINVD]=0<br>+* * MSRC001_1021[DIS_IND]=1<br>+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1<br>+* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1<br>+* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1<br>+* * MSRC001_1022[DIS_HW_PF]=1<br>+* * MSRC001_102A[IcDisSpecTlbWr]=1<br>+* * MSRC001_102A[ClLinesToNbDis]=1<br>+* * No INVD or WBINVD, no exceptions, page faults or interrupts<br>+****************************************************************************/<br>+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10<br>+ //LOCAL fam10_enable_stack_hook_exit<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ shr $20, %eax // AL = cpu extended family<br>+ cmp $0x01, %al // Is this family 10h?<br>+ jnz fam10_enable_stack_hook_exit // Br if no<br>+<br>+ mov $DC_CFG, %ecx // MSR:C001_1022<br>+ _RDMSR<br>+ bts $DC_DIS_SPEC_TLB_RLD, %eax // Turn on Disable speculative DTLB reloads bit<br>+ bts $DIS_CLR_WBTOL2_SMC_HIT, %eax // Turn on Disable the self modifying code check buffer bit<br>+ bts $DIS_HW_PF, %eax // Turn on Disable hardware prefetches bit<br>+ _WRMSR<br>+<br>+ dec %cx // MSR:C001_1021<br>+ _RDMSR<br>+ bts $IC_DIS_SPEC_TLB_RLD, %eax // Turn on Disable speculative TLB reloads bit<br>+ bts $DIS_IND, %eax // Turn on Disable indirect branch predictor<br>+ _WRMSR<br>+<br>+ mov $BU_CFG2, %ecx // MSR C001_102A<br>+ _RDMSR<br>+ bts $F10_CL_LINES_TO_NB_DIS, %eax // Allow BIOS ROM to be cached in the IC<br>+ bts $(IC_DIS_SPEC_TLB_WR-32), %edx //Disable speculative writes to the ITLB<br>+ _WRMSR<br>+<br>+ mov $HWCR, %ecx // MSR C001_0015<br>+ _RDMSR<br>+ bt $FLAG_STACK_REENTRY, %esi // Check if stack has already been set<br>+ jc fam10_skipClearingBit4<br>+ btr $INVD_WBINVD, %eax // disable INVD -> WBINVD conversion<br>+ _WRMSR<br>+<br>+fam10_skipClearingBit4:<br>+ mov %esi, %eax // load core#<br>+ or %al, %al // If (BSP)<br>+ jne fam10_enable_stack_hook_exit<br>+ mov $PERF_COUNTER3, %ecx // Select performance counter three<br>+ // to count number of CAR evictions<br>+ xor %eax, %eax // Initialize the lower part of the counter to zero<br>+ xor %edx, %edx // Initializa the upper part of the counter to zero<br>+ _WRMSR // Save it<br>+ mov $PERF_CONTROL3, %ecx // Select the event control three<br>+ _RDMSR // Get the current setting<br>+ and $PERF_CONTROL3_RESERVE_L, %eax // Preserve the reserved bits<br>+ or $CONFIG_EVENT_L, %eax // Set the lower part of event register to<br>+ // select CAR Corruption occurred by any cores<br>+ and $PERF_CONTROL3_RESERVE_H, %dx // Preserve the reserved bits<br>+ or $CONFIG_EVENT_H, %dx // Set the upper part of event register<br>+ _WRMSR // Save it<br>+ bts $EVENT_ENABLE, %eax // Enable it<br>+ _WRMSR // Save it<br>+<br>+fam10_enable_stack_hook_exit:<br>+.endm<br>+<br>+/****************************************************************************<br>+*<br>+* AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless<br>+*<br>+* Return any family specific controls to their 'standard'<br>+* settings for using cache with main memory.<br>+*<br>+* Inputs:<br>+* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#<br>+* Outputs:<br>+* none<br>+*<br>+* Family 10h requirements:<br>+* * INVD or WBINVD<br>+* * MSRC001_0015[INVD_WBINVD]=1<br>+* * MSRC001_1021[DIS_IND]=0<br>+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0<br>+* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0<br>+* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0<br>+* * MSRC001_1022[DIS_HW_PF]=0<br>+* * MSRC001_102A[IcDisSpecTlbWr]=0<br>+* * MSRC001_102A[ClLinesToNbDis]=0<br>+*****************************************************************************/<br>+<br>+.macro AMD_DISABLE_STACK_FAMILY_HOOK_F10<br>+ //LOCAL fam10_disable_stack_hook_exit<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ shr $20, %eax // AL = cpu extended family<br>+ cmp $0x01, %al // Is this family 10h?<br>+ jnz fam10_disable_stack_hook_exit // Br if no<br>+<br>+ mov $DC_CFG, %ecx // MSR:C001_1022<br>+ _RDMSR<br>+ btr $DC_DIS_SPEC_TLB_RLD, %eax // Enable speculative TLB reloads<br>+ btr $DIS_CLR_WBTOL2_SMC_HIT, %eax // Allow self modifying code check buffer<br>+ btr $DIS_HW_PF, %eax // Allow hardware prefetches<br>+ _WRMSR<br>+<br>+ dec %cx // MSR:C001_1021<br>+ _RDMSR<br>+ btr $DIS_IND, %eax // Turn on indirect branch predictor<br>+ btr $IC_DIS_SPEC_TLB_RLD, %eax // Turn on speculative TLB reloads<br>+ _WRMSR<br>+<br>+ mov $BU_CFG2, %ecx // MSR:C001_102A<br>+ _RDMSR<br>+ btr $F10_CL_LINES_TO_NB_DIS, %eax // Return L3 to normal mode<br>+ btr $(IC_DIS_SPEC_TLB_WR-32), %edx //Re-enable speculative writes to the ITLB<br>+ _WRMSR<br>+<br>+ //--------------------------------------------------------------------------<br>+ // Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>+ //--------------------------------------------------------------------------<br>+<br>+ mov $HWCR, %ecx // MSR:0000_0015<br>+ _RDMSR<br>+ mov %ax, %bx // Save INVD -> WBINVD bit<br>+ btr $INVD_WBINVD, %eax // Disable INVD -> WBINVD conversion for the invd instruction.<br>+ _WRMSR<br>+ invd // Clear the cache tag RAMs<br>+ mov %bx, %ax // Restore INVD -> WBINVD bit<br>+ _WRMSR<br>+<br>+ //--------------------------------------------------------------------------<br>+ // End critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>+ //--------------------------------------------------------------------------<br>+<br>+ mov $PERF_CONTROL3, %ecx // Select the event control three<br>+ _RDMSR // Retrieve the current value<br>+ btc $EVENT_ENABLE, %eax // Is event enable, complement it as well<br>+ jnc fam10_disable_stack_hook_exit // No<br>+ cmp $CONFIG_EVENT_L, %ax // Is the lower part of event set to capture the CAR Corruption<br>+ jne fam10_disable_stack_hook_exit // No<br>+ cmp $CONFIG_EVENT_H, %dl // Is the upper part of event set to capture the CAR Corruption<br>+ jne fam10_disable_stack_hook_exit // No<br>+ _WRMSR // Disable the event<br>+<br>+fam10_disable_stack_hook_exit:<br>+<br>+.endm<br>+<br>+/****************************************************************************<br>+*<br>+* GET_NODE_ID_CORE_ID_F10 Macro - Stackless<br>+*<br>+* Read family specific values to determine the node and core<br>+* numbers for the core executing this code.<br>+*<br>+* Inputs:<br>+* none<br>+* Outputs:<br>+* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)<br>+*****************************************************************************/<br>+.macro GET_NODE_ID_CORE_ID_F10<br>+<br>+ //LOCAL node_core_f10_exit<br>+ //LOCAL node_core_f10_AP<br>+<br>+ cmp $-1, %si // Has node/core already been discovered?<br>+ jnz node_core_f10_exit // Br if yes<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ shr $20, %eax // AL = cpu extended family<br>+ cmp $0x01, %al // Is this family 10h?<br>+ jnz node_core_f10_exit // Br if no<br>+<br>+ xor %esi, %esi // Assume BSC, clear flags<br>+ mov $APIC_BASE_ADDRESS, %ecx // MSR:0000_001B<br>+ _RDMSR<br>+ bt $APIC_BSC, %eax // Is this the BSC?<br>+ jnc node_core_f10_AP // Br if no<br>+<br>+ // This is the BSP.<br>+ // Enable routing tables on BSP (just in case the HT init code has not yet enabled them)<br>+ mov $0x8000C06C, %eax // PCI address for D18F0x6C Link Initialization Control Register<br>+ mov $0x0CF8, %dx<br>+ out %eax, %dx<br>+ add $4, %dx<br>+ in %dx, %eax<br>+ btr $0, %eax // Set LinkInitializationControl[RouteTblDis] = 0<br>+ out %eax, %dx<br>+ jmp 1f //<br>+<br>+node_core_f10_AP:<br>+ //<br>+ // This is an AP. Routing tables have been enabled by the HT Init process.<br>+ // Also, the MailBox register was set by the BSP during early init<br>+ // The Mailbox register content is formatted as follows:<br>+ // UINT32 Node:4# // The node id of Core's node.<br>+ // UINT32 Socket:4# // The socket of this Core's node.<br>+ // UINT32 Module:2# // The internal module number for Core's node.<br>+ // UINT32 ModuleType:2# // Single Module = 0, Multi-module = 1.<br>+ // UINT32 :20# // Reserved<br>+ //<br>+ mov $0x0C0000408, %ecx // Read the family 10h mailbox<br>+ _RDMSR // MC4_MISC1[63:32]<br>+ mov %dx, %si // SI = raw mailbox contents (will extract node# from this)<br>+ shr $24, %ebx // BL = CPUID Fn0000_0001_EBX[LocalApicId]<br>+ mov %bx, %di // DI = Initial APIC ID (will extract core// from this)<br>+<br>+ AMD_CPUID $AMD_CPUID_APIC //<br>+ shr $4, %ch // CH = ApicIdSize, #bits in APIC ID that show core#<br>+ inc %cl // CL = Number of enabled cores in the socket<br>+ mov %cx, %bx<br>+<br>+ mov $NB_CFG, %ecx // MSR:C001_001F<br>+ _RDMSR // EDX has InitApicIdCpuIdLo bit<br>+<br>+ mov %bh, %cl // CL = APIC ID size<br>+ mov $1, %al // Convert APIC ID size to an AND mask<br>+ shl %cl, %al // AL = 2^APIC ID size<br>+ dec %al // AL = mask for relative core number<br>+ xor %ah, %ah // AX = mask for relative core number<br>+ bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx // InitApicIdCpuIdLo == 1?<br>+ //.if (!carry?) // Br if yes<br>+ jc 0f<br>+ mov $8, %ch // Calculate core number shift count<br>+ sub %cl, %ch // CH = core shift count<br>+ mov %ch, %cl<br>+ shr %cl, %di // Right justify core number<br>+ //.endif<br>+ 0:<br>+ and %ax, %di // DI = socket-relative core number<br>+<br>+ mov %si, %cx // CX = raw mailbox value<br>+ shr $10, %cx // CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)<br>+ and $3, %cl // Isolate ModuleType<br>+ xor %bh, %bh // BX = Number of enabled cores in the socket<br>+ shr %cl, %bx // BX = Number of enabled cores per node<br>+ xor %dx, %dx // Clear upper word for div<br>+ mov %di, %ax // AX = socket-relative core number<br>+ div %bx // DX = node-relative core number<br>+ movzx %si, %eax // prepare return value, [23:16]=shared Core# (=0, not shared)<br>+ and $0x000F, %ax // AX = node number<br>+ shl $8, %ax // [15:8]=node#<br>+ mov %dl, %al // [7:0]=core# (relative to node)<br>+ mov %eax, %esi // ESI = return value<br>+1:<br>+ bts $FLAG_IS_PRIMARY, %esi // all Family 10h cores are primary<br>+node_core_f10_exit:<br>+.endm<br>+<br>+/*****************************************************************************<br>+** Family 12h MACROS<br>+*****************************************************************************/<br>+/*****************************************************************************<br>+*<br>+* AMD_ENABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless<br>+*<br>+* Set any family specific controls needed to enable the use of<br>+* cache as general storage before main memory is available.<br>+*<br>+* Inputs:<br>+* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID<br>+* Outputs:<br>+* none<br>+*<br>+* Family 12h requirements (BKDG section 2.3.3):<br>+* The following requirements must be satisfied prior to using the cache as general storage:<br>+* * Paging must be disabled.<br>+* * MSRC001_0015[INVD_WBINVD]=0<br>+* * MSRC001_1020[DIS_SS]=1<br>+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1<br>+* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1<br>+* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1<br>+* * MSRC001_1022[DIS_HW_PF]=1<br>+* * MSRC001_1029[ClflushSerialize]=1<br>+* * No INVD or WBINVD, no exceptions, page faults or interrupts<br>+*****************************************************************************/<br>+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F12<br>+ //LOCAL fam12_enable_stack_hook_exit<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ shr $20, %eax // AL = cpu extended family<br>+ cmp $0x03, %al // Is this family 12h?<br>+ jnz fam12_enable_stack_hook_exit // Br if no<br>+<br>+ mov $DC_CFG, %ecx // MSR:C001_1022<br>+ _RDMSR<br>+ bts $DC_DIS_SPEC_TLB_RLD, %eax // Disable speculative DC-TLB reloads<br>+ bts $DIS_CLR_WBTOL2_SMC_HIT, %eax // Disable self modifying code check buffer<br>+ bts $DIS_HW_PF, %eax // Disable hardware prefetches<br>+ _WRMSR<br>+<br>+ dec %cx //IC_CFG // MSR:C001_1021<br>+ _RDMSR<br>+ bts $IC_DIS_SPEC_TLB_RLD, %eax // Disable speculative IC-TLB reloads<br>+ _WRMSR<br>+<br>+ dec %cx //LS_CFG // MSR:C001_1020<br>+ _RDMSR<br>+ bts $DIS_SS, %eax // Disabled Streaming store functionality<br>+ _WRMSR<br>+<br>+ mov $HWCR, %ecx // MSR C001_0015<br>+ _RDMSR<br>+ bt $FLAG_STACK_REENTRY , %esi // Check if stack has already been set<br>+ jc fam12_skipClearingBit4<br>+ btr $INVD_WBINVD, %eax // disable INVD -> WBINVD conversion<br>+ _WRMSR<br>+<br>+fam12_skipClearingBit4:<br>+ mov $DE_CFG, %ecx // MSR:C001_1029<br>+ _RDMSR<br>+ bts $CL_FLUSH_SERIALIZE, %eax // Serialize all CL Flush actions<br>+ _WRMSR<br>+<br>+fam12_enable_stack_hook_exit:<br>+.endm<br>+<br>+/*****************************************************************************<br>+*<br>+* AMD_DISABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless<br>+*<br>+* Return any family specific controls to their 'standard'<br>+* settings for using cache with main memory.<br>+*<br>+* Inputs:<br>+* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#<br>+* Outputs:<br>+* none<br>+*<br>+* Family 12h requirements:<br>+* * INVD or WBINVD<br>+* * MSRC001_0015[INVD_WBINVD]=1<br>+* * MSRC001_1020[DIS_SS]=0<br>+* * MSRC001_1021[IC_DIS_SPEC_TLB_RLD]=0<br>+* * MSRC001_1022[DC_DIS_SPEC_TLB_RLD]=0<br>+* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0<br>+* * MSRC001_1022[DIS_HW_PF]=0<br>+* * MSRC001_1029[ClflushSerialize]=0<br>+*****************************************************************************/<br>+.macro AMD_DISABLE_STACK_FAMILY_HOOK_F12<br>+ //LOCAL fam12_disable_stack_hook_exit<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ shr $20, %eax // AL = cpu extended family<br>+ cmp $0x03, %al // Is this family 12h?<br>+ jnz fam12_disable_stack_hook_exit // Br if no<br>+<br>+ mov $DC_CFG, %ecx // MSR:C001_1022<br>+ _RDMSR<br>+ btr $DC_DIS_SPEC_TLB_RLD, %eax // Turn on speculative DC-TLB reloads<br>+ btr $DIS_CLR_WBTOL2_SMC_HIT, %eax // Enable self modifying code check buffer<br>+ btr $DIS_HW_PF, %eax // Enable Hardware prefetches<br>+ _WRMSR<br>+<br>+ dec %cx //IC_CFG // MSR:C001_1021<br>+ _RDMSR<br>+ btr $IC_DIS_SPEC_TLB_RLD, %eax // Turn on speculative IC-TLB reloads<br>+ _WRMSR<br>+<br>+ dec %cx //LS_CFG // MSR:C001_1020<br>+ _RDMSR<br>+ btr $DIS_SS, %eax // Turn on Streaming store functionality<br>+ _WRMSR<br>+<br>+ mov $DE_CFG, %ecx // MSR:C001_1029<br>+ _RDMSR<br>+ btr $CL_FLUSH_SERIALIZE, %eax<br>+ _WRMSR<br>+<br>+ //--------------------------------------------------------------------------<br>+ // Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>+ //--------------------------------------------------------------------------<br>+<br>+ mov $HWCR, %ecx // MSR:0000_0015h<br>+ _RDMSR<br>+ mov %ax, %bx // Save INVD -> WBINVD bit<br>+ btr $INVD_WBINVD, %eax // Disable INVD -> WBINVD conversion<br>+ _WRMSR<br>+ invd // Clear the cache tag RAMs<br>+ mov %bx, %ax // Restore INVD -> WBINVD bit<br>+ _WRMSR<br>+<br>+ //--------------------------------------------------------------------------<br>+ // End critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>+ //--------------------------------------------------------------------------<br>+<br>+fam12_disable_stack_hook_exit:<br>+.endm<br>+<br>+/*****************************************************************************<br>+*<br>+* GET_NODE_ID_CORE_ID_F12 Macro - Stackless<br>+*<br>+* Read family specific values to determine the node and core<br>+* numbers for the core executing this code.<br>+*<br>+* Inputs:<br>+* none<br>+* Outputs:<br>+* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)<br>+*****************************************************************************/<br>+.macro GET_NODE_ID_CORE_ID_F12<br>+<br>+ //LOCAL node_core_f12_exit<br>+<br>+ cmp $-1, %si // Has node/core already been discovered?<br>+ jnz node_core_f12_exit // Br if yes<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ shr $20, %eax // AL = cpu extended family<br>+ cmp $0x03, %al // Is this family 12h?<br>+ jnz node_core_f12_exit // Br if no<br>+<br>+ shr $24, %ebx // CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID<br>+ bts $FLAG_IS_PRIMARY, %ebx // all family 12h cores are primary<br>+ mov %ebx, %esi // ESI = Node#=0, core number<br>+node_core_f12_exit:<br>+.endm<br>+<br>+/*****************************************************************************<br>+** Family 14h MACROS<br>+*****************************************************************************/<br>+/*****************************************************************************<br>+*<br>+* AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless<br>+*<br>+* Set any family specific controls needed to enable the use of<br>+* cache as general storage before main memory is available.<br>+*<br>+* Inputs:<br>+* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID<br>+* Outputs:<br>+* none<br>+*<br>+* Family 14h requirements (BKDG section 2.3.3):<br>+* * Paging must be disabled.<br>+* * MSRC001_0015[INVD_WBINVD]=0.<br>+* * MSRC001_1020[DisStreamSt]=1.<br>+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.<br>+* * MSRC001_1022[DIS_HW_PF]=1.<br>+* * No INVD or WBINVD, no exceptions, page faults or interrupts<br>+*****************************************************************************/<br>+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F14<br>+ //LOCAL fam14_enable_stack_hook_exit<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ shr $20, %eax // AL = cpu extended family<br>+ cmp $0x05, %al // Is this family 14h?<br>+ jnz fam14_enable_stack_hook_exit // Br if no<br>+<br>+ mov $DC_CFG, %ecx // MSR:C001_1022<br>+ _RDMSR<br>+ bts $DIS_HW_PF, %eax // Disable hardware prefetches<br>+ _WRMSR<br>+<br>+ dec %cx //IC_CFG // MSR:C001_1021<br>+ _RDMSR<br>+ bts $IC_DIS_SPEC_TLB_RLD, %eax // Disable speculative TLB reloads<br>+ _WRMSR<br>+<br>+ dec %cx //LS_CFG // MSR:C001_1020<br>+ _RDMSR<br>+ bts $DIS_STREAM_ST, %eax // Disabled Streaming store functionality<br>+ _WRMSR<br>+<br>+ mov $HWCR, %ecx // MSR C001_0015<br>+ _RDMSR<br>+ bt $FLAG_STACK_REENTRY, %esi // Check if stack has already been set<br>+ jc fam14_skipClearingBit4<br>+ btr $INVD_WBINVD, %eax // Disable INVD -> WBINVD conversion<br>+ _WRMSR<br>+fam14_skipClearingBit4: // Keeping this label<br>+<br>+fam14_enable_stack_hook_exit:<br>+.endm<br>+<br>+/*****************************************************************************<br>+*<br>+* AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless<br>+*<br>+* Return any family specific controls to their 'standard'<br>+* settings for using cache with main memory.<br>+*<br>+* Inputs:<br>+* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#<br>+* Outputs:<br>+* none<br>+*<br>+* Family 14h requirements:<br>+* * INVD or WBINVD<br>+* * MSRC001_0015[INVD_WBINVD]=1.<br>+* * MSRC001_1020[DisStreamSt]=0.<br>+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0.<br>+* * MSRC001_1022[DIS_HW_PF]=0.<br>+*****************************************************************************/<br>+.macro AMD_DISABLE_STACK_FAMILY_HOOK_F14<br>+ //LOCAL fam14_disable_stack_hook_exit<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ shr $20, %eax // AL = cpu extended family<br>+ cmp $0x05, %al // Is this family 14h?<br>+ jnz fam14_disable_stack_hook_exit // Br if no<br>+<br>+ mov $LS_CFG, %ecx // MSR:C001_1020<br>+ _RDMSR<br>+ btr $DIS_STREAM_ST, %eax // Turn on Streaming store functionality<br>+ _WRMSR<br>+<br>+ inc %cx //IC_CFG // MSR:C001_1021<br>+ _RDMSR<br>+ btr $IC_DIS_SPEC_TLB_RLD, %eax // Turn on speculative DC-TLB reloads<br>+ _WRMSR<br>+<br>+ inc %cx //DC_CFG // MSR:C001_1022<br>+ _RDMSR<br>+ btr $DIS_HW_PF, %eax // Turn on hardware prefetches<br>+ _WRMSR<br>+<br>+ //--------------------------------------------------------------------------<br>+ // Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>+ //--------------------------------------------------------------------------<br>+<br>+ mov $HWCR, %ecx // MSR:C001_0015h<br>+ _RDMSR<br>+ btr $INVD_WBINVD, %eax // Disable INVD -> WBINVD conversion<br>+ _WRMSR<br>+ invd // Clear the cache tag RAMs<br>+ bts $INVD_WBINVD, %eax // Turn on Conversion of INVD to WBINVD<br>+ _WRMSR<br>+<br>+ //--------------------------------------------------------------------------<br>+ // End critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>+ //--------------------------------------------------------------------------<br>+<br>+fam14_disable_stack_hook_exit:<br>+.endm<br>+<br>+/*****************************************************************************<br>+*<br>+* GET_NODE_ID_CORE_ID_F14 Macro - Stackless<br>+*<br>+* Read family specific values to determine the node and core<br>+* numbers for the core executing this code.<br>+*<br>+* Inputs:<br>+* none<br>+* Outputs:<br>+* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)<br>+*****************************************************************************/<br>+.macro GET_NODE_ID_CORE_ID_F14<br>+<br>+ //LOCAL node_core_f14_exit<br>+<br>+ cmp $-1, %si // Has node/core already been discovered?<br>+ jnz node_core_f14_exit // Br if yes<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ shr $20, %eax // AL = cpu extended family<br>+ cmp $0x05, %al // Is this family 14h?<br>+ jnz node_core_f14_exit // Br if no<br>+<br>+ xor %esi, %esi // Node must be 0<br>+ bts $FLAG_IS_PRIMARY, %esi // all family 14h cores are primary<br>+ mov $APIC_BASE_ADDRESS, %ecx // MSR:0000_001B<br>+ _RDMSR<br>+ bt $APIC_BSC, %eax // Is this the BSC?<br>+ jc node_core_f14_exit // Br if yes<br>+ inc %si // Set core to 1<br>+node_core_f14_exit:<br>+.endm<br>+<br>+/*****************************************************************************<br>+** Family 15h MACROS<br>+*****************************************************************************/<br>+/*****************************************************************************<br>+*<br>+* AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless<br>+*<br>+* Set any family specific controls needed to enable the use of<br>+* cache as general storage before main memory is available.<br>+*<br>+* Inputs:<br>+* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID<br>+* Outputs:<br>+* none<br>+*<br>+* Family 15h requirements (BKDG #42301 section 2.3.3):<br>+* * Paging must be disabled.<br>+* * MSRC001_0015[INVD_WBINVD]=0<br>+* * MSRC001_1020[DisSS]=1<br>+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1<br>+* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1<br>+* * MSRC001_1022[DisHwPf]=1<br>+* * No INVD or WBINVD, no exceptions, page faults or interrupts<br>+*****************************************************************************/<br>+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F15<br>+ //LOCAL fam15_enable_stack_hook_exit<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ mov %eax, %ebx // Save revision info to EBX<br>+ shr $20, %eax // AL = cpu extended family<br>+ cmp $0x06, %al // Is this family 15h?<br>+ jnz fam15_enable_stack_hook_exit // Br if no<br>+<br>+ bt $FLAG_STACK_REENTRY , %esi // Check if stack has already been set<br>+ jc fam15_skipClearingBit4<br>+ mov $HWCR, %ecx // MSR C001_0015<br>+ _RDMSR<br>+ btr $INVD_WBINVD, %eax // disable INVD -> WBINVD conversion<br>+ _WRMSR<br>+<br>+fam15_skipClearingBit4:<br>+ mov $LS_CFG, %ecx // MSR:C001_1020<br>+ _RDMSR<br>+ bts $DIS_SS, %eax // Turn on Streaming store functionality disabled bit<br>+ _WRMSR<br>+<br>+ inc %ecx //IC_CFG // MSR:C001_1021<br>+ _RDMSR<br>+ bts $IC_DIS_SPEC_TLB_RLD, %eax // Turn on Disable speculative IC-TLB reloads bit<br>+ _WRMSR<br>+<br>+ mov %ebx, %eax // Restore revision info to EAX<br>+ shr $16, %eax<br>+ and $0x0F, %al // AL = cpu extended model<br>+<br>+ inc %ecx //DC_CFG // MSR:C001_1022<br>+ _RDMSR<br>+ bts $DC_DIS_SPEC_TLB_RLD, %eax // Turn on Disable speculative DC-TLB reloads bit<br>+ bts $DIS_HW_PF, %eax // Turn on Disable hardware prefetches bit<br>+ _WRMSR // Remove KM in PI 1.1.0.0<br>+<br>+ mov %ebx, %eax // Restore revision info to EAX<br>+ shr $16, %eax<br>+ and $0xF, %al<br>+ //.if (al == 01h) || (al == 03h) Is this TN or KV?<br>+ cmp $1, %eax<br>+ jz 1f<br>+ cmp $3, %eax<br>+ jz 3f // Skip if it is KV, it is only for TN from Label 1 to 3<br>+ jmp 2f<br>+1: //.if (al == 01h) // TN only<br>+ //Enable MSRC001_001F[EnableCf8ExtCfg]<br>+ mov $NB_CFG, %ecx // MSR:C001_001F<br>+ _RDMSR<br>+ bts $(ENABLE_CF8_EXT_CFG - 32), %edx<br>+ _WRMSR<br>+ // Set F3x44[6, CpuErrDis] = 1<br>+ MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, 0x44 //MCA_NB_CFG<br>+ //mov $(1 << 31 | 2 << 28 | (((MCA_NB_CFG) & (0x0F00)) >> 8) << 24 | 2 << 16 | 1 << 11 | FUNC_3 << 8), %eax<br>+<br>+ mov $0xCF8, %dx<br>+ out %eax, %dx<br>+ add $4, %dx<br>+ in %dx, %eax<br>+ bts $CPU_ERR_DIS, %eax<br>+ out %eax, %dx<br>+<br>+3: mov $CU_CFG, %ecx // TN or KV<br>+ _RDMSR<br>+ bt $L2_WAY_LOCK_EN, %eax<br>+ //.if (!carry?)<br>+ jc 2f<br>+ bts $L2_WAY_LOCK_EN, %eax<br>+ or $L2_FIRST_LOCKED_WAY_OR_MASK, %eax<br>+ _WRMSR<br>+ //.endif<br>+ //.endif<br>+2:<br>+ mov %ebx, %eax // Restore revision info to EAX<br>+ xchg %ah, %al<br>+ shr $8, %eax<br>+ and $0xF, %al<br>+ //.if (ax == 6100h) ; Is this TN-A0?<br>+ cmp $0x6100, %ax<br>+ jnz 2f<br>+ MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, PRODUCT_INFO_REG1<br>+ mov $0xCF8, %dx<br>+ out %eax, %dx<br>+ add $4, %dx<br>+ in %dx, %eax<br>+ bt $21, %eax<br>+ jc 2f<br>+ mov $CU_CFG2, %ecx //MSR:C001_102A<br>+ _RDMSR<br>+ bts $8, %eax<br>+ _WRMSR<br>+ // .endif<br>+<br>+2: // Do Standard Family 15 work<br>+<br>+ mov $CU_CFG3, %ecx // MSR:C001_102B<br>+ _RDMSR<br>+ btr $(COMBINE_CR0_CD - 32), %edx // Clear CombineCr0Cd bit<br>+ _WRMSR<br>+<br>+fam15_enable_stack_hook_exit:<br>+.endm<br>+<br>+/*****************************************************************************<br>+*<br>+* AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless<br>+*<br>+* Return any family specific controls to their 'standard'<br>+* settings for using cache with main memory.<br>+*<br>+* Note: Customized for coreboot:<br>+* A wbinvd is used to send cache to memory. The existing stack is preserved<br>+* at its original location and additional information is preserved (e.g.<br>+* coreboot CAR globals, heap structures, etc.). This implementation should<br>+* NOT be used with S3 resume IF the stack/cache area is not reserved and<br>+* over system memory.<br>+*<br>+* Inputs:<br>+* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#<br>+* Outputs:<br>+* none<br>+*<br>+* Family 15h requirements:<br>+* * INVD or WBINVD<br>+* * MSRC001_0015[INVD_WBINVD]=1<br>+* * MSRC001_1020[DisSS]=0<br>+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0<br>+* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0<br>+* * MSRC001_1022[DIS_HW_PF]=0<br>+*****************************************************************************/<br>+.macro AMD_DISABLE_STACK_FAMILY_HOOK_F15<br>+ //LOCAL fam15_disable_stack_hook_exit<br>+ //LOCAL fam15_disable_stack_remote_read_exit<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ mov %eax, %ebx // Save revision info to EBX<br>+ shr $20, %eax // AL = cpu extended family<br>+ cmp $0x06, %al // Is this family 15h?<br>+ jnz fam15_disable_stack_hook_exit // Br if no<br>+<br>+ mov %ebx, %edi // Save revision info to EDI<br>+ AMD_CPUID $AMD_CPUID_APIC<br>+ mov %cl, %al // AL = number of cores - 1<br>+ shr $APIC_ID_CORE_ID_SIZE, %cx // CL = ApicIdCoreIdSize<br>+ mov $1, %bx<br>+ shl %cl, %bl // BL = theoretical number of cores on socket<br>+ dec %bx // BL = core number on socket mask<br>+ mov %bl, %ah // AH = core number on socket mask<br>+ mov %edi, %ebx // Restore revision info to EBX<br>+ mov %ax, %di // DI[15:8] = core number mask, DI[7:0] = number of cores - 1<br>+<br>+ and $0x0F00FF, %ebx<br>+ mov %ebx, %eax<br>+ shr $8, %eax<br>+ or %ax, %bx // Save Extended Model, Model and Stepping to BX<br>+ // [11:8] = Extended Model, [7:4] = Model, [3:0] = Stepping (bx=0000000000010100, ok)<br>+<br>+ mov $APIC_BASE_ADDRESS, %ecx<br>+ _RDMSR // dx=0 ax=fee00800<br>+ mov %bx, %dx // Save Extended Model, Model and Stepping to DX<br>+ shl $16, %edx //EDX[31:16] = Extended Model, Model and Stepping<br>+ mov %eax ,%ebx // EBX = LAPIC base<br>+ xor %ecx ,%ecx // Zero out CU flags<br>+ bts $AMD_CU_NEED_TO_WAIT, %ecx // Default to waiting<br>+ bts $AMD_CU_SEND_INVD_MSG, %ecx // Default to signaling<br>+ mov %cr0, %eax<br>+ bt $CR0_PE_BIT, %ax // Are we in protected mode?<br>+ // .if (!carry?)<br>+ jc 1f<br>+ bts $AMD_CU_RESTORE_ES, %ecx // Indicate ES restore is required<br>+ mov %es, %cx // Save ES segment register to CX<br>+ xor %ax, %ax<br>+ mov %ax, %es // Set ES to big real mode selector for 4GB access<br>+ // .endif<br>+<br>+1:<br>+ and $0x0F000, %bx // EBX = LAPIC base, offset 0<br>+ or $APIC_ID_REG, %bl //<br>+ mov %es:(%ebx), %eax // EAX[31:24] = APIC ID<br>+ shr $APIC20_APICID, %eax // AL = APIC ID<br>+ mov %al, %ah // AH = APIC ID<br>+ mov %di, %dx // DH = core mask<br>+ and %dh, %ah // AH = core number // ax=111 dx=01000F03<br>+<br>+ // .if (zero?)<br>+ jnz 1f<br>+ // Core 0 of a socket<br>+ btr $AMD_CU_SEND_INVD_MSG, %ecx // No need to signal after INVD<br>+ //.if (dl != 0)<br>+ cmp $0, %dl<br>+ jz 2f<br>+ // This socket has multiple cores<br>+ and $0xf000, %bx // EBX = LAPIC base, offset 0<br>+ or $APIC_MSG_REG, %bx<br>+ mov $APIC_MSG, %edi<br>+ mov %edi, %es:(%ebx) // Signal for non core 0s to complete CAR breakdown<br>+ jmp 1f<br>+ //.else<br>+2: btr $AMD_CU_NEED_TO_WAIT, %ecx // No need to wait on a single core CPU<br>+ //.endif<br>+ // .endif<br>+1:<br>+<br>+ bt $AMD_CU_NEED_TO_WAIT, %ecx //cx = c0000000<br>+ //.if (carry?)<br>+ jnc 1f<br>+ //.if (ah == dl)<br>+ cmp %dl, %ah<br>+ jnz 2f<br>+ // This is the highest numbered core on this socket -- wait on core 0<br>+ not %dh // Flip the mask to determine local core 0's APID ID<br>+ and %dh, %al // AL = target APIC ID # ax=310<br>+ jmp 3f<br>+2: //.else<br>+ // All other cores (including core 0) wait on the next highest core.<br>+ // In this way, cores will halt in a cascading fashion down to 0.<br>+ inc %al<br>+ //.endif<br>+3:<br>+ shl $APIC20_APICID, %eax<br>+ and $0x0F000, %bx<br>+ or $APIC_CMD_HI_REG, %bx<br>+ mov %eax, %es:(%ebx) // Set target APIC ID<br>+<br>+ // Use bits 23:16 as a timeout for unresponsive cores<br>+ ror $8, %ecx<br>+ mov $0xFF, %ch<br>+ stc<br>+<br>+ //.while (carry?)<br>+5: jnc 4f<br>+ and $0xF000, %bx //EBX = LAPIC base, offset 0<br>+ or $APIC_CMD_LO_REG, %bx // bx = 00000000FEE00300<br>+ mov $CMD_REG_TO_READ_DATA, %eax<br>+ mov %eax, %es:(%ebx) //Fire remove read IPI<br>+ inc %ch //Pre increment the timeout<br>+ stc<br>+ //.while (carry?)<br>+7: jnc 6f<br>+ dec %ch //Check the timeout<br>+ jz fam15_disable_stack_remote_read_exit<br>+ mov %es:(%ebx), %eax // ax = 0000000000020338<br>+ bt $DELIVERY_STS_BIT, %eax<br>+ jmp 7b<br>+6: //.endw<br>+ stc<br>+ //.while (carry?)<br>+7: jnc 6f<br>+ mov %es:(%ebx), %eax<br>+ and $REMOTE_READ_STS, %eax<br>+ //.if (eax == REMOTE_DELIVERY_PEND)<br>+ cmp $REMOTE_DELIVERY_PEND, %eax<br>+ jnz 8f<br>+ dec %ch // Check the timeout<br>+ jz fam15_disable_stack_hook_exit // Branch if there is an unreponsive core<br>+ stc<br>+ jmp 9f<br>+8: //.else<br>+ clc<br>+9: //.endif<br>+ jmp 7b<br>+6: //.endw<br>+ //.if (eax == REMOTE_DELIVERY_DONE)<br>+ cmp $REMOTE_DELIVERY_DONE, %eax<br>+ jnz 6f<br>+ and $0x0F000, %bx //EBX = LAPIC base, offset 0<br>+ or $APIC_REMOTE_READ_REG, %bl<br>+ mov %es:(%ebx), %eax<br>+ //.if (eax == APIC_MSG)<br>+ cmp $APIC_MSG, %eax // ax=00000000FFC5BBB2<br>+ jnz 8f<br>+ clc<br>+ jmp 9f<br>+ //.else<br>+8: stc<br>+9: //.endif<br>+ jmp 7f<br>+6: //.else<br>+ dec %ch<br>+ jz fam15_disable_stack_remote_read_exit<br>+ stc<br>+7: //.endif<br>+ jmp 5b<br>+4: //.endw<br>+<br>+fam15_disable_stack_remote_read_exit:<br>+ rol $8, %ecx // Restore ECX<br>+<br>+1: //.endif<br>+<br>+ bt $AMD_CU_RESTORE_ES, %ecx<br>+ //.if (carry?)<br>+ jnc 1f<br>+ mov %cx, %es<br>+1:<br>+ mov %ecx, %edi<br>+ shr $16, %edx<br>+ mov %dx, %bx<br>+<br>+ //Handshaking complete. Continue tearing down CAR.<br>+<br>+ mov $LS_CFG, %ecx // MSR:C001_1020<br>+ //.if (bx != 0) ; Is this OR A0?<br>+ cmp $0x0, %bx<br>+ jz 0f<br>+ _RDMSR<br>+ btr $DIS_SS, %eax // Turn on Streaming store functionality<br>+ _WRMSR<br>+ //.endif<br>+0: // End workaround for errata 495 and 496<br>+<br>+ inc %ecx //IC_CFG // MSR:C001_1021<br>+ _RDMSR<br>+ btr $IC_DIS_SPEC_TLB_RLD, %eax // Turn on speculative TLB reloads<br>+ _WRMSR<br>+<br>+ inc %ecx //DC_CFG // MSR:C001_1022<br>+ _RDMSR<br>+ btr $DC_DIS_SPEC_TLB_RLD, %eax // Turn on speculative TLB reloads<br>+ //.if (bx != 0) // Is this rev A0?<br>+ cmp $0, %bx<br>+ jz 0f<br>+ btr $DIS_HW_PF, %eax // Turn on hardware prefetches<br>+ //.endif // End workaround for erratum 498<br>+ 0:<br>+ _WRMSR<br>+ //--------------------------------------------------------------------------<br>+ // Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>+ //--------------------------------------------------------------------------<br>+<br>+ mov $HWCR, %ecx // MSR:C001_0015h<br>+ _RDMSR<br>+ btr $INVD_WBINVD, %eax // Disable INVD -> WBINVD conversion<br>+ _WRMSR<br>+<br>+ //--------------------------------------------------------------------------<br>+ // Send cache to memory. Preserve stack and coreboot CAR globals.<br>+ // This shouldn't be used with S3 resume IF the stack/cache area is<br>+ // not reserved and over system memory.<br>+ //--------------------------------------------------------------------------<br>+ wbinvd<br>+<br>+ //.if (bh == 01h) || (bh == 03h) ; Is this TN or KM?<br>+ cmp $01, %bh<br>+ jz 4f<br>+ cmp $03, %bh<br>+ jnz 1f<br>+4: mov $CU_CFG, %ecx // MSR:C001_1023<br>+ _RDMSR<br>+ shr $L2_FIRST_LOCKED_WAY, %eax<br>+ and $0x1F, %eax<br>+ //.if (eax == 01Fh)<br>+ cmp $0x1F, %eax //Check if way 15 of the L2 needs to be reserved<br>+ jnz 3f<br>+ _RDMSR<br>+ btr $L2_WAY_LOCK_EN, %eax<br>+ _WRMSR<br>+3: //.endif<br>+<br>+1: //.endif<br>+ //Do Standard Family 15 work<br>+ mov $HWCR, %ecx // MSR:C001_0015h<br>+ _RDMSR<br>+ bts $INVD_WBINVD, %eax // Turn on Conversion of INVD to WBINVD<br>+ _WRMSR<br>+ //.endif // end<br>+ 0:<br>+//<br>+// //--------------------------------------------------------------------------<br>+// // End critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>+// //--------------------------------------------------------------------------<br>+//<br>+ mov $CU_CFG3, %ecx // MSR:C001_102B<br>+ _RDMSR<br>+ bts $(COMBINE_CR0_CD - 32), %edx // Set CombineCr0Cd bit<br>+ _WRMSR<br>+<br>+ bt $AMD_CU_SEND_INVD_MSG, %edi<br>+ //.if (carry?)<br>+ jnc 1f<br>+ // Non core zero needs to signal to core 0 to proceed<br>+ mov $APIC_BASE_ADDRESS, %ecx<br>+ _RDMSR<br>+ mov %eax, %ebx // EBX = LAPIC base<br>+ and $0x0F000, %bx // EBX = LAPIC base, offset 0<br>+ or $APIC_MSG_REG, %bx<br>+ mov $APIC_MSG, %eax<br>+ mov %eax, %es:(%ebx) // Signal for core 0 to complete CAR breakdown<br>+<br>+1: //.endif<br>+<br>+fam15_disable_stack_hook_exit:<br>+.endm<br>+<br>+/*****************************************************************************<br>+*<br>+* GET_NODE_ID_CORE_ID_F15 Macro - Stackless<br>+*<br>+* Read family specific values to determine the node and core<br>+* numbers for the core executing this code.<br>+*<br>+* Inputs:<br>+* none<br>+* Outputs:<br>+* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)<br>+*****************************************************************************/<br>+.macro GET_NODE_ID_CORE_ID_F15<br>+<br>+ //LOCAL node_core_f15_exit<br>+ //LOCAL node_core_f15_AP<br>+ //LOCAL node_core_f15_shared<br>+ //LOCAL node_core_f15_AP_not_TN<br>+<br>+#define F15_L2Size 512<br>+#define F15_ShareCores 2<br>+#define F15_AllocMem 0<br>+#define F15_AllocExe 0<br>+#define F15_SzAddrBus 48<br>+#define F15_pad 0<br>+ cmp $-1, %si // Has node/core already been discovered?<br>+ jnz node_core_f15_exit // Br if yes<br>+<br>+ AMD_CPUID $CPUID_MODEL<br>+ shr $12, %eax // AL = cpu extended family<br>+ cmp $06, %ah // Is this family 15h?<br>+ jnz node_core_f15_exit // Br if no<br>+ shr $4, %al // AL = cpu extended model<br>+ shr $16, %ebx // BH = LocalApicId<br>+ mov %al, %bl // BL = cpu extended model<br>+<br>+ // LoadTableAddress(FAM15H_INFO_STRUCT)<br>+ // movd mm5, eax // load pointer to Family Info Struc<br>+<br>+ xor %esi, %esi // Assume BSC, clear local flags<br>+ mov $APIC_BASE_ADDRESS, %ecx // MSR:0000_001B<br>+ _RDMSR<br>+ bt $APIC_BSC, %eax // Is this the BSC?<br>+ jnc node_core_f15_AP // Br if no<br>+<br>+ // This is the BSP.<br>+ // Enable routing tables on BSP (just in case the HT init code has not yet enabled them)<br>+ mov $0x8000C06C, %eax // PCI address for D18F0x6C Link Initialization Control Register<br>+ mov $0x0CF8, %dx<br>+ out %eax, %dx<br>+ add $4, %dx<br>+ in %dx, %eax<br>+ btr $0, %eax // Set LinkInitializationControl[RouteTblDis] = 0<br>+ out %eax, %dx<br>+ jmp node_core_f15_shared //<br>+<br>+node_core_f15_AP:<br>+ mov %bl, %al // AL = cpu extended model<br>+ shr $8, %bx // BL = CPUID Fn0000_0001_EBX[LocalApicId]<br>+ cmp $1, %al // Is This TN?<br>+ jz 4f<br>+ cmp $3, %al<br>+ jnz node_core_f15_AP_not_TN<br>+4: mov %bx, %si<br>+ jmp node_core_f15_shared<br>+ //<br>+ // This is an AP. Routing tables have been enabled by the HT Init process.<br>+ // Also, the MailBox register was set by the BSP during early init<br>+ // The Mailbox register content is formatted as follows:<br>+ // UINT32 Node:4; // The node id of Core's node.<br>+ // UINT32 Socket:4; // The socket of this Core's node.<br>+ // UINT32 Module:2; // The internal module number for Core's node.<br>+ // UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1.<br>+ // UINT32 :20; // Reserved<br>+ //<br>+node_core_f15_AP_not_TN:<br>+ mov $0x0C0000408, %ecx // Read the family 15h mailbox<br>+ _RDMSR // MC4_MISC1[63:32]<br>+ mov %dx, %si // SI = raw mailbox contents (will extract node# from this)<br>+ shr $24, %ebx // BL = CPUID Fn0000_0001_EBX[LocalApicId]<br>+ mov %bx, %di // DI = Initial APIC ID (will extract core# from this)<br>+<br>+ AMD_CPUID $AMD_CPUID_APIC //<br>+ shr $4, %ch // CH = ApicIdSize, #bits in APIC ID that show core#<br>+ inc %cl // CL = Number of enabled cores in the socket<br>+ mov %cx, %bx<br>+<br>+ mov $NB_CFG, %ecx<br>+ _RDMSR // EDX has InitApicIdCpuIdLo bit<br>+<br>+ mov %bh, %cl // CL = APIC ID size<br>+ mov $1, %al // Convert APIC ID size to an AND mask<br>+ shl %cl, %al // AL = 2^APIC ID size<br>+ dec %al // AL = mask for relative core number<br>+ xor %ah, %ah // AX = mask for relative core number<br>+ bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx // InitApicIdCpuIdLo == 1?<br>+ //.if (!carry?) // Br if yes<br>+ jc 0f<br>+ mov $8, %ch // Calculate core number shift count<br>+ sub %cl, %ch // CH = core shift count<br>+ mov %ch, %cl<br>+ shr %cl, %di // Right justify core number<br>+ //.endif<br>+ 0:<br>+ and %ax, %di // DI = socket-relative core number<br>+<br>+ mov %si, %cx // CX = raw mailbox value<br>+ shr $10, %cx // CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)<br>+ and $3, %cl // Isolate ModuleType<br>+ xor %bh, %bh // BX = Number of enabled cores in the socket<br>+ shr %cl, %bx // BX = Number of enabled cores per node<br>+ xor %dx, %dx // Clear upper word for div<br>+ mov %di, %ax // AX = socket-relative core number<br>+ div %bx // DX = node-relative core number<br>+ movzx %si, %eax // Prepare return value<br>+ and $0x000F, %ax // AX = node number<br>+ shl $8,%ax // [15:8]=node#<br>+ mov %dl, %al // [7:0]=core# (relative to node)<br>+ mov %eax, %esi // ESI = node-relative core number<br>+<br>+ //<br>+ // determine if this core shares MTRRs<br>+ //<br>+node_core_f15_shared:<br>+ mov $0x8000C580, %eax // Compute Unit Status<br>+ mov %si, %bx<br>+ shl $3, %bh // Move node# to PCI Dev# field<br>+ add %bh, %ah // Adjust for node number<br>+ mov $0x0CF8, %dx<br>+ out %eax, %dx<br>+ add $4, %dx<br>+ in %dx, %eax // [3:0]=Enabled# [19:16]=DualCore<br>+<br>+ // BL is MyCore#<br>+ mov $0x06, %cx // Use CH as 'first of pair' core#<br>+ //.while (cl > 0)<br>+ jmp 0f<br>+ 8:<br>+ bt $0, %eax // Is pair enabled?<br>+ //.if (carry?) //<br>+ jnc 1f<br>+ mov $0x01, %bh // flag core as primary<br>+ bt $16, %eax // Is there a 2nd in the pair?<br>+ //.if (carry?) //<br>+ jnc 4f<br>+ //.break .if (ch == bl) // Does 1st match MyCore#?<br>+ cmp %bl, %ch<br>+ je 9f<br>+ inc %ch<br>+ xor %bh, %bh // flag core as NOT primary<br>+ //.break .if (ch == bl) // Does 2nd match MyCore#?<br>+ cmp %bl, %ch<br>+ je 9f<br>+ jmp 2f<br>+ //.else // No 2nd core<br>+ 4:<br>+ //.break .if (ch == bl) // Does 1st match MyCore#?<br>+ cmp %bl, %ch<br>+ je 9f<br>+ //.endif<br>+ 2:<br>+ inc %ch<br>+ //.endif<br>+ 1:<br>+ shr $1, %eax<br>+ dec %cl<br>+ //.endw<br>+ 0:<br>+ //.if (cl == 0)<br>+ cmp $0x0, %cl<br>+ ja 8b<br>+ 9:<br>+ or %cl, %cl<br>+ jne 1f<br>+ //Error - core# didn't match Compute Unit Status content<br>+ bts $FLAG_CORE_NOT_IDENTIFIED, %esi<br>+ bts $FLAG_IS_PRIMARY, %esi // Set Is_Primary for unknowns<br>+ //.endif<br>+ 1:<br>+ //.if (bh != 0) // Check state of primary for the matched core<br>+ or %bh, %bh<br>+ je 2f<br>+ bts $FLAG_IS_PRIMARY, %esi // Set shared flag into return value<br>+ //.endif<br>+ 2:<br>+<br>+node_core_f15_exit:<br>+<br>+.endm<br>+<br> /****************************************************************************<br> *<br> * AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless<br>@@ -264,1246 +1513,6 @@<br> AMD_DISABLE_STACK_FAMILY_HOOK_F12<br> AMD_DISABLE_STACK_FAMILY_HOOK_F14<br> AMD_DISABLE_STACK_FAMILY_HOOK_F15<br>-<br>-.endm<br>-<br>-/****************************************************************************<br>-*<br>-* GET_NODE_ID_CORE_ID Macro - Stackless<br>-*<br>-* Read family specific values to determine the node and core<br>-* numbers for the core executing this code.<br>-*<br>-* Inputs:<br>-* none<br>-* Outputs:<br>-* SI[7:0] = Core# (0..N, relative to node)<br>-* SI[15:8]= Node# (0..N)<br>-* SI[23:16]= reserved<br>-* SI[24]= flag: 1=Family Unrecognized<br>-* SI[25]= flag: 1=Interface re-entry call<br>-* SI[26]= flag: 1=Core is primary of compute unit<br>-* SI[31:27]= reserved, =0<br>-****************************************************************************/<br>-.macro GET_NODE_ID_CORE_ID<br>- LOCAL node_core_exit<br>-<br>- mov $-1, %si<br>- GET_NODE_ID_CORE_ID_F10<br>- GET_NODE_ID_CORE_ID_F12<br>- GET_NODE_ID_CORE_ID_F14<br>- GET_NODE_ID_CORE_ID_F15<br>- /*<br>- * Check for unrecognized Family<br>- */<br>- cmp $-1, %si # Has family (node/core) already been discovered?<br>- jnz node_core_exit # Br if yes<br>-<br>- mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue<br>-<br>- mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B<br>- _RDMSR<br>- bt $APIC_BSC, %eax # Is this the BSC?<br>- jc node_core_exit # Br if yes<br>- hlt # Kill APs<br>-node_core_exit:<br>-<br>-.endm<br>-<br>-/****************************************************************************<br>-## Family 10h MACROS<br>-##***************************************************************************<br>-#---------------------------------------------------<br>-#<br>-# AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless<br>-#<br>-# Set any family specific controls needed to enable the use of<br>-# cache as general storage before main memory is available.<br>-#<br>-# Inputs:<br>-# ESI - node#, core#, flags from GET_NODE_ID_CORE_ID<br>-# Outputs:<br>-# none<br>-#<br>-# Family 10h requirements (BKDG section 2.3.3):<br>-# * Paging disabled<br>-# * MSRC001_0015[INVDWBINVD]=0<br>-# * MSRC001_1021[DIS_IND]=1<br>-# * MSRC001_1021[DIS_SPEC_TLB_RLD]=1<br>-# * MSRC001_1022[DIS_SPEC_TLB_RLD]=1<br>-# * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1<br>-# * MSRC001_1022[DIS_HW_PF]=1<br>-# * MSRC001_102A[IcDisSpecTlbWr]=1<br>-# * MSRC001_102A[ClLinesToNbDis]=1<br>-# * No INVD or WBINVD, no exceptions, page faults or interrupts<br>-****************************************************************************/<br>-.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10<br>- LOCAL fam10_enable_stack_hook_exit<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- shr $20, %eax # AL = cpu extended family<br>- cmp $0x01, %al # Is this family 10h?<br>- jnz fam10_enable_stack_hook_exit # Br if no<br>-<br>- mov $DC_CFG, %ecx # MSR:C001_1022<br>- _RDMSR<br>- bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DTLB reloads bit<br>- bts $DIS_CLR_WBTOL2_SMC_HIT, %eax # Turn on Disable the self modifying code check buffer bit<br>- bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit<br>- _WRMSR<br>-<br>- dec %cx # MSR:C001_1021<br>- _RDMSR<br>- bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative TLB reloads bit<br>- bts $DIS_IND, %eax # Turn on Disable indirect branch predictor<br>- _WRMSR<br>-<br>- mov $BU_CFG2, %ecx # MSR C001_102A<br>- _RDMSR<br>- bts $F10_CL_LINES_TO_NB_DIS, %eax # Allow BIOS ROM to be cached in the IC<br>- bts $(IC_DIS_SPEC_TLB_WR-32), %edx #Disable speculative writes to the ITLB<br>- _WRMSR<br>-<br>- mov $HWCR, %ecx # MSR C001_0015<br>- _RDMSR<br>- bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set<br>- jc fam10_skipClearingBit4<br>- btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion<br>- _WRMSR<br>-<br>-fam10_skipClearingBit4:<br>- mov %esi, %eax # load core#<br>- or %al, %al # If (BSP)<br>- jne fam10_enable_stack_hook_exit<br>- mov $PERF_COUNTER3, %ecx # Select performance counter three<br>- # to count number of CAR evictions<br>- xor %eax, %eax # Initialize the lower part of the counter to zero<br>- xor %edx, %edx # Initializa the upper part of the counter to zero<br>- _WRMSR # Save it<br>- mov $PERF_CONTROL3, %ecx # Select the event control three<br>- _RDMSR # Get the current setting<br>- and $PERF_CONTROL3_RESERVE_L, %eax # Preserve the reserved bits<br>- or $CONFIG_EVENT_L, %eax # Set the lower part of event register to<br>- # select CAR Corruption occurred by any cores<br>- and $PERF_CONTROL3_RESERVE_H, %dx # Preserve the reserved bits<br>- or $CONFIG_EVENT_H, %dx # Set the upper part of event register<br>- _WRMSR # Save it<br>- bts $EVENT_ENABLE, %eax # Enable it<br>- _WRMSR # Save it<br>-<br>-fam10_enable_stack_hook_exit:<br>-.endm<br>-<br>-/****************************************************************************<br>-*<br>-* AMD_DISABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless<br>-*<br>-* Return any family specific controls to their 'standard'<br>-* settings for using cache with main memory.<br>-*<br>-* Inputs:<br>-* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#<br>-* Outputs:<br>-* none<br>-*<br>-* Family 10h requirements:<br>-* * INVD or WBINVD<br>-* * MSRC001_0015[INVD_WBINVD]=1<br>-* * MSRC001_1021[DIS_IND]=0<br>-* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0<br>-* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0<br>-* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0<br>-* * MSRC001_1022[DIS_HW_PF]=0<br>-* * MSRC001_102A[IcDisSpecTlbWr]=0<br>-* * MSRC001_102A[ClLinesToNbDis]=0<br>-*****************************************************************************/<br>-<br>-.macro AMD_DISABLE_STACK_FAMILY_HOOK_F10<br>- LOCAL fam10_disable_stack_hook_exit<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- shr $20, %eax # AL = cpu extended family<br>- cmp $0x01, %al # Is this family 10h?<br>- jnz fam10_disable_stack_hook_exit # Br if no<br>-<br>- mov $DC_CFG, %ecx # MSR:C001_1022<br>- _RDMSR<br>- btr $DC_DIS_SPEC_TLB_RLD, %eax # Enable speculative TLB reloads<br>- btr $DIS_CLR_WBTOL2_SMC_HIT, %eax # Allow self modifying code check buffer<br>- btr $DIS_HW_PF, %eax # Allow hardware prefetches<br>- _WRMSR<br>-<br>- dec %cx # MSR:C001_1021<br>- _RDMSR<br>- btr $DIS_IND, %eax # Turn on indirect branch predictor<br>- btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads<br>- _WRMSR<br>-<br>- mov $BU_CFG2, %ecx # MSR:C001_102A<br>- _RDMSR<br>- btr $F10_CL_LINES_TO_NB_DIS, %eax # Return L3 to normal mode<br>- btr $(IC_DIS_SPEC_TLB_WR-32), %edx #Re-enable speculative writes to the ITLB<br>- _WRMSR<br>-<br>- #--------------------------------------------------------------------------<br>- # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>- #--------------------------------------------------------------------------<br>-<br>- mov $HWCR, %ecx # MSR:0000_0015<br>- _RDMSR<br>- mov %ax, %bx # Save INVD -> WBINVD bit<br>- btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion for the invd instruction.<br>- _WRMSR<br>- invd # Clear the cache tag RAMs<br>- mov %bx, %ax # Restore INVD -> WBINVD bit<br>- _WRMSR<br>-<br>- #--------------------------------------------------------------------------<br>- # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>- #--------------------------------------------------------------------------<br>-<br>- mov $PERF_CONTROL3, %ecx # Select the event control three<br>- _RDMSR # Retrieve the current value<br>- btc $EVENT_ENABLE, %eax # Is event enable, complement it as well<br>- jnc fam10_disable_stack_hook_exit # No<br>- cmp $CONFIG_EVENT_L, %ax # Is the lower part of event set to capture the CAR Corruption<br>- jne fam10_disable_stack_hook_exit # No<br>- cmp $CONFIG_EVENT_H, %dl # Is the upper part of event set to capture the CAR Corruption<br>- jne fam10_disable_stack_hook_exit # No<br>- _WRMSR # Disable the event<br>-<br>-fam10_disable_stack_hook_exit:<br>-.endm<br>-<br>-/****************************************************************************<br>-*<br>-* GET_NODE_ID_CORE_ID_F10 Macro - Stackless<br>-*<br>-* Read family specific values to determine the node and core<br>-* numbers for the core executing this code.<br>-*<br>-* Inputs:<br>-* none<br>-* Outputs:<br>-* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)<br>-*****************************************************************************/<br>-.macro GET_NODE_ID_CORE_ID_F10<br>-<br>- LOCAL node_core_f10_exit<br>- LOCAL node_core_f10_AP<br>-<br>- cmp $-1, %si # Has node/core already been discovered?<br>- jnz node_core_f10_exit # Br if yes<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- shr $20, %eax # AL = cpu extended family<br>- cmp $0x01, %al # Is this family 10h?<br>- jnz node_core_f10_exit # Br if no<br>-<br>- xor %esi, %esi # Assume BSC, clear flags<br>- mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B<br>- _RDMSR<br>- bt $APIC_BSC, %eax # Is this the BSC?<br>- jnc node_core_f10_AP # Br if no<br>-<br>- # This is the BSP.<br>- # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)<br>- mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register<br>- mov $0x0CF8, %dx<br>- out %eax, %dx<br>- add $4, %dx<br>- in %dx, %eax<br>- btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0<br>- out %eax, %dx<br>- jmp 1f #<br>-<br>-node_core_f10_AP:<br>- #<br>- # This is an AP. Routing tables have been enabled by the HT Init process.<br>- # Also, the MailBox register was set by the BSP during early init<br>- # The Mailbox register content is formatted as follows:<br>- # UINT32 Node:4# // The node id of Core's node.<br>- # UINT32 Socket:4# // The socket of this Core's node.<br>- # UINT32 Module:2# // The internal module number for Core's node.<br>- # UINT32 ModuleType:2# // Single Module = 0, Multi-module = 1.<br>- # UINT32 :20# // Reserved<br>- #<br>- mov $0x0C0000408, %ecx # Read the family 10h mailbox<br>- _RDMSR # MC4_MISC1[63:32]<br>- mov %dx, %si # SI = raw mailbox contents (will extract node# from this)<br>- shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId]<br>- mov %bx, %di # DI = Initial APIC ID (will extract core# from this)<br>-<br>- AMD_CPUID $AMD_CPUID_APIC #<br>- shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core#<br>- inc %cl # CL = Number of enabled cores in the socket<br>- mov %cx, %bx<br>-<br>- mov $NB_CFG, %ecx # MSR:C001_001F<br>- _RDMSR # EDX has InitApicIdCpuIdLo bit<br>-<br>- mov %bh, %cl # CL = APIC ID size<br>- mov $1, %al # Convert APIC ID size to an AND mask<br>- shl %cl, %al # AL = 2^APIC ID size<br>- dec %al # AL = mask for relative core number<br>- xor %ah, %ah # AX = mask for relative core number<br>- bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1?<br>- #.if (!carry?) # Br if yes<br>- jc 0f<br>- mov $8, %ch # Calculate core number shift count<br>- sub %cl, %ch # CH = core shift count<br>- mov %ch, %cl<br>- shr %cl, %di # Right justify core number<br>- #.endif<br>- 0:<br>- and %ax, %di # DI = socket-relative core number<br>-<br>- mov %si, %cx # CX = raw mailbox value<br>- shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)<br>- and $3, %cl # Isolate ModuleType<br>- xor %bh, %bh # BX = Number of enabled cores in the socket<br>- shr %cl, %bx # BX = Number of enabled cores per node<br>- xor %dx, %dx # Clear upper word for div<br>- mov %di, %ax # AX = socket-relative core number<br>- div %bx # DX = node-relative core number<br>- movzx %si, %eax # prepare return value, [23:16]=shared Core# (=0, not shared)<br>- and $0x000F, %ax # AX = node number<br>- shl $8, %ax # [15:8]=node#<br>- mov %dl, %al # [7:0]=core# (relative to node)<br>- mov %eax, %esi # ESI = return value<br>-1:<br>- bts $FLAG_IS_PRIMARY, %esi # all Family 10h cores are primary<br>-node_core_f10_exit:<br>-.endm<br>-<br>-/*****************************************************************************<br>-** Family 12h MACROS<br>-*****************************************************************************/<br>-/*****************************************************************************<br>-*<br>-* AMD_ENABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless<br>-*<br>-* Set any family specific controls needed to enable the use of<br>-* cache as general storage before main memory is available.<br>-*<br>-* Inputs:<br>-* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID<br>-* Outputs:<br>-* none<br>-*<br>-* Family 12h requirements (BKDG section 2.3.3):<br>-* The following requirements must be satisfied prior to using the cache as general storage:<br>-* * Paging must be disabled.<br>-* * MSRC001_0015[INVD_WBINVD]=0<br>-* * MSRC001_1020[DIS_SS]=1<br>-* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1<br>-* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1<br>-* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1<br>-* * MSRC001_1022[DIS_HW_PF]=1<br>-* * MSRC001_1029[ClflushSerialize]=1<br>-* * No INVD or WBINVD, no exceptions, page faults or interrupts<br>-*****************************************************************************/<br>-.macro AMD_ENABLE_STACK_FAMILY_HOOK_F12<br>- LOCAL fam12_enable_stack_hook_exit<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- shr $20, %eax # AL = cpu extended family<br>- cmp $0x03, %al # Is this family 12h?<br>- jnz fam12_enable_stack_hook_exit # Br if no<br>-<br>- mov $DC_CFG, %ecx # MSR:C001_1022<br>- _RDMSR<br>- bts $DC_DIS_SPEC_TLB_RLD, %eax # Disable speculative DC-TLB reloads<br>- bts $DIS_CLR_WBTOL2_SMC_HIT, %eax # Disable self modifying code check buffer<br>- bts $DIS_HW_PF, %eax # Disable hardware prefetches<br>- _WRMSR<br>-<br>- dec %cx #IC_CFG # MSR:C001_1021<br>- _RDMSR<br>- bts $IC_DIS_SPEC_TLB_RLD, %eax # Disable speculative IC-TLB reloads<br>- _WRMSR<br>-<br>- dec %cx #LS_CFG # MSR:C001_1020<br>- _RDMSR<br>- bts $DIS_SS, %eax # Disabled Streaming store functionality<br>- _WRMSR<br>-<br>- mov $HWCR, %ecx # MSR C001_0015<br>- _RDMSR<br>- bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set<br>- jc fam12_skipClearingBit4<br>- btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion<br>- _WRMSR<br>-<br>-fam12_skipClearingBit4:<br>- mov $DE_CFG, %ecx # MSR:C001_1029<br>- _RDMSR<br>- bts $CL_FLUSH_SERIALIZE, %eax # Serialize all CL Flush actions<br>- _WRMSR<br>-<br>-fam12_enable_stack_hook_exit:<br>-.endm<br>-<br>-/*****************************************************************************<br>-*<br>-* AMD_DISABLE_STACK_FAMILY_HOOK_F12 Macro - Stackless<br>-*<br>-* Return any family specific controls to their 'standard'<br>-* settings for using cache with main memory.<br>-*<br>-* Inputs:<br>-* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#<br>-* Outputs:<br>-* none<br>-*<br>-* Family 12h requirements:<br>-* * INVD or WBINVD<br>-* * MSRC001_0015[INVD_WBINVD]=1<br>-* * MSRC001_1020[DIS_SS]=0<br>-* * MSRC001_1021[IC_DIS_SPEC_TLB_RLD]=0<br>-* * MSRC001_1022[DC_DIS_SPEC_TLB_RLD]=0<br>-* * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=0<br>-* * MSRC001_1022[DIS_HW_PF]=0<br>-* * MSRC001_1029[ClflushSerialize]=0<br>-*****************************************************************************/<br>-.macro AMD_DISABLE_STACK_FAMILY_HOOK_F12<br>- LOCAL fam12_disable_stack_hook_exit<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- shr $20, %eax # AL = cpu extended family<br>- cmp $0x03, %al # Is this family 12h?<br>- jnz fam12_disable_stack_hook_exit # Br if no<br>-<br>- mov $DC_CFG, %ecx # MSR:C001_1022<br>- _RDMSR<br>- btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative DC-TLB reloads<br>- btr $DIS_CLR_WBTOL2_SMC_HIT, %eax # Enable self modifying code check buffer<br>- btr $DIS_HW_PF, %eax # Enable Hardware prefetches<br>- _WRMSR<br>-<br>- dec %cx #IC_CFG # MSR:C001_1021<br>- _RDMSR<br>- btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative IC-TLB reloads<br>- _WRMSR<br>-<br>- dec %cx #LS_CFG # MSR:C001_1020<br>- _RDMSR<br>- btr $DIS_SS, %eax # Turn on Streaming store functionality<br>- _WRMSR<br>-<br>- mov $DE_CFG, %ecx # MSR:C001_1029<br>- _RDMSR<br>- btr $CL_FLUSH_SERIALIZE, %eax<br>- _WRMSR<br>-<br>- #--------------------------------------------------------------------------<br>- # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>- #--------------------------------------------------------------------------<br>-<br>- mov $HWCR, %ecx # MSR:0000_0015h<br>- _RDMSR<br>- mov %ax, %bx # Save INVD -> WBINVD bit<br>- btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion<br>- _WRMSR<br>- invd # Clear the cache tag RAMs<br>- mov %bx, %ax # Restore INVD -> WBINVD bit<br>- _WRMSR<br>-<br>- #--------------------------------------------------------------------------<br>- # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>- #--------------------------------------------------------------------------<br>-<br>-fam12_disable_stack_hook_exit:<br>-.endm<br>-<br>-/*****************************************************************************<br>-*<br>-* GET_NODE_ID_CORE_ID_F12 Macro - Stackless<br>-*<br>-* Read family specific values to determine the node and core<br>-* numbers for the core executing this code.<br>-*<br>-* Inputs:<br>-* none<br>-* Outputs:<br>-* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)<br>-*****************************************************************************/<br>-.macro GET_NODE_ID_CORE_ID_F12<br>-<br>- LOCAL node_core_f12_exit<br>-<br>- cmp $-1, %si # Has node/core already been discovered?<br>- jnz node_core_f12_exit # Br if yes<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- shr $20, %eax # AL = cpu extended family<br>- cmp $0x03, %al # Is this family 12h?<br>- jnz node_core_f12_exit # Br if no<br>-<br>- shr $24, %ebx # CPUID_0000_0001_EBX[31:24]: initial local APIC physical ID<br>- bts $FLAG_IS_PRIMARY, %ebx # all family 12h cores are primary<br>- mov %ebx, %esi # ESI = Node#=0, core number<br>-node_core_f12_exit:<br>-.endm<br>-<br>-/*****************************************************************************<br>-** Family 14h MACROS<br>-*****************************************************************************/<br>-/*****************************************************************************<br>-*<br>-* AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless<br>-*<br>-* Set any family specific controls needed to enable the use of<br>-* cache as general storage before main memory is available.<br>-*<br>-* Inputs:<br>-* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID<br>-* Outputs:<br>-* none<br>-*<br>-* Family 14h requirements (BKDG section 2.3.3):<br>-* * Paging must be disabled.<br>-* * MSRC001_0015[INVD_WBINVD]=0.<br>-* * MSRC001_1020[DisStreamSt]=1.<br>-* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.<br>-* * MSRC001_1022[DIS_HW_PF]=1.<br>-* * No INVD or WBINVD, no exceptions, page faults or interrupts<br>-*****************************************************************************/<br>-.macro AMD_ENABLE_STACK_FAMILY_HOOK_F14<br>- LOCAL fam14_enable_stack_hook_exit<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- shr $20, %eax # AL = cpu extended family<br>- cmp $0x05, %al # Is this family 14h?<br>- jnz fam14_enable_stack_hook_exit # Br if no<br>-<br>- mov $DC_CFG, %ecx # MSR:C001_1022<br>- _RDMSR<br>- bts $DIS_HW_PF, %eax # Disable hardware prefetches<br>- _WRMSR<br>-<br>- dec %cx #IC_CFG # MSR:C001_1021<br>- _RDMSR<br>- bts $IC_DIS_SPEC_TLB_RLD, %eax # Disable speculative TLB reloads<br>- _WRMSR<br>-<br>- dec %cx #LS_CFG # MSR:C001_1020<br>- _RDMSR<br>- bts $DIS_STREAM_ST, %eax # Disabled Streaming store functionality<br>- _WRMSR<br>-<br>- mov $HWCR, %ecx # MSR C001_0015<br>- _RDMSR<br>- bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set<br>- jc fam14_skipClearingBit4<br>- btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion<br>- _WRMSR<br>-fam14_skipClearingBit4: # Keeping this label<br>-<br>-fam14_enable_stack_hook_exit:<br>-.endm<br>-<br>-/*****************************************************************************<br>-*<br>-* AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless<br>-*<br>-* Return any family specific controls to their 'standard'<br>-* settings for using cache with main memory.<br>-*<br>-* Inputs:<br>-* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#<br>-* Outputs:<br>-* none<br>-*<br>-* Family 14h requirements:<br>-* * INVD or WBINVD<br>-* * MSRC001_0015[INVD_WBINVD]=1.<br>-* * MSRC001_1020[DisStreamSt]=0.<br>-* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0.<br>-* * MSRC001_1022[DIS_HW_PF]=0.<br>-*****************************************************************************/<br>-.macro AMD_DISABLE_STACK_FAMILY_HOOK_F14<br>- LOCAL fam14_disable_stack_hook_exit<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- shr $20, %eax # AL = cpu extended family<br>- cmp $0x05, %al # Is this family 14h?<br>- jnz fam14_disable_stack_hook_exit # Br if no<br>-<br>- mov $LS_CFG, %ecx # MSR:C001_1020<br>- _RDMSR<br>- btr $DIS_STREAM_ST, %eax # Turn on Streaming store functionality<br>- _WRMSR<br>-<br>- inc %cx #IC_CFG # MSR:C001_1021<br>- _RDMSR<br>- btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative DC-TLB reloads<br>- _WRMSR<br>-<br>- inc %cx #DC_CFG # MSR:C001_1022<br>- _RDMSR<br>- btr $DIS_HW_PF, %eax # Turn on hardware prefetches<br>- _WRMSR<br>-<br>- #--------------------------------------------------------------------------<br>- # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>- #--------------------------------------------------------------------------<br>-<br>- mov $HWCR, %ecx # MSR:C001_0015h<br>- _RDMSR<br>- btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion<br>- _WRMSR<br>- invd # Clear the cache tag RAMs<br>- bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD<br>- _WRMSR<br>-<br>- #--------------------------------------------------------------------------<br>- # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>- #--------------------------------------------------------------------------<br>-<br>-fam14_disable_stack_hook_exit:<br>-.endm<br>-<br>-/*****************************************************************************<br>-*<br>-* GET_NODE_ID_CORE_ID_F14 Macro - Stackless<br>-*<br>-* Read family specific values to determine the node and core<br>-* numbers for the core executing this code.<br>-*<br>-* Inputs:<br>-* none<br>-* Outputs:<br>-* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)<br>-*****************************************************************************/<br>-.macro GET_NODE_ID_CORE_ID_F14<br>-<br>- LOCAL node_core_f14_exit<br>-<br>- cmp $-1, %si # Has node/core already been discovered?<br>- jnz node_core_f14_exit # Br if yes<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- shr $20, %eax # AL = cpu extended family<br>- cmp $0x05, %al # Is this family 14h?<br>- jnz node_core_f14_exit # Br if no<br>-<br>- xor %esi, %esi # Node must be 0<br>- bts $FLAG_IS_PRIMARY, %esi # all family 14h cores are primary<br>- mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B<br>- _RDMSR<br>- bt $APIC_BSC, %eax # Is this the BSC?<br>- jc node_core_f14_exit # Br if yes<br>- inc %si # Set core to 1<br>-node_core_f14_exit:<br>-.endm<br>-<br>-/*****************************************************************************<br>-** Family 15h MACROS<br>-*****************************************************************************/<br>-/*****************************************************************************<br>-*<br>-* AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless<br>-*<br>-* Set any family specific controls needed to enable the use of<br>-* cache as general storage before main memory is available.<br>-*<br>-* Inputs:<br>-* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID<br>-* Outputs:<br>-* none<br>-*<br>-* Family 15h requirements (BKDG #42301 section 2.3.3):<br>-* * Paging must be disabled.<br>-* * MSRC001_0015[INVD_WBINVD]=0<br>-* * MSRC001_1020[DisSS]=1<br>-* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1<br>-* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1<br>-* * MSRC001_1022[DisHwPf]=1<br>-* * No INVD or WBINVD, no exceptions, page faults or interrupts<br>-*****************************************************************************/<br>-.macro AMD_ENABLE_STACK_FAMILY_HOOK_F15<br>- LOCAL fam15_enable_stack_hook_exit<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- mov %eax, %ebx # Save revision info to EBX<br>- shr $20, %eax # AL = cpu extended family<br>- cmp $0x06, %al # Is this family 15h?<br>- jnz fam15_enable_stack_hook_exit # Br if no<br>-<br>- bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set<br>- jc fam15_skipClearingBit4<br>- mov $HWCR, %ecx # MSR C001_0015<br>- _RDMSR<br>- btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion<br>- _WRMSR<br>-<br>-fam15_skipClearingBit4:<br>- mov $LS_CFG, %ecx # MSR:C001_1020<br>- _RDMSR<br>- bts $DIS_SS, %eax # Turn on Streaming store functionality disabled bit<br>- _WRMSR<br>-<br>- inc %ecx #IC_CFG # MSR:C001_1021<br>- _RDMSR<br>- bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative IC-TLB reloads bit<br>- _WRMSR<br>-<br>- mov %ebx, %eax # Restore revision info to EAX<br>- shr $16, %eax<br>- and $0x0F, %al # AL = cpu extended model<br>-<br>- inc %ecx #DC_CFG # MSR:C001_1022<br>- _RDMSR<br>- bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DC-TLB reloads bit<br>- bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit<br>- _WRMSR # Remove KM in PI 1.1.0.0<br>-<br>- mov %ebx, %eax # Restore revision info to EAX<br>- shr $16, %eax<br>- and $0xF, %al<br>- #.if (al == 01h) || (al == 03h) Is this TN or KV?<br>- cmp $1, %eax<br>- jz 1f<br>- cmp $3, %eax<br>- jz 3f # Skip if it is KV, it is only for TN from Label 1 to 3<br>- jmp 2f<br>-1: #.if (al == 01h) # TN only<br>- #Enable MSRC001_001F[EnableCf8ExtCfg]<br>- mov $NB_CFG, %ecx # MSR:C001_001F<br>- _rdmsr<br>- bts $(ENABLE_CF8_EXT_CFG - 32), %edx<br>- _wrmsr<br>- # Set F3x44[6, CpuErrDis] = 1<br>- MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, 0x44 //MCA_NB_CFG<br>- //mov $(1 << 31 | 2 << 28 | (((MCA_NB_CFG) & (0x0F00)) >> 8) << 24 | 2 << 16 | 1 << 11 | FUNC_3 << 8), %eax<br>-<br>- mov $0xCF8, %dx<br>- out %eax, %dx<br>- add $4, %dx<br>- in %dx, %eax<br>- bts $CPU_ERR_DIS, %eax<br>- out %eax, %dx<br>-<br>-3: mov $CU_CFG, %ecx # TN or KV<br>- _RDMSR<br>- bt $L2_WAY_LOCK_EN, %eax<br>- #.if (!carry?)<br>- jc 2f<br>- bts $L2_WAY_LOCK_EN, %eax<br>- or $L2_FIRST_LOCKED_WAY_OR_MASK, %eax<br>- _WRMSR<br>- #.endif<br>- #.endif<br>-2:<br>- mov %ebx, %eax # Restore revision info to EAX<br>- xchg %ah, %al<br>- shr $8, %eax<br>- and $0xF, %al<br>- #.if (ax == 6100h) ; Is this TN-A0?<br>- cmp $0x6100, %ax<br>- jnz 2f<br>- MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, PRODUCT_INFO_REG1<br>- mov $0xCF8, %dx<br>- out %eax, %dx<br>- add $4, %dx<br>- in %dx, %eax<br>- bt $21, %eax<br>- jc 2f<br>- mov $CU_CFG2, %ecx #MSR:C001_102A<br>- _RDMSR<br>- bts $8, %eax<br>- _WRMSR<br>- # .endif<br>-<br>-2: # Do Standard Family 15 work<br>-<br>- mov $CU_CFG3, %ecx # MSR:C001_102B<br>- _RDMSR<br>- btr $(COMBINE_CR0_CD - 32), %edx # Clear CombineCr0Cd bit<br>- _WRMSR<br>-<br>-fam15_enable_stack_hook_exit:<br>-.endm<br>-<br>-/*****************************************************************************<br>-*<br>-* AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless<br>-*<br>-* Return any family specific controls to their 'standard'<br>-* settings for using cache with main memory.<br>-*<br>-* Note: Customized for coreboot:<br>-* A wbinvd is used to send cache to memory. The existing stack is preserved<br>-* at its original location and additional information is preserved (e.g.<br>-* coreboot CAR globals, heap structures, etc.). This implementation should<br>-* NOT be used with S3 resume IF the stack/cache area is not reserved and<br>-* over system memory.<br>-*<br>-* Inputs:<br>-* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#<br>-* Outputs:<br>-* none<br>-*<br>-* Family 15h requirements:<br>-* * INVD or WBINVD<br>-* * MSRC001_0015[INVD_WBINVD]=1<br>-* * MSRC001_1020[DisSS]=0<br>-* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0<br>-* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0<br>-* * MSRC001_1022[DIS_HW_PF]=0<br>-*****************************************************************************/<br>-.macro AMD_DISABLE_STACK_FAMILY_HOOK_F15<br>- LOCAL fam15_disable_stack_hook_exit<br>- LOCAL fam15_disable_stack_remote_read_exit<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- mov %eax, %ebx # Save revision info to EBX<br>- shr $20, %eax # AL = cpu extended family<br>- cmp $0x06, %al # Is this family 15h?<br>- jnz fam15_disable_stack_hook_exit # Br if no<br>-<br>- mov %ebx, %edi # Save revision info to EDI<br>- AMD_CPUID $AMD_CPUID_APIC<br>- mov %cl, %al # AL = number of cores - 1<br>- shr $APIC_ID_CORE_ID_SIZE, %cx # CL = ApicIdCoreIdSize<br>- mov $1, %bx<br>- shl %cl, %bl # BL = theoretical number of cores on socket<br>- dec %bx # BL = core number on socket mask<br>- mov %bl, %ah # AH = core number on socket mask<br>- mov %edi, %ebx # Restore revision info to EBX<br>- mov %ax, %di # DI[15:8] = core number mask, DI[7:0] = number of cores - 1<br>-<br>- and $0x0F00FF, %ebx<br>- mov %ebx, %eax<br>- shr $8, %eax<br>- or %ax, %bx # Save Extended Model, Model and Stepping to BX<br>- # [11:8] = Extended Model, [7:4] = Model, [3:0] = Stepping (bx=0000000000010100, ok)<br>-<br>- mov $APIC_BASE_ADDRESS, %ecx<br>- _RDMSR # dx=0 ax=fee00800<br>- mov %bx, %dx # Save Extended Model, Model and Stepping to DX<br>- shl $16, %edx #EDX[31:16] = Extended Model, Model and Stepping<br>- mov %eax ,%ebx # EBX = LAPIC base<br>- xor %ecx ,%ecx # Zero out CU flags<br>- bts $AMD_CU_NEED_TO_WAIT, %ecx # Default to waiting<br>- bts $AMD_CU_SEND_INVD_MSG, %ecx # Default to signaling<br>- mov %cr0, %eax<br>- bt $CR0_PE, %ax # Are we in protected mode?<br>- # .if (!carry?)<br>- jc 1f<br>- bts $AMD_CU_RESTORE_ES, %ecx # Indicate ES restore is required<br>- mov %es, %cx # Save ES segment register to CX<br>- xor %ax, %ax<br>- mov %ax, %es # Set ES to big real mode selector for 4GB access<br>- # .endif<br>-<br>-1:<br>- and $0x0F000, %bx # EBX = LAPIC base, offset 0<br>- or $APIC_ID_REG, %bl #<br>- mov %es:(%ebx), %eax # EAX[31:24] = APIC ID<br>- shr $APIC20_APICID, %eax # AL = APIC ID<br>- mov %al, %ah # AH = APIC ID<br>- mov %di, %dx # DH = core mask<br>- and %dh, %ah # AH = core number # ax=111 dx=01000F03<br>-<br>- # .if (zero?)<br>- jnz 1f<br>- # Core 0 of a socket<br>- btr $AMD_CU_SEND_INVD_MSG, %ecx # No need to signal after INVD<br>- #.if (dl != 0)<br>- cmp $0, %dl<br>- jz 2f<br>- # This socket has multiple cores<br>- and $0xf000, %bx # EBX = LAPIC base, offset 0<br>- or $APIC_MSG_REG, %bx<br>- mov $APIC_MSG, %edi<br>- mov %edi, %es:(%ebx) # Signal for non core 0s to complete CAR breakdown<br>- jmp 1f<br>- #.else<br>-2: btr $AMD_CU_NEED_TO_WAIT, %ecx # No need to wait on a single core CPU<br>- #.endif<br>- # .endif<br>-1:<br>-<br>- bt $AMD_CU_NEED_TO_WAIT, %ecx #cx = c0000000<br>- #.if (carry?)<br>- jnc 1f<br>- #.if (ah == dl)<br>- cmp %dl, %ah<br>- jnz 2f<br>- # This is the highest numbered core on this socket -- wait on core 0<br>- not %dh # Flip the mask to determine local core 0's APID ID<br>- and %dh, %al # AL = target APIC ID # ax=310<br>- jmp 3f<br>-2: #.else<br>- # All other cores (including core 0) wait on the next highest core.<br>- # In this way, cores will halt in a cascading fashion down to 0.<br>- inc %al<br>- #.endif<br>-3:<br>- shl $APIC20_APICID, %eax<br>- and $0x0F000, %bx<br>- or $APIC_CMD_HI_REG, %bx<br>- mov %eax, %es:(%ebx) # Set target APIC ID<br>-<br>- # Use bits 23:16 as a timeout for unresponsive cores<br>- ror $8, %ecx<br>- mov $0xFF, %ch<br>- stc<br>-<br>- #.while (carry?)<br>-5: jnc 4f<br>- and $0xF000, %bx #EBX = LAPIC base, offset 0<br>- or $APIC_CMD_LO_REG, %bx # bx = 00000000FEE00300<br>- mov $CMD_REG_TO_READ_DATA, %eax<br>- mov %eax, %es:(%ebx) #Fire remove read IPI<br>- inc %ch #Pre increment the timeout<br>- stc<br>- #.while (carry?)<br>-7: jnc 6f<br>- dec %ch #Check the timeout<br>- jz fam15_disable_stack_remote_read_exit<br>- mov %es:(%ebx), %eax # ax = 0000000000020338<br>- bt $DELIVERY_STS_BIT, %eax<br>- jmp 7b<br>-6: #.endw<br>- stc<br>- #.while (carry?)<br>-7: jnc 6f<br>- mov %es:(%ebx), %eax<br>- and $REMOTE_READ_STS, %eax<br>- #.if (eax == REMOTE_DELIVERY_PEND)<br>- cmp $REMOTE_DELIVERY_PEND, %eax<br>- jnz 8f<br>- dec %ch # Check the timeout<br>- jz fam15_disable_stack_hook_exit # Branch if there is an unreponsive core<br>- stc<br>- jmp 9f<br>-8: #.else<br>- clc<br>-9: #.endif<br>- jmp 7b<br>-6: #.endw<br>- #.if (eax == REMOTE_DELIVERY_DONE)<br>- cmp $REMOTE_DELIVERY_DONE, %eax<br>- jnz 6f<br>- and $0x0F000, %bx #EBX = LAPIC base, offset 0<br>- or $APIC_REMOTE_READ_REG, %bl<br>- mov %es:(%ebx), %eax<br>- #.if (eax == APIC_MSG)<br>- cmp $APIC_MSG, %eax # ax=00000000FFC5BBB2<br>- jnz 8f<br>- clc<br>- jmp 9f<br>- #.else<br>-8: stc<br>-9: #.endif<br>- jmp 7f<br>-6: #.else<br>- dec %ch<br>- jz fam15_disable_stack_remote_read_exit<br>- stc<br>-7: #.endif<br>- jmp 5b<br>-4: #.endw<br>-<br>-fam15_disable_stack_remote_read_exit:<br>- rol $8, %ecx # Restore ECX<br>-<br>-1: #.endif<br>-<br>- bt $AMD_CU_RESTORE_ES, %ecx<br>- #.if (carry?)<br>- jnc 1f<br>- mov %cx, %es<br>-1:<br>- mov %ecx, %edi<br>- shr $16, %edx<br>- mov %dx, %bx<br>-<br>- #Handshaking complete. Continue tearing down CAR.<br>-<br>- mov $LS_CFG, %ecx # MSR:C001_1020<br>- #.if (bx != 0) ; Is this OR A0?<br>- cmp $0x0, %bx<br>- jz 0f<br>- _RDMSR<br>- btr $DIS_SS, %eax # Turn on Streaming store functionality<br>- _WRMSR<br>- #.endif<br>-0: # End workaround for errata 495 and 496<br>-<br>- inc %ecx #IC_CFG # MSR:C001_1021<br>- _RDMSR<br>- btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads<br>- _WRMSR<br>-<br>- inc %ecx #DC_CFG # MSR:C001_1022<br>- _RDMSR<br>- btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads<br>- #.if (bx != 0) # Is this rev A0?<br>- cmp $0, %bx<br>- jz 0f<br>- btr $DIS_HW_PF, %eax # Turn on hardware prefetches<br>- #.endif # End workaround for erratum 498<br>- 0:<br>- _WRMSR<br>- #--------------------------------------------------------------------------<br>- # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>- #--------------------------------------------------------------------------<br>-<br>- mov $HWCR, %ecx # MSR:C001_0015h<br>- _RDMSR<br>- btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion<br>- _WRMSR<br>-<br>- #--------------------------------------------------------------------------<br>- # Send cache to memory. Preserve stack and coreboot CAR globals.<br>- # This shouldn't be used with S3 resume IF the stack/cache area is<br>- # not reserved and over system memory.<br>- #--------------------------------------------------------------------------<br>- wbinvd<br>-<br>- #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM?<br>- cmp $01, %bh<br>- jz 4f<br>- cmp $03, %bh<br>- jnz 1f<br>-4: mov $CU_CFG, %ecx # MSR:C001_1023<br>- _RDMSR<br>- shr $L2_FIRST_LOCKED_WAY, %eax<br>- and $0x1F, %eax<br>- #.if (eax == 01Fh)<br>- cmp $0x1F, %eax #Check if way 15 of the L2 needs to be reserved<br>- jnz 3f<br>- _RDMSR<br>- btr $L2_WAY_LOCK_EN, %eax<br>- _WRMSR<br>-3: #.endif<br>-<br>-1: #.endif<br>- #Do Standard Family 15 work<br>- mov $HWCR, %ecx # MSR:C001_0015h<br>- _RDMSR<br>- bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD<br>- _WRMSR<br>- #.endif # end<br>- 0:<br>-//<br>-// #--------------------------------------------------------------------------<br>-// # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.<br>-// #--------------------------------------------------------------------------<br>-//<br>- mov $CU_CFG3, %ecx # MSR:C001_102B<br>- _RDMSR<br>- bts $(COMBINE_CR0_CD - 32), %edx # Set CombineCr0Cd bit<br>- _WRMSR<br>-<br>- bt $AMD_CU_SEND_INVD_MSG, %edi<br>- #.if (carry?)<br>- jnc 1f<br>- # Non core zero needs to signal to core 0 to proceed<br>- mov $APIC_BASE_ADDRESS, %ecx<br>- _RDMSR<br>- mov %eax, %ebx # EBX = LAPIC base<br>- and $0x0F000, %bx # EBX = LAPIC base, offset 0<br>- or $APIC_MSG_REG, %bx<br>- mov $APIC_MSG, %eax<br>- mov %eax, %es:(%ebx) # Signal for core 0 to complete CAR breakdown<br>-<br>-1: #.endif<br>-<br>-fam15_disable_stack_hook_exit:<br>-.endm<br>-<br>-/*****************************************************************************<br>-*<br>-* GET_NODE_ID_CORE_ID_F15 Macro - Stackless<br>-*<br>-* Read family specific values to determine the node and core<br>-* numbers for the core executing this code.<br>-*<br>-* Inputs:<br>-* none<br>-* Outputs:<br>-* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)<br>-*****************************************************************************/<br>-.macro GET_NODE_ID_CORE_ID_F15<br>-<br>- LOCAL node_core_f15_exit<br>- LOCAL node_core_f15_AP<br>- LOCAL node_core_f15_shared<br>- LOCAL node_core_f15_AP_not_TN<br>-<br>-#define F15_L2Size 512<br>-#define F15_ShareCores 2<br>-#define F15_AllocMem 0<br>-#define F15_AllocExe 0<br>-#define F15_SzAddrBus 48<br>-#define F15_pad 0<br>- cmp $-1, %si # Has node/core already been discovered?<br>- jnz node_core_f15_exit # Br if yes<br>-<br>- AMD_CPUID $CPUID_MODEL<br>- shr $12, %eax # AL = cpu extended family<br>- cmp $06, %ah # Is this family 15h?<br>- jnz node_core_f15_exit # Br if no<br>- shr $4, %al # AL = cpu extended model<br>- shr $16, %ebx # BH = LocalApicId<br>- mov %al, %bl # BL = cpu extended model<br>-<br>- # LoadTableAddress(FAM15H_INFO_STRUCT)<br>- # movd mm5, eax # load pointer to Family Info Struc<br>-<br>- xor %esi, %esi # Assume BSC, clear local flags<br>- mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B<br>- _RDMSR<br>- bt $APIC_BSC, %eax # Is this the BSC?<br>- jnc node_core_f15_AP # Br if no<br>-<br>- # This is the BSP.<br>- # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)<br>- mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register<br>- mov $0x0CF8, %dx<br>- out %eax, %dx<br>- add $4, %dx<br>- in %dx, %eax<br>- btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0<br>- out %eax, %dx<br>- jmp node_core_f15_shared #<br>-<br>-node_core_f15_AP:<br>- mov %bl, %al # AL = cpu extended model<br>- shr $8, %bx # BL = CPUID Fn0000_0001_EBX[LocalApicId]<br>- cmp $1, %al # Is This TN?<br>- jz 4f<br>- cmp $3, %al<br>- jnz node_core_f15_AP_not_TN<br>-4: mov %bx, %si<br>- jmp node_core_f15_shared<br>- #<br>- # This is an AP. Routing tables have been enabled by the HT Init process.<br>- # Also, the MailBox register was set by the BSP during early init<br>- # The Mailbox register content is formatted as follows:<br>- # UINT32 Node:4; // The node id of Core's node.<br>- # UINT32 Socket:4; // The socket of this Core's node.<br>- # UINT32 Module:2; // The internal module number for Core's node.<br>- # UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1.<br>- # UINT32 :20; // Reserved<br>- #<br>-node_core_f15_AP_not_TN:<br>- mov $0x0C0000408, %ecx # Read the family 15h mailbox<br>- _RDMSR # MC4_MISC1[63:32]<br>- mov %dx, %si # SI = raw mailbox contents (will extract node# from this)<br>- shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId]<br>- mov %bx, %di # DI = Initial APIC ID (will extract core# from this)<br>-<br>- AMD_CPUID $AMD_CPUID_APIC #<br>- shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core#<br>- inc %cl # CL = Number of enabled cores in the socket<br>- mov %cx, %bx<br>-<br>- mov $NB_CFG, %ecx<br>- _RDMSR # EDX has InitApicIdCpuIdLo bit<br>-<br>- mov %bh, %cl # CL = APIC ID size<br>- mov $1, %al # Convert APIC ID size to an AND mask<br>- shl %cl, %al # AL = 2^APIC ID size<br>- dec %al # AL = mask for relative core number<br>- xor %ah, %ah # AX = mask for relative core number<br>- bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1?<br>- #.if (!carry?) # Br if yes<br>- jc 0f<br>- mov $8, %ch # Calculate core number shift count<br>- sub %cl, %ch # CH = core shift count<br>- mov %ch, %cl<br>- shr %cl, %di # Right justify core number<br>- #.endif<br>- 0:<br>- and %ax, %di # DI = socket-relative core number<br>-<br>- mov %si, %cx # CX = raw mailbox value<br>- shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)<br>- and $3, %cl # Isolate ModuleType<br>- xor %bh, %bh # BX = Number of enabled cores in the socket<br>- shr %cl, %bx # BX = Number of enabled cores per node<br>- xor %dx, %dx # Clear upper word for div<br>- mov %di, %ax # AX = socket-relative core number<br>- div %bx # DX = node-relative core number<br>- movzx %si, %eax # Prepare return value<br>- and $0x000F, %ax # AX = node number<br>- shl $8,%ax # [15:8]=node#<br>- mov %dl, %al # [7:0]=core# (relative to node)<br>- mov %eax, %esi # ESI = node-relative core number<br>-<br>- #<br>- # determine if this core shares MTRRs<br>- #<br>-node_core_f15_shared:<br>- mov $0x8000C580, %eax # Compute Unit Status<br>- mov %si, %bx<br>- shl $3, %bh # Move node# to PCI Dev# field<br>- add %bh, %ah # Adjust for node number<br>- mov $0x0CF8, %dx<br>- out %eax, %dx<br>- add $4, %dx<br>- in %dx, %eax # [3:0]=Enabled# [19:16]=DualCore<br>-<br>- # BL is MyCore#<br>- mov $0x06, %cx # Use CH as 'first of pair' core#<br>- #.while (cl > 0)<br>- jmp 0f<br>- 8:<br>- bt $0, %eax # Is pair enabled?<br>- #.if (carry?) #<br>- jnc 1f<br>- mov $0x01, %bh # flag core as primary<br>- bt $16, %eax # Is there a 2nd in the pair?<br>- #.if (carry?) #<br>- jnc 4f<br>- #.break .if (ch == bl) # Does 1st match MyCore#?<br>- cmp %bl, %ch<br>- je 9f<br>- inc %ch<br>- xor %bh, %bh # flag core as NOT primary<br>- #.break .if (ch == bl) # Does 2nd match MyCore#?<br>- cmp %bl, %ch<br>- je 9f<br>- jmp 2f<br>- #.else # No 2nd core<br>- 4:<br>- #.break .if (ch == bl) # Does 1st match MyCore#?<br>- cmp %bl, %ch<br>- je 9f<br>- #.endif<br>- 2:<br>- inc %ch<br>- #.endif<br>- 1:<br>- shr $1, %eax<br>- dec %cl<br>- #.endw<br>- 0:<br>- #.if (cl == 0)<br>- cmp $0x0, %cl<br>- ja 8b<br>- 9:<br>- or %cl, %cl<br>- jne 1f<br>- #Error - core# didn't match Compute Unit Status content<br>- bts $FLAG_CORE_NOT_IDENTIFIED, %esi<br>- bts $FLAG_IS_PRIMARY, %esi # Set Is_Primary for unknowns<br>- #.endif<br>- 1:<br>- #.if (bh != 0) # Check state of primary for the matched core<br>- or %bh, %bh<br>- je 2f<br>- bts $FLAG_IS_PRIMARY, %esi # Set shared flag into return value<br>- #.endif<br>- 2:<br>-<br>-node_core_f15_exit:<br> <br> .endm<br> <br>@@ -1574,325 +1583,325 @@<br> *****************************************************************************/<br> .macro AMD_ENABLE_STACK<br> <br>-# These are local labels. Declared so linker doesn't cause 'redefined label' errors<br>- LOCAL SetupStack<br>- LOCAL Real16bMode<br>- LOCAL Protected32Mode<br>- LOCAL ClearTheStack<br>+// These are local labels. Declared so linker doesn't cause 'redefined label' errors<br>+ //LOCAL SetupStack<br>+ //LOCAL Real16bMode<br>+ //LOCAL Protected32Mode<br>+ //LOCAL ClearTheStack<br> <br>-# Note that SS:ESP will be default stack. Note that this stack<br>-# routine will not be used after memory has been initialized. Because<br>-# of its limited lifetime, it will not conflict with typical PCI devices.<br>+// Note that SS:ESP will be default stack. Note that this stack<br>+// routine will not be used after memory has been initialized. Because<br>+// of its limited lifetime, it will not conflict with typical PCI devices.<br> <br>- # get node id and core id of current executing core<br>- GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)<br>- # Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established<br>+ // get node id and core id of current executing core<br>+ GET_NODE_ID_CORE_ID // Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)<br>+ // Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established<br> <br>- # determine if stack is already enabled. We are using the DefType MSR for this determination.<br>- # It is =0 after reset; CAR setup sets it to enable the MTRRs<br>+ // determine if stack is already enabled. We are using the DefType MSR for this determination.<br>+ // It is =0 after reset; CAR setup sets it to enable the MTRRs<br> mov %cr0, %eax<br>- test $CR0_MASK, %eax # Is cache disabled? (CD & NW bits)<br>- jnz SetupStack # Jump if yes<br>- mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF<br>+ test $CR0_MASK, %eax // Is cache disabled? (CD & NW bits)<br>+ jnz SetupStack // Jump if yes<br>+ mov $AMD_MTRR_DEFTYPE, %ecx // MSR:0000_02FF<br> _RDMSR<br>- test $MSR_MASK, %eax # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)<br>- jz SetupStack # Jump if no<br>- or $FLAG_STACK_REENTRY, %esi # Bit25, indicate stack has already been initialized<br>+ test $MSR_MASK, %eax // Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)<br>+ jz SetupStack // Jump if no<br>+ or $FLAG_STACK_REENTRY, %esi // Bit25, indicate stack has already been initialized<br> <br> SetupStack:<br>- # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM<br>- mov %esi, %ebx # Get my Node/Core info<br>+ // Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM<br>+ mov %esi, %ebx // Get my Node/Core info<br> xor %bl, %bl<br>- shl $3, %bh # Isolate my node#, match alignment for PCI Dev#<br>- mov $0x8000C144, %eax # D18F1x44:DRAM Base/Limit# N is Base, N+4 is Limit<br>+ shl $3, %bh // Isolate my node#, match alignment for PCI Dev#<br>+ mov $0x8000C144, %eax // D18F1x44:DRAM Base/Limit# N is Base, N+4 is Limit<br> add %bh, %ah<br>- mov %eax, %ebx # Save PCI address for Base/Limit pair<br>+ mov %eax, %ebx // Save PCI address for Base/Limit pair<br> <br> mov $0x0CF8, %dx<br> out %eax, %dx<br> add $4, %dx<br>- xor %eax, %eax # Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)<br>- out %eax, %dx # DRAM Limit = node0, no interleave<br>+ xor %eax, %eax // Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)<br>+ out %eax, %dx // DRAM Limit = node0, no interleave<br> <br> mov %ebx, %eax<br>- sub $4, %eax # Now point to the Base register<br>+ sub $4, %eax // Now point to the Base register<br> mov $0x0CF8, %dx<br> out %eax, %dx<br> add $4, %dx<br>- mov $0x00000003, %eax # Set the read and write enable bits<br>- out %eax, %dx # DRAM Base = 0x0000, R/W<br>+ mov $0x00000003, %eax // Set the read and write enable bits<br>+ out %eax, %dx // DRAM Base = 0x0000, R/W<br> <br> AMD_ENABLE_STACK_FAMILY_HOOK<br> <br>- # Init CPU MSRs for our init routines<br>- mov $MTRR_SYS_CFG, %ecx # SYS_CFG<br>+ // Init CPU MSRs for our init routines<br>+ mov $MTRR_SYS_CFG, %ecx // SYS_CFG<br> _RDMSR<br>- bts $MTRR_FIX_DRAM_MOD_EN, %eax # Turn on modification enable bit<br>+ bts $MTRR_FIX_DRAM_MOD_EN, %eax // Turn on modification enable bit<br> _WRMSR<br> <br> mov %esi, %eax<br>- bt $FLAG_STACK_REENTRY, %eax # Is this a 2nd entry?<br>- #.if (!carry?) # On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP<br>+ bt $FLAG_STACK_REENTRY, %eax // Is this a 2nd entry?<br>+ //.if (!carry?) // On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP<br> jc 0f<br>- bt $FLAG_IS_PRIMARY, %eax # Is this core the primary in a compute unit?<br>- #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset<br>- # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores<br>- # Clear all variable and Fixed MTRRs for non-shared cores<br>+ bt $FLAG_IS_PRIMARY, %eax // Is this core the primary in a compute unit?<br>+ //.if (carry?) // Families using shared groups do not need to clear the MTRRs since that is done at power-on reset<br>+ // Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores<br>+ // Clear all variable and Fixed MTRRs for non-shared cores<br> jnc 0f<br> mov $AMD_MTRR_VARIABLE_BASE0, %ecx<br> xor %eax, %eax<br> xor %edx, %edx<br>- #.while (cl != 10h) # Variable MTRRphysBase[n] and MTRRphysMask[n]<br>+ //.while (cl != 10h) // Variable MTRRphysBase[n] and MTRRphysMask[n]<br> jmp 1f<br> 2:<br> _WRMSR<br> inc %cl<br>- #.endw<br>+ //.endw<br> 1:<br> cmp $0x10, %cl<br> jne 2b<br>- mov $AMD_MTRR_FIX64k_00000, %cx # MSR:0000_0250<br>+ mov $AMD_MTRR_FIX64k_00000, %cx // MSR:0000_0250<br> _WRMSR<br>- mov $AMD_MTRR_FIX16k_80000, %cx # MSR:0000_0258<br>+ mov $AMD_MTRR_FIX16k_80000, %cx // MSR:0000_0258<br> _WRMSR<br>- mov $AMD_MTRR_FIX16k_A0000, %cx # MSR:0000_0259<br>+ mov $AMD_MTRR_FIX16k_A0000, %cx // MSR:0000_0259<br> _WRMSR<br>- mov $AMD_MTRR_FIX4k_C0000, %cx # Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000<br>- #.while (cl != 70h)<br>+ mov $AMD_MTRR_FIX4k_C0000, %cx // Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000<br>+ //.while (cl != 70h)<br> jmp 3f<br> 4:<br> _WRMSR<br> inc %cl<br>- #.endw<br>+ //.endw<br> 3:<br> cmp $0x70, %cl<br> jne 4b<br>- # Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.<br>- # - not strictly needed since the FixedMTRRs take presedence.<br>+ // Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.<br>+ // - not strictly needed since the FixedMTRRs take presedence.<br> mov $(16 * 1024 * 1024), %eax<br>- mov $TOP_MEM, %ecx # MSR:C001_001A<br>+ mov $TOP_MEM, %ecx // MSR:C001_001A<br> _WRMSR<br>- #.endif # End Is_Primary<br>- #.endif # End Stack_ReEntry<br>+ //.endif // End Is_Primary<br>+ //.endif // End Stack_ReEntry<br> 0:<br>- # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores<br>+ // Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores<br> xor %eax, %eax<br> xor %edx, %edx<br>- mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019<br>- #.while (cl != 1Ah)<br>+ mov $IORR_BASE, %ecx // MSR:C001_0016 - 0019<br>+ //.while (cl != 1Ah)<br> jmp 1f<br> 2:<br> _WRMSR<br> inc %cl<br>- #.endw<br>+ //.endw<br> 1:<br> cmp $0x1A, %cl<br> jne 2b<br>- mov $TOP_MEM2, %ecx # MSR:C001_001D<br>+ mov $TOP_MEM2, %ecx // MSR:C001_001D<br> _WRMSR<br> <br>- # setup MTRRs for stacks<br>- # A speculative read can be generated by a speculative fetch mis-aligned in a code zone<br>- # or due to a data zone being interpreted as code. When a speculative read occurs outside a<br>- # controlled region (intentionally used by software), it could cause an unwanted cache eviction.<br>- # To prevent speculative reads from causing an eviction, the unused cache ranges are set<br>- # to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.<br>- # Note: some core stack regions will share an MTRR since the control granularity is much<br>- # larger than the allocated stack zone. The allocation algorithm must account for this 'extra'<br>- # space covered by the MTRR when parseling out cache space for the various uses. In some cases<br>- # this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c<br>- #<br>- # Outcome of this block is that: (Note the MTRR map at the top of the file)<br>- # ebp - start address of stack block<br>- # ebx - [31:16] - MTRR MSR address<br>- # - [15:8] - slot# in MTRR register<br>- # - [7:0] - block size in #4K blocks<br>- # review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)<br>- #<br>+ // setup MTRRs for stacks<br>+ // A speculative read can be generated by a speculative fetch mis-aligned in a code zone<br>+ // or due to a data zone being interpreted as code. When a speculative read occurs outside a<br>+ // controlled region (intentionally used by software), it could cause an unwanted cache eviction.<br>+ // To prevent speculative reads from causing an eviction, the unused cache ranges are set<br>+ // to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.<br>+ // Note: some core stack regions will share an MTRR since the control granularity is much<br>+ // larger than the allocated stack zone. The allocation algorithm must account for this 'extra'<br>+ // space covered by the MTRR when parseling out cache space for the various uses. In some cases<br>+ // this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c<br>+ //<br>+ // Outcome of this block is that: (Note the MTRR map at the top of the file)<br>+ // ebp - start address of stack block<br>+ // ebx - [31:16] - MTRR MSR address<br>+ // - [15:8] - slot// in MTRR register<br>+ // - [7:0] - block size in #4K blocks<br>+ // review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)<br>+ //<br> <br>- mov %si, %ax # Load node, core<br>- #.if (al == 0) # Is a core 0?<br>+ mov %si, %ax // Load node, core<br>+ //.if (al == 0) // Is a core 0?<br> or %al, %al<br> jne 1f<br>- #.if (ah == 0) # Is Node 0? (BSP)<br>+ //.if (ah == 0) // Is Node 0? (BSP)<br> or %ah, %ah<br> jne 2f<br>- # Is BSP, assign a 64K stack<br>+ // Is BSP, assign a 64K stack<br> mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx<br> mov $BSP_STACK_BASE_ADDR, %ebp<br> jmp 0f<br>- #.else # node 1 to 7, core0<br>+ //.else # node 1 to 7, core0<br> 2:<br>- # Is a Core0 of secondary node, assign 16K stacks<br>+ // Is a Core0 of secondary node, assign 16K stacks<br> mov $AMD_MTRR_FIX16k_80000, %bx<br>- shl $16, %ebx #<br>- mov %ah, %bh # Node# is used as slot#<br>+ shl $16, %ebx //<br>+ mov %ah, %bh // Node# is used as slot#<br> mov $(CORE0_STACK_SIZE >> 12), %bl<br>- mov %ah, %al # Base = (Node# * Size)#<br>- mul %bl #<br>+ mov %ah, %al // Base = (Node# * Size)#<br>+ mul %bl //<br> movzx %ax, %eax #<br>- shl $12, %eax # Expand back to full byte count (* 4K)<br>+ shl $12, %eax // Expand back to full byte count (* 4K)<br> add $CORE0_STACK_BASE_ADDR, %eax<br> mov %eax, %ebp<br>- #.endif<br>+ //.endif<br> jmp 0f<br>- #.else #core 1 thru core 7<br>+ //.else #core 1 thru core 7<br> 1:<br>- # Is core 1-7 of any node, assign 4K stacks<br>- mov $8, %al # CoreIndex = ( (Node# * 8) ...<br>- mul %ah #<br>- mov %si, %bx #<br>- add %bl, %al # ... + Core#)#<br>+ // Is core 1-7 of any node, assign 4K stacks<br>+ mov $8, %al // CoreIndex = ( (Node# * 8) ...<br>+ mul %ah //<br>+ mov %si, %bx //<br>+ add %bl, %al // ... + Core#)#<br> <br> mov $AMD_MTRR_FIX64k_00000, %bx<br>- shl $16, %ebx #<br>- mov %al, %bh # Slot# = (CoreIndex / 16) + 4#<br>- shr $4, %bh #<br>- add $4, %bh #<br>+ shl $16, %ebx //<br>+ mov %al, %bh // Slot# = (CoreIndex / 16) + 4#<br>+ shr $4, %bh //<br>+ add $4, %bh //<br> mov $(CORE1_STACK_SIZE >> 12), %bl<br> <br>- mul %bl # Base = ( (CoreIndex * Size) ...<br>- movzx %ax, %eax #<br>- shl $12, %eax # Expand back to full byte count (* 4K)<br>- add $CORE1_STACK_BASE_ADDR, %eax # ... + Base_Addr)#<br>+ mul %bl // Base = ( (CoreIndex * Size) ...<br>+ movzx %ax, %eax //<br>+ shl $12, %eax // Expand back to full byte count (* 4K)<br>+ add $CORE1_STACK_BASE_ADDR, %eax // ... + Base_Addr)#<br> mov %eax, %ebp<br>- #.endif<br>+ //.endif<br> 0:<br> <br>- # Now set the MTRR. Add this to already existing settings (don't clear any MTRR)<br>- mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot<br>- mov %bh, %cl # ShiftCount = ((slot# ...<br>- and $0x03, %cl # ... % 4) ...<br>- shl $0x03, %cl # ... * 8)#<br>- shl %cl, %edi # Cache type is now in correct position<br>- ror $16, %ebx # Get the MTRR address<br>- movzx %bx, %ecx #<br>- rol $16, %ebx # Put slot# & size back in BX<br>- _RDMSR # Read-modify-write the MSR<br>- #.if (bh < 4) # Is value in lower or upper half of MSR?<br>+ // Now set the MTRR. Add this to already existing settings (don't clear any MTRR)<br>+ mov $WB_DRAM_TYPE, %edi // Load Cache type in 1st slot<br>+ mov %bh, %cl // ShiftCount = ((slot// ...<br>+ and $0x03, %cl // ... % 4) ...<br>+ shl $0x03, %cl // ... * 8)#<br>+ shl %cl, %edi // Cache type is now in correct position<br>+ ror $16, %ebx // Get the MTRR address<br>+ movzx %bx, %ecx //<br>+ rol $16, %ebx // Put slot# & size back in BX<br>+ _RDMSR // Read-modify-write the MSR<br>+ //.if (bh < 4) // Is value in lower or upper half of MSR?<br> cmp $4, %bh<br> jae 1f<br>- or %edi, %eax #<br>+ or %edi, %eax<br> jmp 0f<br>- #.else<br>- 1: #<br>- or %edi, %edx #<br>- #.endif #<br>+ //.else<br>+ 1:<br>+ or %edi, %edx<br>+ //.endif<br> 0:<br>- _WRMSR #<br>-<br>- # Enable MTRR defaults as UC type<br>- mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF<br>- _RDMSR # Read-modify-write the MSR<br>- bts $MTRR_DEF_TYPE_EN, %eax # MtrrDefTypeEn<br>- bts $MTRR_DEF_TYPE_FIX_EN, %eax # MtrrDefTypeFixEn<br> _WRMSR<br> <br>- # Close the modification window on the Fixed MTRRs<br>- mov $MTRR_SYS_CFG, %ecx # MSR:0C001_0010<br>+ // Enable MTRR defaults as UC type<br>+ mov $AMD_MTRR_DEFTYPE, %ecx // MSR:0000_02FF<br>+ _RDMSR // Read-modify-write the MSR<br>+ bts $MTRR_DEF_TYPE_EN, %eax // MtrrDefTypeEn<br>+ bts $MTRR_DEF_TYPE_FIX_EN, %eax // MtrrDefTypeFixEn<br>+ _WRMSR<br>+<br>+ // Close the modification window on the Fixed MTRRs<br>+ mov $MTRR_SYS_CFG, %ecx // MSR:0C001_0010<br> _RDMSR<br>- bts $MTRR_FIX_DRAM_EN, %eax # MtrrFixDramEn<br>- bts $MTRR_VAR_DRAM_EN, %eax # variable MTRR enable bit<br>- btr $MTRR_FIX_DRAM_MOD_EN, %eax # Turn off modification enable bit<br>+ bts $MTRR_FIX_DRAM_EN, %eax // MtrrFixDramEn<br>+ bts $MTRR_VAR_DRAM_EN, %eax // variable MTRR enable bit<br>+ btr $MTRR_FIX_DRAM_MOD_EN, %eax // Turn off modification enable bit<br> _WRMSR<br> <br>- # Enable caching in CR0<br>- mov %cr0, %eax # Enable WT/WB cache<br>- btr $CR0_PG, %eax # Make sure paging is disabled<br>- btr $CR0_CD, %eax # Clear CR0 NW and CD<br>- btr $CR0_NW, %eax<br>+ // Enable caching in CR0<br>+ mov %cr0, %eax // Enable WT/WB cache<br>+ btr $CR0_PG_BIT, %eax // Make sure paging is disabled<br>+ btr $CR0_CD_BIT, %eax // Clear CR0 NW and CD<br>+ btr $CR0_NW_BIT, %eax<br> mov %eax, %cr0<br> <br>- # Use the Stack Base & size to calculate SS and ESP values<br>- # review:<br>- # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)<br>- # ebp - start address of stack block<br>- # ebx - [31:16] - MTRR MSR address<br>- # - [15:8] - slot# in MTRR register<br>- # - [7:0] - block size in #4K blocks<br>- #<br>- mov %ebp, %esp # Initialize the stack pointer<br>- mov %esp, %edi # Copy the stack start to edi<br>+ // Use the Stack Base & size to calculate SS and ESP values<br>+ // review:<br>+ // esi[31:24]=Flags; esi[15,8]= Node//; esi[7,0]= core# (relative to node)<br>+ // ebp - start address of stack block<br>+ // ebx - [31:16] - MTRR MSR address<br>+ // - [15:8] - slot# in MTRR register<br>+ // - [7:0] - block size in #4K blocks<br>+ //<br>+ mov %ebp, %esp // Initialize the stack pointer<br>+ mov %esp, %edi // Copy the stack start to edi<br> movzx %bl, %bx<br>- movzx %bx, %ebx # Clear upper ebx, don't need MSR addr anymore<br>- shl $12, %ebx # Make size full byte count (* 4K)<br>- add %ebx, %esp # Set the Stack Pointer as full linear address<br>+ movzx %bx, %ebx // Clear upper ebx, don't need MSR addr anymore<br>+ shl $12, %ebx // Make size full byte count (* 4K)<br>+ add %ebx, %esp // Set the Stack Pointer as full linear address<br> sub $4, %esp<br>- #<br>- # review:<br>- # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)<br>- # edi - 32b start address of stack block<br>- # ebx - size of stack block<br>- # esp - 32b linear stack pointer<br>- #<br>+ //<br>+ // review:<br>+ // esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)<br>+ // edi - 32b start address of stack block<br>+ // ebx - size of stack block<br>+ // esp - 32b linear stack pointer<br>+ //<br> <br>- # Determine mode for SS base;<br>- mov %cr0, %ecx # Check for 32-bit protect mode<br>- bt $CR0_PE, %ecx #<br>- #.if (!carry?) # PE=0 means real mode<br>+ // Determine mode for SS base;<br>+ mov %cr0, %ecx // Check for 32-bit protect mode<br>+ bt $CR0_PE_BIT, %ecx //<br>+ //.if (!carry?) // PE=0 means real mode<br> jc Protected32Mode<br>- mov %cs, %cx # PE=1<br>- cmp $0x0D000, %cx # Check for CS<br>- jb Protected32Mode # If CS < D000, it is a selector instead of a segment<br>- # alter SS:ESP for 16b Real Mode:<br>+ mov %cs, %cx // PE=1<br>+ cmp $0x0D000, %cx // Check for CS<br>+ jb Protected32Mode // If CS < D000, it is a selector instead of a segment<br>+ // alter SS:ESP for 16b Real Mode:<br> Real16bMode:<br> mov %edi, %eax<br>- shr $4, %eax # Create a Real Mode segment for ss, ds, es<br>+ shr $4, %eax // Create a Real Mode segment for ss, ds, es<br> mov %ax, %ss<br> mov %ax, %ds<br> mov %ax, %es<br> shl $4, %eax<br>- sub %eax, %edi # Adjust the clearing pointer for Seg:Offset mode<br>- mov %ebx, %esp # Make SP an offset from SS<br>- sub $4, %esp #<br>- # .endif # endif<br>- # #else<br>- # Default is to use Protected 32b Mode<br>- #.endif<br>+ sub %eax, %edi // Adjust the clearing pointer for Seg:Offset mode<br>+ mov %ebx, %esp // Make SP an offset from SS<br>+ sub $4, %esp<br>+ // .endif // endif<br>+ // //else<br>+ // Default is to use Protected 32b Mode<br>+ //.endif<br> ;<br> Protected32Mode:<br>- #<br>- # Clear The Stack<br>- # Now that we have set the location and the MTRRs, initialize the cache by<br>- # reading then writing to zero all of the stack area.<br>- # review:<br>- # ss - Stack base<br>- # esp - stack pointer<br>- # ebx - size of stack block<br>- # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)<br>- # edi - address of start of stack block<br>- #<br>+ //<br>+ // Clear The Stack<br>+ // Now that we have set the location and the MTRRs, initialize the cache by<br>+ // reading then writing to zero all of the stack area.<br>+ // review:<br>+ // ss - Stack base<br>+ // esp - stack pointer<br>+ // ebx - size of stack block<br>+ // esi[31:24]=Flags; esi[15,8]= Node//; esi[7,0]= core# (relative to node)<br>+ // edi - address of start of stack block<br>+ //<br> <br>-ClearTheStack: # Stack base is in SS, stack pointer is in ESP<br>- shr $2, %ebx # ebx = stack block size in dwords<br>- mov %bx, %cx #<br>- # Check our flags - Don't clear an existing stack<br>- #.if ( !(esi & 0FF000000h)) # Check our flags<br>+ClearTheStack: // Stack base is in SS, stack pointer is in ESP<br>+ shr $2, %ebx // ebx = stack block size in dwords<br>+ mov %bx, %cx //<br>+ // Check our flags - Don't clear an existing stack<br>+ //.if ( !(esi & 0FF000000h)) // Check our flags<br> test $(1 << FLAG_STACK_REENTRY), %esi<br> jne 1f<br> cld<br> mov %edi, %esi<br>- rep lodsl (%esi) # Pre-load the range<br>+ rep lodsl (%esi) // Pre-load the range<br> xor %eax, %eax<br> mov %bx, %cx<br>- mov %edi, %esi # Preserve base for push on stack<br>- rep stosl (%edi) # Clear the range<br>- movl $0x0ABCDDCBA, (%esp) # Put marker in top stack dword<br>- shl $2, %ebx # Put stack size and base<br>- push %ebx # in top of stack<br>+ mov %edi, %esi // Preserve base for push on stack<br>+ rep stosl (%edi) // Clear the range<br>+ movl $0x0ABCDDCBA, (%esp) // Put marker in top stack dword<br>+ shl $2, %ebx // Put stack size and base<br>+ push %ebx // in top of stack<br> push %esi<br> <br>- mov %ebx, %ecx # Return size of stack in bytes<br>- xor %eax, %eax # eax = 0 : no error return code<br>+ mov %ebx, %ecx // Return size of stack in bytes<br>+ xor %eax, %eax // eax = 0 : no error return code<br> jmp 0f<br>- #.else<br>+ //.else<br> 1:<br> movzx %cx, %ecx<br>- shl $2, %ecx # Return size of stack in bytes<br>+ shl $2, %ecx // Return size of stack in bytes<br> mov %esi, %eax<br>- shr $24, %eax # Keep the flags as part of the error report<br>- or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)<br>- #.endif<br>+ shr $24, %eax // Keep the flags as part of the error report<br>+ or $0x40000000, %eax // eax = AGESA_WARNING (Stack has already been set up)<br>+ //.endif<br> 0:<br> .endm<br> <br>@@ -1922,29 +1931,29 @@<br> *****************************************************************************/<br> .macro AMD_DISABLE_STACK<br> <br>- # get node/core/flags of current executing core<br>- GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)<br>+ // get node/core/flags of current executing core<br>+ GET_NODE_ID_CORE_ID // Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)<br> <br>- # Turn on modification enable bit<br>- mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010<br>+ // Turn on modification enable bit<br>+ mov $MTRR_SYS_CFG, %ecx // MSR:C001_0010<br> _RDMSR<br>- bts $MTRR_FIX_DRAM_MOD_EN, %eax # Enable modifications<br>+ bts $MTRR_FIX_DRAM_MOD_EN, %eax // Enable modifications<br> _WRMSR<br> <br>- # Set lower 640K MTRRs for Write-Back memory caching<br>+ // Set lower 640K MTRRs for Write-Back memory caching<br> mov $AMD_MTRR_FIX64k_00000, %ecx<br> mov $0x1E1E1E1E, %eax<br> mov %eax, %edx<br>- _WRMSR # 0 - 512K = WB Mem<br>+ _WRMSR // 0 - 512K = WB Mem<br> mov $AMD_MTRR_FIX16k_80000, %ecx<br>- _WRMSR # 512K - 640K = WB Mem<br>+ _WRMSR // 512K - 640K = WB Mem<br> <br>- # Turn off modification enable bit<br>- mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010<br>+ // Turn off modification enable bit<br>+ mov $MTRR_SYS_CFG, %ecx // MSR:C001_0010<br> _RDMSR<br>- btr $MTRR_FIX_DRAM_MOD_EN, %eax # Disable modification<br>+ btr $MTRR_FIX_DRAM_MOD_EN, %eax // Disable modification<br> _WRMSR<br> <br>- AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations<br>+ AMD_DISABLE_STACK_FAMILY_HOOK // Re-Enable 'normal' cache operations<br> <br> .endm<br></pre><p>To view, visit <a href="https://review.coreboot.org/21362">change 21362</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I3cf3f117f0f56e45f9008f787618800584de6c46 </div>
<div style="display:none"> Gerrit-Change-Number: 21362 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Damien Zammit <damien@zamaudio.com> </div>