<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21292">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/asrock/g41c-gs: Add the revision 1 variant<br><br>Both g41c-gs and g41c-s can be supported by the same code since the<br>only difference is ethernet NIC.<br><br>UNTESTED<br><br>Change-Id: Ib69c2ac0a9dc1b5c46220d2d2d5239edc99b0516<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/asrock/g41c-gs/Kconfig<br>M src/mainboard/asrock/g41c-gs/Kconfig.name<br>M src/mainboard/asrock/g41c-gs/Makefile.inc<br>M src/mainboard/asrock/g41c-gs/romstage.c<br>A src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb<br>A src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb<br>6 files changed, 316 insertions(+), 13 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/21292/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/asrock/g41c-gs/Kconfig b/src/mainboard/asrock/g41c-gs/Kconfig<br>index e65f4ee..7d0b781 100644<br>--- a/src/mainboard/asrock/g41c-gs/Kconfig<br>+++ b/src/mainboard/asrock/g41c-gs/Kconfig<br>@@ -14,7 +14,7 @@<br> # GNU General Public License for more details.<br> #<br> <br>-if BOARD_ASROCK_G41C_GS_R2_0<br>+if BOARD_ASROCK_G41C_GS_R2_0 || BOARD_ASROCK_G41C_GS<br> <br> config BOARD_SPECIFIC_OPTIONS<br> def_bool y<br>@@ -22,7 +22,8 @@<br> select CPU_INTEL_SOCKET_LGA775<br> select NORTHBRIDGE_INTEL_X4X<br> select SOUTHBRIDGE_INTEL_I82801GX<br>- select SUPERIO_NUVOTON_NCT6776<br>+ select SUPERIO_NUVOTON_NCT6776 if BOARD_ASROCK_G41C_GS_R2_0<br>+ select SUPERIO_WINBOND_W83627DHG if BOARD_ASROCK_G41C_GS<br> select HAVE_ACPI_TABLES<br> select BOARD_ROMSIZE_KB_1024<br> select INTEL_EDID<br>@@ -41,7 +42,13 @@<br> <br> config MAINBOARD_PART_NUMBER<br> string<br>- default "G41C-GS R2.0"<br>+ default "G41C-GS R2.0" if BOARD_ASROCK_G41C_GS_R2_0<br>+ default "G41C-GS" if BOARD_ASROCK_G41C_GS<br>+<br>+config DEVICETREE<br>+ string<br>+ default "variants/g41c-gs-r2/devicetree.cb" if BOARD_ASROCK_G41C_GS_R2_0<br>+ default "variants/g41c-gs/devicetree.cb" if BOARD_ASROCK_G41C_GS<br> <br> config MAX_CPUS<br> int<br>diff --git a/src/mainboard/asrock/g41c-gs/Kconfig.name b/src/mainboard/asrock/g41c-gs/Kconfig.name<br>index 5cf5887..5ce5aa7 100644<br>--- a/src/mainboard/asrock/g41c-gs/Kconfig.name<br>+++ b/src/mainboard/asrock/g41c-gs/Kconfig.name<br>@@ -1,2 +1,5 @@<br> config BOARD_ASROCK_G41C_GS_R2_0<br> bool "G41C-GS R2.0"<br>+<br>+config BOARD_ASROCK_G41C_GS<br>+ bool "G41C-GS / G41C-S"<br>diff --git a/src/mainboard/asrock/g41c-gs/Makefile.inc b/src/mainboard/asrock/g41c-gs/Makefile.inc<br>index f3d7e76..f533c40 100644<br>--- a/src/mainboard/asrock/g41c-gs/Makefile.inc<br>+++ b/src/mainboard/asrock/g41c-gs/Makefile.inc<br>@@ -1,2 +1,2 @@<br> ramstage-y += cstates.c<br>-romstage-y += gpio.c<br>+romstage-y += gpio.c<br>\ No newline at end of file<br>diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c<br>index dd885db..07edfb4 100644<br>--- a/src/mainboard/asrock/g41c-gs/romstage.c<br>+++ b/src/mainboard/asrock/g41c-gs/romstage.c<br>@@ -22,6 +22,8 @@<br> #include <cpu/x86/bist.h><br> #include <cpu/intel/romstage.h><br> #include <superio/nuvoton/nct6776/nct6776.h><br>+#include <superio/winbond/w83627dhg/w83627dhg.h><br>+#include <superio/winbond/common/winbond.h><br> #include <superio/nuvoton/common/nuvoton.h><br> #include <lib.h><br> #include <arch/stages.h><br>@@ -30,7 +32,8 @@<br> #include <device/pnp_def.h><br> #include <timestamp.h><br> <br>-#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)<br>+#define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1)<br>+#define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1)<br> #define SUPERIO_DEV PNP_DEV(0x2e, 0)<br> #define LPC_DEV PCI_DEV(0, 0x1f, 0)<br> <br>@@ -44,15 +47,19 @@<br> setup_pch_gpios(&mainboard_gpio_map);<br> <br> /* Set GPIOs on superio, enable UART */<br>- nuvoton_pnp_enter_conf_state(SERIAL_DEV);<br>- pnp_set_logical_device(SERIAL_DEV);<br>+ if (IS_ENABLED(CONFIG_BOARD_ASROCK_G41C_GS_R2_0)) {<br>+ nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2);<br>+ pnp_set_logical_device(SERIAL_DEV_R2);<br> <br>- pnp_write_config(SERIAL_DEV, 0x1c, 0x80);<br>- pnp_write_config(SERIAL_DEV, 0x27, 0x80);<br>- pnp_write_config(SERIAL_DEV, 0x2a, 0x60);<br>+ pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80);<br>+ pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80);<br>+ pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60);<br> <br>- nuvoton_pnp_exit_conf_state(SERIAL_DEV);<br>-<br>+ nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2);<br>+ nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE);<br>+ } else { /* BOARD_ASROCK_G41C_GS */<br>+ winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE);<br>+ }<br> /* IRQ routing */<br> RCBA16(D31IR) = 0x0132;<br> RCBA16(D29IR) = 0x0237;<br>@@ -93,7 +100,6 @@<br> /* Set southbridge and Super I/O GPIOs. */<br> ich7_enable_lpc();<br> mb_lpc_setup();<br>- nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br> <br> console_init();<br> <br>diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb<br>new file mode 100644<br>index 0000000..fd7f271<br>--- /dev/null<br>+++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb<br>@@ -0,0 +1,149 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz><br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; either version 2 of the License, or<br>+# (at your option) any later version.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+chip northbridge/intel/x4x # Northbridge<br>+ device cpu_cluster 0 on # APIC cluster<br>+ chip cpu/intel/socket_LGA775<br>+ device lapic 0 on end<br>+ end<br>+ chip cpu/intel/model_1067x # CPU<br>+ device lapic 0xACAC off end<br>+ end<br>+ end<br>+ device domain 0 on # PCI domain<br>+ subsystemid 0x1458 0x5000 inherit<br>+ device pci 0.0 on # Host Bridge<br>+ subsystemid 0x1849 0x2e30<br>+ end<br>+ device pci 1.0 on end # PEG<br>+<br>+ device pci 2.0 on # Integrated graphics controller<br>+ subsystemid 0x1849 0x2e32<br>+ end<br>+ device pci 3.0 off end # ME<br>+ device pci 3.1 off end # ME<br>+ chip southbridge/intel/i82801gx # Southbridge<br>+ register "pirqa_routing" = "0x0b"<br>+ register "pirqb_routing" = "0x0b"<br>+ register "pirqc_routing" = "0x0b"<br>+ register "pirqd_routing" = "0x0b"<br>+ register "pirqe_routing" = "0x80"<br>+ register "pirqf_routing" = "0x80"<br>+ register "pirqg_routing" = "0x80"<br>+ register "pirqh_routing" = "0x0b"<br>+ # GPI routing<br>+ # 0 No effect (default)<br>+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)<br>+ # 2 SCI (if corresponding GPIO_EN bit is also set)<br>+ register "gpi13_routing" = "2"<br>+<br>+ register "ide_enable_primary" = "0x1"<br>+ register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant<br>+ register "sata_ports_implemented" = "0x3"<br>+ register "gpe0_en" = "0x440"<br>+<br>+ device pci 1b.0 on # Audio<br>+ subsystemid 0x1849 0x3662<br>+ end<br>+ device pci 1c.0 on end # PCIe 1<br>+ device pci 1c.1 on end # PCIe 2<br>+ device pci 1c.2 off end # PCIe 3<br>+ device pci 1c.3 off end # PCIe 4<br>+ device pci 1d.0 on # USB<br>+ subsystemid 0x1849 0x27c8<br>+ end<br>+ device pci 1d.1 on # USB<br>+ subsystemid 0x1849 0x27c9<br>+ end<br>+ device pci 1d.2 on # USB<br>+ subsystemid 0x1849 0x27ca<br>+ end<br>+ device pci 1d.3 on # USB<br>+ subsystemid 0x1849 0x27cb<br>+ end<br>+ device pci 1d.7 on # USB<br>+ subsystemid 0x1849 0x27cc<br>+ end<br>+ device pci 1e.0 on end # PCI bridge<br>+ device pci 1f.0 on # ISA bridge<br>+ subsystemid 0x1849 0x27b8<br>+ chip superio/nuvoton/nct6776<br>+ device pnp 2e.0 off end # Floppy<br>+ device pnp 2e.1 on # Parallel port<br>+ # global<br>+ irq 0x1c = 0x80<br>+ irq 0x27 = 0x80<br>+ irq 0x2a = 0x60<br>+ # parallel port<br>+ io 0x60 = 0x378<br>+ irq 0x70 = 7<br>+ drq 0x74 = 3<br>+ end<br>+ device pnp 2e.2 on # COM1<br>+ io 0x60 = 0x3f8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 2e.3 off end # COM2, IR<br>+ device pnp 2e.5 on # Keyboard<br>+ io 0x60 = 0x60<br>+ io 0x62 = 0x64<br>+ irq 0x70 = 1<br>+ end<br>+ device pnp 2e.6 on # CIR<br>+ io 0x60 = 0x230<br>+ irq 0x70 = 3<br>+ end<br>+ device pnp 2e.7 off end # GPIO6-9<br>+ device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA<br>+ device pnp 2e.9 off end # GPIO2-5<br>+ device pnp 2e.a on # ACPI<br>+ irq 0xe0 = 0x03<br>+ irq 0xe4 = 0x10 # Power dram during s3<br>+ irq 0xe6 = 0x4c<br>+ irq 0xe9 = 0x02<br>+ irq 0xf0 = 0x20<br>+ end<br>+ device pnp 2e.b on # HWM, front pannel LED<br>+ io 0x60 = 0x290<br>+ io 0x62 = 0x200<br>+ irq 0x70 = 0<br>+ end<br>+ device pnp 2e.d on end # VID<br>+ device pnp 2e.e on # CIR WAKE-UP<br>+ io 0x60 = 0x240<br>+ irq 0x70 = 0<br>+ end<br>+ device pnp 2e.f on end # GPIO Push-Pull or Open-drain<br>+ device pnp 2e.14 on end # SVID<br>+ device pnp 2e.16 on end # Deep Sleep<br>+ device pnp 2e.17 on end # GPIOA<br>+ end<br>+ end<br>+ device pci 1f.1 on # PATA/IDE<br>+ subsystemid 0x1849 0x27df<br>+ end<br>+ device pci 1f.2 on # SATA<br>+ subsystemid 0x1849 0x27c0<br>+ end<br>+ device pci 1f.3 on # SMbus<br>+ subsystemid 0x1849 0x27da<br>+ end<br>+ device pci 1f.4 off end<br>+ device pci 1f.5 off end<br>+ device pci 1f.6 off end<br>+ end<br>+ end<br>+end<br>diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb<br>new file mode 100644<br>index 0000000..4b4cb2a<br>--- /dev/null<br>+++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb<br>@@ -0,0 +1,138 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2017 Arthur Heymans <arthur@aheymans.xyz><br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; either version 2 of the License, or<br>+# (at your option) any later version.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+chip northbridge/intel/x4x # Northbridge<br>+ device cpu_cluster 0 on # APIC cluster<br>+ chip cpu/intel/socket_LGA775<br>+ device lapic 0 on end<br>+ end<br>+ chip cpu/intel/model_1067x # CPU<br>+ device lapic 0xACAC off end<br>+ end<br>+ end<br>+ device domain 0 on # PCI domain<br>+ subsystemid 0x1458 0x5000 inherit<br>+ device pci 0.0 on # Host Bridge<br>+ subsystemid 0x1849 0x2e30<br>+ end<br>+ device pci 1.0 on end # PEG<br>+<br>+ device pci 2.0 on # Integrated graphics controller<br>+ subsystemid 0x1849 0x2e32<br>+ end<br>+ device pci 3.0 off end # ME<br>+ device pci 3.1 off end # ME<br>+ chip southbridge/intel/i82801gx # Southbridge<br>+ register "pirqa_routing" = "0x0b"<br>+ register "pirqb_routing" = "0x0b"<br>+ register "pirqc_routing" = "0x0b"<br>+ register "pirqd_routing" = "0x0b"<br>+ register "pirqe_routing" = "0x80"<br>+ register "pirqf_routing" = "0x80"<br>+ register "pirqg_routing" = "0x80"<br>+ register "pirqh_routing" = "0x0b"<br>+ # GPI routing<br>+ # 0 No effect (default)<br>+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)<br>+ # 2 SCI (if corresponding GPIO_EN bit is also set)<br>+ register "gpi13_routing" = "2"<br>+<br>+ register "ide_enable_primary" = "0x1"<br>+ register "sata_ahci" = "0x0" # AHCI not supported on this ICH7 variant<br>+ register "sata_ports_implemented" = "0x3"<br>+ register "gpe0_en" = "0x440"<br>+<br>+ device pci 1b.0 on # Audio<br>+ subsystemid 0x1849 0x3662<br>+ end<br>+ device pci 1c.0 on end # PCIe 1<br>+ device pci 1c.1 on end # PCIe 2<br>+ device pci 1c.2 off end # PCIe 3<br>+ device pci 1c.3 off end # PCIe 4<br>+ device pci 1d.0 on # USB<br>+ subsystemid 0x1849 0x27c8<br>+ end<br>+ device pci 1d.1 on # USB<br>+ subsystemid 0x1849 0x27c9<br>+ end<br>+ device pci 1d.2 on # USB<br>+ subsystemid 0x1849 0x27ca<br>+ end<br>+ device pci 1d.3 on # USB<br>+ subsystemid 0x1849 0x27cb<br>+ end<br>+ device pci 1d.7 on # USB<br>+ subsystemid 0x1849 0x27cc<br>+ end<br>+ device pci 1e.0 on end # PCI bridge<br>+ device pci 1f.0 on # ISA bridge<br>+ subsystemid 0x1849 0x27b8<br>+ chip superio/nuvoton/nct6776<br>+ device pnp 2e.0 off end # Floppy<br>+ device pnp 2e.1 on # Parallel port<br>+ # global<br>+ irq 0x28 = 0x70<br>+ irq 0x2c = 0xd2<br>+ # parallel port<br>+ io 0x60 = 0x378<br>+ irq 0x70 = 7<br>+ drq 0x74 = 3<br>+ end<br>+ device pnp 2e.2 on # COM1<br>+ io 0x60 = 0x3f8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 2e.3 off end # COM2<br>+ device pnp 2e.5 on # Keyboard & MOUSE<br>+ io 0x60 = 0x60<br>+ io 0x62 = 0x64<br>+ irq 0x70 = 1<br>+ irq 0x72 = 0x0C<br>+ end<br>+ device pnp 2e.6 off end # SPI<br>+ device pnp 2e.7 off end # GPIO6<br>+ device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA<br>+ device pnp 2e.9 off end # GPIO2<br>+ device pnp 2e.109 off end # GPIO3<br>+ device pnp 2e.209 on # GPIO4<br>+ irq 0xf4 = 0x73<br>+ end<br>+ device pnp 2e.309 off end # GPIO5<br>+ device pnp 2e.a on # ACPI<br>+ irq 0xe4 = 0x10 # Power dram during s3<br>+ end<br>+ device pnp 2e.b on # HWM, front pannel LED<br>+ io 0x60 = 0x290<br>+ irq 0x70 = 0<br>+ end<br>+ device pnp 2e.c off end # PECI, SST<br>+ end<br>+ end<br>+ device pci 1f.1 on # PATA/IDE<br>+ subsystemid 0x1849 0x27df<br>+ end<br>+ device pci 1f.2 on # SATA<br>+ subsystemid 0x1849 0x27c0<br>+ end<br>+ device pci 1f.3 on # SMbus<br>+ subsystemid 0x1849 0x27da<br>+ end<br>+ device pci 1f.4 off end<br>+ device pci 1f.5 off end<br>+ device pci 1f.6 off end<br>+ end<br>+ end<br>+end<br></pre><p>To view, visit <a href="https://review.coreboot.org/21292">change 21292</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21292"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib69c2ac0a9dc1b5c46220d2d2d5239edc99b0516 </div>
<div style="display:none"> Gerrit-Change-Number: 21292 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>