<p>Pratikkumar V Prajapati has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21272">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Define Max PCIE Root Ports<br><br>This patch defines Max PCIE Root Ports and fixes<br>bellow Coverity scan defect,<br><br>*** CID 1380036:  Control flow issues  (NO_EFFECT)<br>/src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params()<br>79<br>>>>     CID 1380036:  Control flow issues  (NO_EFFECT)<br>>>>     "i" is converted to an unsigned type because it's compared to an unsigned constant.<br>80      for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {<br>81              if (config->PcieRpEnable[i])<br>82                      mask |= (1 << i);<br><br>Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e<br>Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/romstage/romstage.c<br>2 files changed, 5 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/21272/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig<br>index 65b581e..cf0a534 100644<br>--- a/src/soc/intel/cannonlake/Kconfig<br>+++ b/src/soc/intel/cannonlake/Kconfig<br>@@ -89,6 +89,10 @@<br>     hex<br>   default 0x400000<br> <br>+config MAX_ROOT_PORTS<br>+  int<br>+  default 24<br>+<br> config SMM_TSEG_SIZE<br>  hex<br>   default 0x800000<br>diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c<br>index 17c3191..74a2abc 100644<br>--- a/src/soc/intel/cannonlake/romstage/romstage.c<br>+++ b/src/soc/intel/cannonlake/romstage/romstage.c<br>@@ -68,7 +68,7 @@<br> <br> static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)<br> {<br>-        int i;<br>+       uint8_t i;<br>    uint32_t mask = 0;<br> <br>         m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE;<br></pre><p>To view, visit <a href="https://review.coreboot.org/21272">change 21272</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21272"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e </div>
<div style="display:none"> Gerrit-Change-Number: 21272 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>