<p>Nick Vaccaro has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21273">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">google/zoombini: Add new board<br><br>Add zoombini board files using cannonlake and FSP 2.0.<br><br>BUG=b:64395641<br>BRANCH=None<br>TEST=None<br><br>Change-Id: I13ebaae403d08f1b2e6881eeba4dc1787c792b4e<br>Signed-off-by: Nick Vaccaro <nvaccaro@google.com><br>---<br>A src/mainboard/google/zoombini/Kconfig<br>A src/mainboard/google/zoombini/Kconfig.name<br>A src/mainboard/google/zoombini/Makefile.inc<br>A src/mainboard/google/zoombini/acpi/ec.asl<br>A src/mainboard/google/zoombini/acpi/superio.asl<br>A src/mainboard/google/zoombini/acpi_tables.c<br>A src/mainboard/google/zoombini/board_info.txt<br>A src/mainboard/google/zoombini/boardid.c<br>A src/mainboard/google/zoombini/bootblock.c<br>A src/mainboard/google/zoombini/chromeos.c<br>A src/mainboard/google/zoombini/chromeos.fmd<br>A src/mainboard/google/zoombini/ec.c<br>A src/mainboard/google/zoombini/ramstage.c<br>A src/mainboard/google/zoombini/romstage.c<br>A src/mainboard/google/zoombini/smihandler.c<br>A src/mainboard/google/zoombini/variants/baseboard/Makefile.inc<br>A src/mainboard/google/zoombini/variants/baseboard/boardid.c<br>A src/mainboard/google/zoombini/variants/baseboard/devicetree.cb<br>A src/mainboard/google/zoombini/variants/baseboard/gpio.c<br>A src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h<br>A src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h<br>A src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h<br>A src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>25 files changed, 982 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/21273/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/zoombini/Kconfig b/src/mainboard/google/zoombini/Kconfig<br>new file mode 100644<br>index 0000000..22502cd<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/Kconfig<br>@@ -0,0 +1,78 @@<br>+if BOARD_GOOGLE_ZOOMBINI<br>+<br>+config BOARD_SPECIFIC_OPTIONS<br>+ def_bool y<br>+ select BOARD_ID_AUTO<br>+ select BOARD_ROMSIZE_KB_16384<br>+ select DRIVERS_I2C_GENERIC<br>+ select EC_GOOGLE_CHROMEEC<br>+ select EC_GOOGLE_CHROMEEC_LPC<br>+ select MAINBOARD_HAS_CHROMEOS<br>+ select SOC_INTEL_CANNONLAKE<br>+<br>+config CHROMEOS<br>+ select EC_GOOGLE_CHROMEEC_SWITCHES<br>+<br>+config DEVICETREE<br>+ string<br>+ default "variants/baseboard/devicetree.cb"<br>+<br>+config DRIVER_TPM_I2C_BUS<br>+ depends on ZOOMBINI_USE_I2C_TPM<br>+ default 0x1<br>+<br>+config DRIVER_TPM_I2C_ADDR<br>+ depends on ZOOMBINI_USE_I2C_TPM<br>+ default 0x50<br>+<br>+config DRIVER_TPM_SPI_BUS<br>+ depends on ZOOMBINI_USE_SPI_TPM<br>+ default 0x1<br>+<br>+config GBB_HWID<br>+ string<br>+ depends on CHROMEOS<br>+ default "ZOOMBINI TEST 5722" if BOARD_GOOGLE_ZOOMBINI<br>+<br>+config MAINBOARD_DIR<br>+ string<br>+ default "google/zoombini"<br>+<br>+config MAINBOARD_FAMILY<br>+ string<br>+ default "Google_Zoombini" if BOARD_GOOGLE_ZOOMBINI<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "Zoombini" if BOARD_GOOGLE_ZOOMBINI<br>+<br>+config MAINBOARD_VENDOR<br>+ string<br>+ default "Google"<br>+<br>+config VARIANT_DIR<br>+ string<br>+ default "zoombini" if BOARD_GOOGLE_ZOOMBINI<br>+<br>+config VBOOT<br>+ select VBOOT_SEPARATE_VERSTAGE<br>+ select VBOOT_STARTS_IN_BOOTBLOCK<br>+ select VBOOT_LID_SWITCH<br>+<br>+# Select this option to enable use of cr50 I2C TPM on zoombini.<br>+config ZOOMBINI_USE_I2C_TPM<br>+ bool<br>+ default n<br>+ select I2C_TPM<br>+ select MAINBOARD_HAS_I2C_TPM_CR50<br>+ select TPM2<br>+<br>+# Select this option to enable use of cr50 SPI TPM on zoombini.<br>+config ZOOMBINI_USE_SPI_TPM<br>+ bool<br>+ default y<br>+ select MAINBOARD_HAS_SPI_TPM_CR50<br>+ select SPI_TPM<br>+ select TPM2<br>+<br>+endif # BOARD_GOOGLE_ZOOMBINI<br>diff --git a/src/mainboard/google/zoombini/Kconfig.name b/src/mainboard/google/zoombini/Kconfig.name<br>new file mode 100644<br>index 0000000..da038f6<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_GOOGLE_ZOOMBINI<br>+ bool "Zoombini"<br>diff --git a/src/mainboard/google/zoombini/Makefile.inc b/src/mainboard/google/zoombini/Makefile.inc<br>new file mode 100644<br>index 0000000..97f0173<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/Makefile.inc<br>@@ -0,0 +1,37 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2017 Google Inc.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+bootblock-y += bootblock.c<br>+bootblock-$(CONFIG_CHROMEOS) += chromeos.c<br>+<br>+verstage-$(CONFIG_CHROMEOS) += chromeos.c<br>+<br>+romstage-y += boardid.c<br>+romstage-$(CONFIG_CHROMEOS) += chromeos.c<br>+romstage-y += romstage.c<br>+<br>+ramstage-y += boardid.c<br>+ramstage-$(CONFIG_CHROMEOS) += chromeos.c<br>+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c<br>+<br>+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c<br>+<br>+subdirs-y += variants/baseboard<br>+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include<br>+<br>+subdirs-y += variants/$(VARIANT_DIR)<br>+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include<br>+<br>+<br>diff --git a/src/mainboard/google/zoombini/acpi/ec.asl b/src/mainboard/google/zoombini/acpi/ec.asl<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/acpi/ec.asl<br>diff --git a/src/mainboard/google/zoombini/acpi/superio.asl b/src/mainboard/google/zoombini/acpi/superio.asl<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/acpi/superio.asl<br>diff --git a/src/mainboard/google/zoombini/acpi_tables.c b/src/mainboard/google/zoombini/acpi_tables.c<br>new file mode 100644<br>index 0000000..e69de29<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/acpi_tables.c<br>diff --git a/src/mainboard/google/zoombini/board_info.txt b/src/mainboard/google/zoombini/board_info.txt<br>new file mode 100644<br>index 0000000..3ed5a7e<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/board_info.txt<br>@@ -0,0 +1,6 @@<br>+Vendor name: Google<br>+Board name: Zoombini Cannonlake Reference Board<br>+Category: laptop<br>+ROM protocol: SPI<br>+ROM socketed: n<br>+Flashrom support: y<br>diff --git a/src/mainboard/google/zoombini/boardid.c b/src/mainboard/google/zoombini/boardid.c<br>new file mode 100644<br>index 0000000..bd9afde<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/boardid.c<br>@@ -0,0 +1,28 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <baseboard/variants.h><br>+#include <boardid.h><br>+#include <stddef.h><br>+<br>+uint8_t board_id(void)<br>+{<br>+ MAYBE_STATIC int id = -1;<br>+<br>+ if (id < 0)<br>+ id = variant_board_id();<br>+<br>+ return id;<br>+}<br>diff --git a/src/mainboard/google/zoombini/bootblock.c b/src/mainboard/google/zoombini/bootblock.c<br>new file mode 100644<br>index 0000000..5f37206<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/bootblock.c<br>@@ -0,0 +1,33 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <baseboard/gpio.h><br>+#include <baseboard/variants.h><br>+#include <bootblock_common.h><br>+#include <soc/gpio.h><br>+<br>+static void early_config_gpio(void)<br>+{<br>+ const struct pad_config *early_gpio_table;<br>+ size_t num_gpios = 0;<br>+<br>+ early_gpio_table = variant_early_gpio_table(&num_gpios);<br>+ gpio_configure_pads(early_gpio_table, num_gpios);<br>+}<br>+<br>+void bootblock_mainboard_init(void)<br>+{<br>+ early_config_gpio();<br>+}<br>diff --git a/src/mainboard/google/zoombini/chromeos.c b/src/mainboard/google/zoombini/chromeos.c<br>new file mode 100644<br>index 0000000..a04065e<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/chromeos.c<br>@@ -0,0 +1,56 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/acpi.h><br>+#include <baseboard/gpio.h><br>+#include <gpio.h><br>+#include <rules.h><br>+#include <soc/gpio.h><br>+#include <vendorcode/google/chromeos/chromeos.h><br>+<br>+<br>+#if ENV_RAMSTAGE<br>+#include <boot/coreboot_tables.h><br>+<br>+void fill_lb_gpios(struct lb_gpios *gpios)<br>+{<br>+ struct lb_gpio chromeos_gpios[] = {<br>+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},<br>+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},<br>+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},<br>+ {-1, ACTIVE_HIGH, 0, "power"},<br>+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},<br>+ {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),<br>+ "EC in RW"},<br>+ };<br>+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));<br>+}<br>+#endif /* ENV_RAMSTAGE */<br>+<br>+int get_write_protect_state(void)<br>+{<br>+ /* Read PCH_WP GPIO. */<br>+ return gpio_get(GPIO_PCH_WP);<br>+}<br>+<br>+static const struct cros_gpio cros_gpios[] = {<br>+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),<br>+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),<br>+};<br>+<br>+void mainboard_chromeos_acpi_generate(void)<br>+{<br>+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));<br>+}<br>diff --git a/src/mainboard/google/zoombini/chromeos.fmd b/src/mainboard/google/zoombini/chromeos.fmd<br>new file mode 100644<br>index 0000000..bdadcf7<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/chromeos.fmd<br>@@ -0,0 +1,43 @@<br>+FLASH@0xff000000 0x1000000 {<br>+ SI_ALL@0x0 0x200000 {<br>+ SI_DESC@0x0 0x1000<br>+ SI_ME@0x1000 0x1ff000<br>+ }<br>+ SI_BIOS@0x200000 0xe00000 {<br>+ RW_SECTION_A@0x0 0x3e8000 {<br>+ VBLOCK_A@0x0 0x10000<br>+ FW_MAIN_A(CBFS)@0x10000 0x3d7fc0<br>+ RW_FWID_A@0x3e7fc0 0x40<br>+ }<br>+ RW_SECTION_B@0x3e8000 0x3e8000 {<br>+ VBLOCK_B@0x0 0x10000<br>+ FW_MAIN_B(CBFS)@0x10000 0x3d7fc0<br>+ RW_FWID_B@0x3e7fc0 0x40<br>+ }<br>+ RW_MISC@0x7d0000 0x30000 {<br>+ UNIFIED_MRC_CACHE@0x0 0x20000 {<br>+ RECOVERY_MRC_CACHE@0x0 0x10000<br>+ RW_MRC_CACHE@0x10000 0x10000<br>+ }<br>+ RW_ELOG@0x20000 0x4000<br>+ RW_SHARED@0x24000 0x4000 {<br>+ SHARED_DATA@0x0 0x2000<br>+ VBLOCK_DEV@0x2000 0x2000<br>+ }<br>+ RW_VPD@0x28000 0x2000<br>+ RW_NVRAM@0x2a000 0x6000<br>+ }<br>+ RW_LEGACY(CBFS)@0x800000 0x200000<br>+ WP_RO@0xa00000 0x400000 {<br>+ RO_VPD@0x0 0x4000<br>+ RO_UNUSED@0x4000 0xc000<br>+ RO_SECTION@0x10000 0x3f0000 {<br>+ FMAP@0x0 0x800<br>+ RO_FRID@0x800 0x40<br>+ RO_FRID_PAD@0x840 0x7c0<br>+ GBB@0x1000 0xef000<br>+ COREBOOT(CBFS)@0xf0000 0x300000<br>+ }<br>+ }<br>+ }<br>+}<br>diff --git a/src/mainboard/google/zoombini/ec.c b/src/mainboard/google/zoombini/ec.c<br>new file mode 100644<br>index 0000000..850b13c<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/ec.c<br>@@ -0,0 +1,43 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/acpi.h><br>+#include <ec/google/chromeec/ec.h><br>+<br>+#include <variant/ec.h><br>+<br>+void mainboard_ec_init(void)<br>+{<br>+ if (acpi_is_wakeup_s3()) {<br>+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |<br>+ MAINBOARD_EC_S3_WAKE_EVENTS);<br>+<br>+ /* Disable SMI and wake events */<br>+ google_chromeec_set_smi_mask(0);<br>+<br>+ /* Clear pending events */<br>+ while (google_chromeec_get_event() != 0)<br>+ ;<br>+<br>+ /* Restore SCI event mask */<br>+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);<br>+ } else {<br>+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |<br>+ MAINBOARD_EC_S5_WAKE_EVENTS);<br>+ }<br>+<br>+ /* Clear wake event mask */<br>+ google_chromeec_set_wake_mask(0);<br>+}<br>diff --git a/src/mainboard/google/zoombini/ramstage.c b/src/mainboard/google/zoombini/ramstage.c<br>new file mode 100644<br>index 0000000..6dafe65<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/ramstage.c<br>@@ -0,0 +1,23 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/ramstage.h><br>+<br>+#include "gpio.h"<br>+<br>+void mainboard_silicon_init_params(FSP_SIL_UPD *params)<br>+{<br>+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));<br>+}<br>diff --git a/src/mainboard/google/zoombini/romstage.c b/src/mainboard/google/zoombini/romstage.c<br>new file mode 100644<br>index 0000000..bbfb985<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/romstage.c<br>@@ -0,0 +1,33 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <soc/romstage.h><br>+<br>+void mainboard_save_dimm_info(void);<br>+<br>+void mainboard_memory_init_params(FSPM_UPD *memupd)<br>+{<br>+/*<br>+ meminit_lpddr4_by_sku(&memupd->FspmConfig, get_lpddr4_config(),<br>+ get_memory_sku());<br>+*/<br>+}<br>+<br>+void mainboard_save_dimm_info(void)<br>+{<br>+/*<br>+ save_lpddr4_dimm_info(get_lpddr4_config(), get_memory_sku());<br>+*/<br>+}<br>diff --git a/src/mainboard/google/zoombini/smihandler.c b/src/mainboard/google/zoombini/smihandler.c<br>new file mode 100644<br>index 0000000..e4ca589<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/smihandler.c<br>@@ -0,0 +1,40 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <cpu/x86/smm.h><br>+#include <ec/google/chromeec/smm.h><br>+#include <gpio.h><br>+#include <soc/gpio.h><br>+#include <soc/smm.h><br>+<br>+#include "ec.h"<br>+<br>+void mainboard_smi_espi_handler(void)<br>+{<br>+ chromeec_smi_process_events();<br>+}<br>+<br>+void mainboard_smi_sleep(u8 slp_typ)<br>+{<br>+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,<br>+ MAINBOARD_EC_S5_WAKE_EVENTS);<br>+}<br>+<br>+int mainboard_smi_apmc(u8 apmc)<br>+{<br>+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,<br>+ MAINBOARD_EC_SMI_EVENTS);<br>+ return 0;<br>+}<br>diff --git a/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc b/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc<br>new file mode 100644<br>index 0000000..3385b4c<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/variants/baseboard/Makefile.inc<br>@@ -0,0 +1,21 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2017 Google Inc.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+bootblock-y += gpio.c<br>+<br>+romstage-y += boardid.c<br>+<br>+ramstage-y += boardid.c<br>+ramstage-y += gpio.c<br>diff --git a/src/mainboard/google/zoombini/variants/baseboard/boardid.c b/src/mainboard/google/zoombini/variants/baseboard/boardid.c<br>new file mode 100644<br>index 0000000..1cb084a<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/variants/baseboard/boardid.c<br>@@ -0,0 +1,22 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <baseboard/variants.h><br>+#include <ec/google/chromeec/ec.h><br>+<br>+uint8_t __attribute__((weak)) variant_board_id(void)<br>+{<br>+ return google_chromeec_get_board_version();<br>+}<br>diff --git a/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb<br>new file mode 100644<br>index 0000000..e71f15b<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/variants/baseboard/devicetree.cb<br>@@ -0,0 +1,61 @@<br>+chip soc/intel/cannonlake<br>+<br>+ device cpu_cluster 0 on<br>+ device lapic 0 on end<br>+ end<br>+<br>+ device domain 0 on<br>+ device pci 00.0 on end # Host Bridge<br>+ device pci 02.0 on end # Integrated Graphics Device<br>+ device pci 04.0 on end # SA Thermal device<br>+ device pci 12.0 on end # Thermal Subsystem<br>+ device pci 12.5 off end # UFS SCS<br>+ device pci 12.6 off end # GSPI #2<br>+ device pci 14.0 on end # USB xHCI<br>+ device pci 14.1 off end # USB xDCI (OTG)<br>+ device pci 14.5 on end # SDCard<br>+ device pci 15.0 on end # I2C #0<br>+ device pci 15.1 on end # I2C #1<br>+ device pci 15.2 off end # I2C #2<br>+ device pci 15.3 off end # I2C #3<br>+ device pci 16.0 on end # Management Engine Interface 1<br>+ device pci 16.1 off end # Management Engine Interface 2<br>+ device pci 16.2 off end # Management Engine IDE-R<br>+ device pci 16.3 off end # Management Engine KT Redirection<br>+ device pci 16.4 off end # Management Engine Interface 3<br>+ device pci 16.5 off end # Management Engine Interface 4<br>+ device pci 17.0 on end # SATA<br>+ device pci 19.0 on end # I2C #4<br>+ device pci 19.1 off end # I2C #5<br>+ device pci 19.2 on end # UART #2<br>+ device pci 1a.0 on end # eMMC<br>+ device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1<br>+ device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN<br>+ device pci 1c.5 off end # PCI Express Port 6<br>+ device pci 1c.6 off end # PCI Express Port 7<br>+ device pci 1c.7 off end # PCI Express Port 8<br>+ device pci 1d.0 off end # PCI Express Port 9<br>+ device pci 1d.1 off end # PCI Express Port 10<br>+ device pci 1d.2 off end # PCI Express Port 11<br>+ device pci 1d.3 off end # PCI Express Port 12<br>+ device pci 1d.4 off end # PCI Express Port 13<br>+ device pci 1d.5 off end # PCI Express Port 14<br>+ device pci 1d.6 off end # PCI Express Port 15<br>+ device pci 1d.7 off end # PCI Express Port 16<br>+ device pci 1e.0 on end # UART #0<br>+ device pci 1e.1 off end # UART #1<br>+ device pci 1e.2 off end # GSPI #0<br>+ device pci 1e.3 off end # GSPI #1<br>+ device pci 1f.0 on<br>+ chip drivers/pc80/tpm<br>+ device pnp 0c31.0 on end<br>+ end<br>+ end # LPC Interface<br>+ device pci 1f.1 on end # P2SB<br>+ device pci 1f.2 on end # Power Management Controller<br>+ device pci 1f.3 on end # Intel HDA<br>+ device pci 1f.4 on end # SMBus<br>+ device pci 1f.5 on end # PCH SPI<br>+ device pci 1f.6 off end # GbE<br>+ end<br>+end<br>diff --git a/src/mainboard/google/zoombini/variants/baseboard/gpio.c b/src/mainboard/google/zoombini/variants/baseboard/gpio.c<br>new file mode 100644<br>index 0000000..5eef040<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/variants/baseboard/gpio.c<br>@@ -0,0 +1,274 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <baseboard/gpio.h><br>+#include <baseboard/variants.h><br>+<br>+/* Pad configuration in ramstage */<br>+static const struct pad_config gpio_table[] = {<br>+/* RCIN# */ PAD_CFG_GPI(GPP_A0, NONE, DEEP), /* PCH_CSI_GPIO1 */<br>+/* ESPI_IO0 */<br>+/* ESPI_IO1 */<br>+/* ESPI_IO2 */<br>+/* ESPI_IO3 */<br>+/* ESPI_CS# */<br>+/* SERIRQ */ PAD_CFG_GPI(GPP_A6, NONE, DEEP), /* PCH_CSI_GPIO2 */<br>+/* PIRQA# */ PAD_NC(GPP_A7, NONE), /* PCH_CSI_GPIO1 */<br>+/* CLKRUN# */ PAD_CFG_GPI(GPP_A8, NONE, DEEP), /* EC_IN_RW_OD */<br>+/* ESPI_CLK */<br>+/* CLKOUT_LPC1 */ PAD_CFG_GPO(GPP_A10, 0, DEEP), /* PEN_RESET_ODL */<br>+/* PME# */ PAD_NC(GPP_A11, NONE),<br>+/* BM_BUSY# */ PAD_CFG_GPI(GPP_A12, UP_20K, DEEP), /* FPMCU_INT */<br>+/* SUSWARN# */<br>+/* ESPI_RESET# */<br>+/* SUSACK# */<br>+/* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE),<br>+/* SD_PWR_EN# */<br>+/* ISH_GP0 */ PAD_CFG_GPO(GPP_A18, 0, DEEP),<br>+ /* GNSS_DISABLE_1V8_ODL */<br>+/* ISH_GP1 */ PAD_CFG_GPO(GPP_A19, 0, DEEP),<br>+ /* WWAN_RADIO_DISABLE_1V8_ODL */<br>+/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP), /* GP_INT_ODL */<br>+/* ISH_GP3 */ PAD_CFG_GPI(GPP_A21, NONE, DEEP), /* FPMCU_PCH_BOOT0 */<br>+/* ISH_GP4 */ PAD_CFG_GPI(GPP_A22, UP_20K, DEEP), /* FPMCU_INT */<br>+/* ISH_GP5 */ PAD_CFG_GPO(GPP_A23, 0, DEEP), /* FPMCU_RST_ODL */<br>+/* CORE_VID0 */ PAD_NC(GPP_B0, NONE),<br>+/* CORE_VID1 */ PAD_NC(GPP_B1, NONE),<br>+/* VRALERT# */ PAD_NC(GPP_B2, NONE),<br>+/* CPU_GP2 */ PAD_NC(GPP_B3, NONE),<br>+/* CPU_GP3 */ PAD_NC(GPP_B4, NONE),<br>+/* SRCCLKREQ0# */ PAD_NC(GPP_B5, NONE),<br>+/* SRCCLKREQ1# */<br>+/* SRCCLKREQ2# */<br>+/* SRCCLKREQ3# */<br>+/* SRCCLKREQ4# */ PAD_NC(GPP_B9, NONE),<br>+/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE),<br>+/* EXT_PWR_GATE# */<br>+/* SLP_S0# */<br>+/* PLTRST# */<br>+/* SPKR */ PAD_NC(GPP_B14, DN_20K), /* GPP_B14_STRAP */<br>+#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)<br>+/* GSPI0_CS# */ /* H1_SLAVE_SPI_CS_L */<br>+/* GSPI0_CLK */ /* H1_SLAVE_SPI_CLK_R */<br>+/* GSPI0_MISO */ /* H1_SLAVE_SPI_MISO_R */<br>+/* GSPI0_MOSI */ /* H1_SLAVE_SPI_MOSI_R */<br>+#else<br>+/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE),<br>+/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),<br>+/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),<br>+/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),<br>+#endif<br>+/* GSPI1_CS# */<br>+/* GSPI1_CLK */<br>+/* GSPI1_MISO */<br>+/* GSPI1_MOSI */<br>+/* SML1ALERT# */ PAD_NC(GPP_B23, DN_20K), /* GPP_B23_STRAP */<br>+/* SMBCLK */ PAD_CFG_GPO(GPP_C0, 0, DEEP), /* SOC_EDP_CABC_EN */<br>+/* SMBDATA */ PAD_CFG_GPI(GPP_C1, NONE, DEEP),<br>+ /* PCIE_8_WLAN_WAKE_ODL */<br>+/* SMBALERT# */ PAD_NC(GPP_C2, DN_20K), /* GPP_C2_STRAP - 20K_PD */<br>+/* SML0CLK */ PAD_CFG_GPO(GPP_C3, 0, DEEP),<br>+ /* EN_PP3300_TRACKPAD */<br>+/* SML0DATA */ PAD_NC(GPP_C4, NONE),<br>+/* SML0ALERT# */ PAD_NC(GPP_C5, DN_20K), /* GPP_C5_STRAP - 20K_PD */<br>+/* SM1CLK */ PAD_CFG_GPI(GPP_C6, NONE, DEEP), /* PEN_PDCT_ODL */<br>+/* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* PEN_INT_ODL */<br>+/* UART0_RXD */<br>+/* UART0_TXD */<br>+/* UART0_RTS# */ PAD_NC(GPP_C10, NONE),<br>+/* UART0_CTS# */ PAD_NC(GPP_C11, NONE),<br>+/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* H1_PCH_INT_ODL */<br>+/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* TRACKPAD_INT_ODL */<br>+/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),<br>+ /* TOUCHSCREEN_INT_ODL */<br>+/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* TRACKPAD_INT_ODL */<br>+/* I2C0_SDA */<br>+/* I2C0_SCL */<br>+/* I2C1_SDA */<br>+/* I2C1_SCL */<br>+/* UART2_RXD */ PAD_NC(GPP_C20, NONE),<br>+/* UART2_TXD */ PAD_NC(GPP_C21, NONE),<br>+/* UART2_RTS# */ PAD_NC(GPP_C22, NONE),<br>+/* UART2_CTS# */ PAD_NC(GPP_C23, NONE),<br>+/* SPI1_CS# */ PAD_CFG_GPI(GPP_D0, NONE, DEEP), /* PCH_MEM_STRAP3 */<br>+/* SPI1_CLK */ PAD_NC(GPP_D1, NONE),<br>+/* SPI1_MISO */ PAD_NC(GPP_D2, NONE),<br>+/* SPI1_MOSI */ PAD_CFG_GPI(GPP_D3, NONE, DEEP), /* PCH_MEM_STRAP0 */<br>+/* FASHTRIG */<br>+/* ISH_I2C0_SDA */ PAD_NC(GPP_D5, NONE), /* TP57 */<br>+/* ISH_I2C0_SCL */ PAD_NC(GPP_D6, NONE), /* TP58 */<br>+/* ISH_I2C1_SDA */ PAD_NC(GPP_D7, NONE), /* TP59 */<br>+/* ISH_I2C1_SCL */ PAD_NC(GPP_D8, NONE),<br>+/* ISH_SPI_CS# */ PAD_NC(GPP_D9, NONE),<br>+/* ISH_SPI_CLK */ PAD_NC(GPP_D10, NONE),<br>+/* ISH_SPI_MISO */ PAD_NC(GPP_D11, NONE),<br>+/* ISH_SPI_MOSI */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), /* GPP_D12_STRAP */<br>+/* ISH_UART0_RXD */ PAD_CFG_GPI(GPP_D13, UP_20K, DEEP), /* VOL_UP_ODL */<br>+/* ISH_UART0_TXD */ PAD_CFG_GPI(GPP_D14, UP_20K, DEEP), /* VOL_DOWN_ODL */<br>+/* ISH_UART0_RTS# */ PAD_CFG_GPO(GPP_D15, 0, DEEP),<br>+ /* TOUCHSCREEN_RST_ODL */<br>+/* ISH_UART0_CTS# */ PAD_CFG_GPO(GPP_D16, 0, DEEP), /* SPK_PA_EN */<br>+/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),<br>+ /* BASE_CAM_DMIC_CLK */<br>+/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),<br>+ /* BASE_CAM_DMIC_DATA */<br>+/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),<br>+ /* LID_CAM_DMIC_CLK */<br>+/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),<br>+ /* LID_CAM_DMIC_DATA */<br>+/* SPI1_IO2 */ PAD_CFG_GPI(GPP_D21, NONE, DEEP), /* PCH_MEM_STRAP1 */<br>+/* SPI1_IO3 */ PAD_CFG_GPI(GPP_D22, NONE, DEEP), /* PCH_MEM_STRAP2 */<br>+/* I2S_MCLK */<br>+/* SATAXPCI0 */ PAD_NC(GPP_E0, NONE), /* PCH_TP_1 */<br>+/* SATAXPCIE1 */ PAD_NC(GPP_E1, NONE), /* PCH_TP_2 */<br>+/* SATAXPCIE2 */ PAD_NC(GPP_E2, NONE), /* PCH_TP_3 */<br>+/* CPU_GP0 */ PAD_NC(GPP_E3, NONE),<br>+/* SATA_DEVSLP0 */ PAD_CFG_GPI(GPP_E4, NONE, DEEP),<br>+ /* PCIE_7_WWAN_WAKE_ODL */<br>+/* SATA_DEVSLP1 */ PAD_NC(GPP_E5, NONE),<br>+/* SATA_DEVSLP2 */ PAD_NC(GPP_E6, NONE),<br>+/* CPU_GP1 */ PAD_NC(GPP_E7, NONE),<br>+/* SATALED# */ PAD_NC(GPP_E8, NONE), /* PCH_TP_4 */<br>+/* USB2_OCO# */<br>+/* USB2_OC1# */<br>+/* USB2_OC2# */<br>+/* USB2_OC3# */<br>+/* DDPB_HPD0 */<br>+/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* USB_C1_HPD */<br>+/* DDPD_HPD2 */<br>+/* DDPE_HPD3 */ PAD_NC(GPP_E16, NONE),<br>+/* EDP_HPD */<br>+/* DDPB_CTRLCLK */ PAD_NC(GPP_E18, NONE),<br>+/* DDPB_CTRLDATA */ PAD_CFG_GPI(GPP_E19, DN_20K, DEEP), /* GPP_E19_STRAP */<br>+/* DDPC_CTRLCLK */ PAD_NC(GPP_E20, NONE),<br>+/* DDPC_CTRLDATA */ PAD_CFG_GPI(GPP_E21, DN_20K, DEEP), /* GPP_E21_STRAP */<br>+/* DDPD_CTRLCLK */ PAD_NC(GPP_E22, NONE),<br>+/* DDPD_CTRLDATA */ PAD_CFG_GPI(GPP_E23, DN_20K, DEEP), /* I2S2_SCLK */<br>+/* I2S2_SFRM */ PAD_CFG_GPO(GPP_F1, 0, DEEP),<br>+ /* WWAN_RESET_1V8_ODL */<br>+/* I2S2_TXD */ PAD_NC(GPP_F2, NONE),<br>+/* I2S2_RXD */ PAD_CFG_GPO(GPP_F3, 0, DEEP), /* CNV_RF_RESET_L */<br>+/* I2C2_SDA */<br>+/* I2C2_SCL */<br>+/* I2C3_SDA */<br>+/* I2C3_SCL */<br>+/* I2C4_SDA */<br>+/* I2C4_SCL */<br>+/* I2C5_SDA */<br>+/* I2C5_SCL */<br>+/* EMMC_CMD */<br>+/* EMMC_DATA0 */<br>+/* EMMC_DATA1 */<br>+/* EMMC_DATA2 */<br>+/* EMMC_DATA3 */<br>+/* EMMC_DATA4 */<br>+/* EMMC_DATA5 */<br>+/* EMMC_DATA6 */<br>+/* EMMC_DATA7 */<br>+/* EMMC_RCLK */<br>+/* EMMC_CLK */<br>+/* RSVD */ PAD_NC(GPP_F23, NONE),<br>+/* SD_CMD */<br>+/* SD_DATA0 */<br>+/* SD_DATA1 */<br>+/* SD_DATA2 */<br>+/* SD_DATA3 */<br>+/* SD_CD# */<br>+/* SD_CLK */<br>+/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* SD_CD_ODL */<br>+/* I2S2_SCLK */ PAD_NC(GPP_H0, NONE), /* I2S2_SCLK - TP75 */<br>+/* I2S2_SFRM */ PAD_NC(GPP_H1, NONE), /* I2S2_SFRM - TP74 */<br>+/* I2S2_TXD */<br>+/* I2S2_RXD */ PAD_NC(GPP_H3, NONE), /* I2S2_PCH_RX TP76 */<br>+/* I2C2_SDA */<br>+/* I2C2_SCL */<br>+/* I2C3_SDA */<br>+/* I2C3_SCL */<br>+/* I2C4_SDA */<br>+/* I2C4_SCL */<br>+/* I2C5_SDA */<br>+/* I2C5_SCL */<br>+/* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), /* PCH_TP_5 - TP60 */<br>+/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* PCH_TP_6 - TP61 */<br>+/* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* PCH_TP_7 - TP62 */<br>+/* M2_SKT2_CFG3 */ PAD_NC(GPP_H15, NONE), /* PCH_TP_8 - TP63 */<br>+/* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE),<br>+/* DPPF_CTRLDATA */ PAD_NC(GPP_H17, NONE),<br>+/* CPU_C10_GATE# */ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),<br>+ /* CPU_C10_GATE_PCH_L */<br>+/* TIMESYNC0 */ PAD_NC(GPP_H19, NONE),<br>+/* IMGCLKOUT1 */ PAD_NC(GPP_H20, NONE),<br>+/* GPP_H21 */ PAD_CFG_GPI(GPP_H21, DN_20K, DEEP), /* H21_STRAP */<br>+/* GPP_H22 */<br>+/* GPP_H23 */ PAD_NC(GPP_H23, DN_20K), /* H23_STRAP */<br>+<br>+/* BATLOW# */<br>+/* ACPRESENT */ PAD_NC(GPD1, NONE),<br>+/* LAN_WAKE# */ PAD_NC(GPD2, NONE), /* LAN_WAKE_L - TP71 */<br>+/* PWRBTN# */<br>+/* SLP_S3# */<br>+/* SLP_S4# */<br>+/* SLP_A# */ PAD_NC(GPD6, NONE),<br>+/* RSVD */<br>+/* SUSCLK */<br>+/* SLP_WLAN# */ PAD_NC(GPD9, NONE),<br>+/* SLP_S5# */ PAD_NC(GPD10, NONE),<br>+/* LANPHYC */ PAD_NC(GPD11, NONE),<br>+};<br>+<br>+/* Early pad configuration in bootblock */<br>+static const struct pad_config early_gpio_table[] = {<br>+#if IS_ENABLED(CONFIG_ZOOMBINI_USE_SPI_TPM)<br>+/* GSPI0_CS# */ PAD_CFG_NF(GPP_B15, NONE, DEEP,<br>+ NF1), /* PCH_SPI_H1_3V3_CS_L */<br>+/* GSPI0_CLK */ PAD_CFG_NF(GPP_B16, NONE, DEEP,<br>+ NF1), /* PCH_SPI_H1_3V3_CLK */<br>+/* GSPI0_MISO */ PAD_CFG_NF(GPP_B17, NONE, DEEP,<br>+ NF1), /* PCH_SPI_H1_3V3_MISO */<br>+/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,<br>+ NF1), /* PCH_SPI_H1_3V3_MOSI */<br>+#endif<br>+#if IS_ENABLED(CONFIG_ZOOMBINI_USE_I2C_TPM)<br>+/* I2C5_SDA */<br>+/* I2C5_SCL */<br>+#endif<br>+/* Ensure UART pins are in native mode for H1. */<br>+/* UART0_RXD */ /* UART_PCH_RX_DEBUG_TX */<br>+/* UART0_TXD */ /* UART_PCH_RX_DEBUG_RX */<br>+};<br>+<br>+const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)<br>+{<br>+ *num = ARRAY_SIZE(gpio_table);<br>+ return gpio_table;<br>+}<br>+<br>+const struct pad_config *__attribute__((weak))<br>+ variant_early_gpio_table(size_t *num)<br>+{<br>+ *num = ARRAY_SIZE(early_gpio_table);<br>+ return early_gpio_table;<br>+}<br>+<br>+static const struct cros_gpio cros_gpios[] = {<br>+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),<br>+};<br>+<br>+const struct cros_gpio *__attribute__((weak)) variant_cros_gpios(size_t *num)<br>+{<br>+ *num = ARRAY_SIZE(cros_gpios);<br>+ return cros_gpios;<br>+}<br>+<br>diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h<br>new file mode 100644<br>index 0000000..9766c1d<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/ec.h<br>@@ -0,0 +1,82 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __BASEBOARD_EC_H__<br>+#define __BASEBOARD_EC_H__<br>+<br>+#include <ec/ec.h><br>+#include <ec/google/chromeec/ec_commands.h><br>+<br>+#include "gpio.h"<br>+<br>+#define MAINBOARD_EC_SCI_EVENTS \<br>+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))<br>+<br>+#define MAINBOARD_EC_SMI_EVENTS \<br>+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))<br>+<br>+/* EC can wake from S5 with lid or power button */<br>+#define MAINBOARD_EC_S5_WAKE_EVENTS \<br>+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))<br>+<br>+/*<br>+ * EC can wake from S3 with lid or power button or key press or<br>+ * mode change event.<br>+ */<br>+#define MAINBOARD_EC_S3_WAKE_EVENTS \<br>+ (MAINBOARD_EC_S5_WAKE_EVENTS |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))<br>+<br>+/* Log EC wake events plus EC shutdown events */<br>+#define MAINBOARD_EC_LOG_EVENTS \<br>+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\<br>+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))<br>+<br>+/*<br>+ * ACPI related definitions for ASL code.<br>+ */<br>+<br>+/* Enable EC backed ALS device in ACPI */<br>+#define EC_ENABLE_ALS_DEVICE<br>+<br>+/* Enable EC backed PD MCU device in ACPI */<br>+#define EC_ENABLE_PD_MCU_DEVICE<br>+<br>+/* Enable LID switch and provide wake pin for EC */<br>+#define EC_ENABLE_LID_SWITCH<br>+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE<br>+<br>+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */<br>+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */<br>+<br>+#define EC_ENABLE_MKBP_DEVICE /* Enable cros_ec_keyb device */<br>+<br>+#endif<br>diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h<br>new file mode 100644<br>index 0000000..8b0ad2b<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/gpio.h<br>@@ -0,0 +1,41 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __MAINBOARD_GPIO_H__<br>+#define __MAINBOARD_GPIO_H__<br>+<br>+#include <soc/gpio.h><br>+<br>+/* Memory configuration board straps */<br>+#define GPIO_MEM_CONFIG_0 GPP_D3<br>+#define GPIO_MEM_CONFIG_1 GPP_D21<br>+#define GPIO_MEM_CONFIG_2 GPP_D22<br>+#define GPIO_MEM_CONFIG_3 GPP_D0<br>+<br>+/* EC in RW */<br>+#define GPIO_EC_IN_RW GPP_A8<br>+<br>+/* BIOS Flash Write Protect */<br>+#define GPIO_PCH_WP GPP_A1<br>+<br>+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */<br>+#define GPE_EC_WAKE GPP_74<br>+<br>+/* eSPI virtual wire reporting */<br>+#define EC_SCI_GPI GPP_76<br>+<br>+const struct pad_config *get_gpio_table(size_t *num);<br>+const struct pad_config *get_early_gpio_table(size_t *num);<br>+#endif<br>diff --git a/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h<br>new file mode 100644<br>index 0000000..8181b8e<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/variants/baseboard/include/baseboard/variants.h<br>@@ -0,0 +1,35 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __BASEBOARD_VARIANTS_H__<br>+#define __BASEBOARD_VARIANTS_H__<br>+<br>+#include <soc/gpio.h><br>+#include <stdint.h><br>+#include <vendorcode/google/chromeos/chromeos.h><br>+<br>+/* Return the board id for the current variant board. */<br>+uint8_t variant_board_id(void);<br>+<br>+/*<br>+ * The next set of functions return the gpio table and fill in the number of<br>+ * entries for each table.<br>+ */<br>+const struct pad_config *variant_gpio_table(size_t *num);<br>+const struct pad_config *variant_early_gpio_table(size_t *num);<br>+<br>+const struct cros_gpio *variant_cros_gpios(size_t *num);<br>+<br>+#endif /*__BASEBOARD_VARIANTS_H__ */<br>diff --git a/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h b/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h<br>new file mode 100644<br>index 0000000..ef47d37<br>--- /dev/null<br>+++ b/src/mainboard/google/zoombini/variants/zoombini/include/variant/ec.h<br>@@ -0,0 +1,21 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __MAINBOARD_EC_H__<br>+#define __MAINBOARD_EC_H__<br>+<br>+#include <baseboard/ec.h><br>+<br>+#endif /* __MAINBOARD_EC_H__ */<br>diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig<br>index 65b581e..85d94f6 100644<br>--- a/src/soc/intel/cannonlake/Kconfig<br>+++ b/src/soc/intel/cannonlake/Kconfig<br>@@ -16,6 +16,7 @@<br> select BOOT_DEVICE_SUPPORTS_WRITES<br> select C_ENVIRONMENT_BOOTBLOCK<br> select CPU_INTEL_FIRMWARE_INTERFACE_TABLE<br>+ select GENERIC_GPIO_LIB<br> select HAVE_HARD_RESET<br> select HAVE_INTEL_FIRMWARE<br> select HAVE_MONOTONIC_TIMER<br>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 0c05057..9ce647d 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -19,6 +19,7 @@<br> bootblock-y += spi.c<br> bootblock-$(CONFIG_UART_DEBUG) += uart.c<br> <br>+romstage-y += gpio.c<br> romstage-y += gspi.c<br> romstage-y += memmap.c<br> romstage-y += pmutil.c<br>@@ -28,6 +29,7 @@<br> <br> ramstage-y += chip.c<br> ramstage-y += cpu.c<br>+ramstage-y += gpio.c<br> ramstage-y += gspi.c<br> ramstage-y += memmap.c<br> ramstage-y += pmutil.c<br></pre><p>To view, visit <a href="https://review.coreboot.org/21273">change 21273</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21273"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I13ebaae403d08f1b2e6881eeba4dc1787c792b4e </div>
<div style="display:none"> Gerrit-Change-Number: 21273 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nick Vaccaro <nvaccaro@google.com> </div>