<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21235">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Usable dram top calculation based on HW registers<br><br>This patch ensures that entire system memory calculation is done<br>based on host bridge registers.<br><br>BRANCH=none<br>BUG=b:63974384<br>TEST=Build and boot cannonlake RVP successfully with below configurations<br>1. Booting to OS with no UPD change<br>2. Enable ProbelessTrace UPD and boot to OS.<br>3. Enable PRMRR with size 1MB and boot to OS.<br>4. Enable PRMRR with size 32MB and boot to OS.<br>5. Enable PRMRR with size 2MB and unable to boot to OS due to<br>unsupported PRMRR size.<br>6. Enable C6 DRAM with PRMRR size 0MB and boot to OS.<br><br>Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/cannonlake/chip.h<br>M src/soc/intel/cannonlake/include/soc/systemagent.h<br>M src/soc/intel/cannonlake/memmap.c<br>3 files changed, 99 insertions(+), 4 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/21235/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h<br>index 48305fe..9b50846 100644<br>--- a/src/soc/intel/cannonlake/chip.h<br>+++ b/src/soc/intel/cannonlake/chip.h<br>@@ -186,6 +186,8 @@<br> <br> /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */<br> uint8_t eist_enable;<br>+ /* Enable C6 DRAM */<br>+ uint8_t enable_c6dram;<br> };<br> <br> typedef struct soc_intel_cannonlake_config config_t;<br>diff --git a/src/soc/intel/cannonlake/include/soc/systemagent.h b/src/soc/intel/cannonlake/include/soc/systemagent.h<br>index 1902314..da83c38 100644<br>--- a/src/soc/intel/cannonlake/include/soc/systemagent.h<br>+++ b/src/soc/intel/cannonlake/include/soc/systemagent.h<br>@@ -40,4 +40,7 @@<br> #define MCH_DDR_POWER_LIMIT_LO 0x58e0<br> #define MCH_DDR_POWER_LIMIT_HI 0x58e4<br> <br>+#define IMRBASE 0x6A40<br>+#define IMRLIMIT 0x6A48<br>+<br> #endif<br>diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c<br>index 8b487f6..1b6e6da 100644<br>--- a/src/soc/intel/cannonlake/memmap.c<br>+++ b/src/soc/intel/cannonlake/memmap.c<br>@@ -34,15 +34,105 @@<br> write32(top_of_ram_register(), 0);<br> }<br> <br>+/*<br>+ * Host Memory Map:<br>+ *<br>+ * +--------------------------+ TOUUD<br>+ * | |<br>+ * +--------------------------+ 4GiB<br>+ * | PCI Address Space |<br>+ * +--------------------------+ TOLUD (also maps into MC address space)<br>+ * | iGD |<br>+ * +--------------------------+ BDSM<br>+ * | GTT |<br>+ * +--------------------------+ BGSM<br>+ * | TSEG |<br>+ * +--------------------------+ TSEGMB<br>+ * | DMA Protected Region |<br>+ * +--------------------------+ DPR<br>+ * | PRM (C6DRAM/SGX) |<br>+ * +--------------------------+ PRMRR<br>+ * | ME Stolen Memory |<br>+ * +--------------------------+ ME Stolen<br>+ * | PTT |<br>+ * +--------------------------+ top_of_ram<br>+ * | Reserved - FSP/CBMEM |<br>+ * +--------------------------+ TOLUM<br>+ * | Usage DRAM |<br>+ * +--------------------------+ 0<br>+ *<br>+ * Some of the base registers above can be equal making the size of those<br>+ * regions 0. The reason is because the memory controller internally subtracts<br>+ * the base registers from each other to determine sizes of the regions. In<br>+ * other words, the memory map is in a fixed order no matter what.<br>+ */<br>+static u32 calculate_dram_base(void)<br>+{<br>+ const struct soc_intel_cannonlake_config *config;<br>+ const struct device *dev;<br>+ uint32_t dram_base;<br>+ uint32_t prmrr_base;<br>+ size_t prmrr_size;<br>+ size_t imr_size;<br>+<br>+ dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));<br>+<br>+ /* Read TOLUD from Host Bridge offset */<br>+ dram_base = sa_get_tolud_base();<br>+<br>+ if (dev->enabled) {<br>+ /* Read BDSM from Host Bridge */<br>+ dram_base -= sa_get_dsm_size();<br>+<br>+ /* Read BGSM from Host Bridge */<br>+ dram_base -= sa_get_gsm_size();<br>+ }<br>+ /* Get TSEG size */<br>+ dram_base -= smm_region_size();<br>+<br>+ /* Get DPR size */<br>+ if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))<br>+ dram_base -= sa_get_dpr_size();<br>+<br>+ dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0));<br>+ config = dev->chip_info;<br>+ prmrr_size = config->PrmrrSize;<br>+<br>+ if (prmrr_size > 0) {<br>+ /*<br>+ * PRMRR Sizes that are > 1MB and < 32MB are<br>+ * not supported and will fail out.<br>+ */<br>+ if ((prmrr_size > 1*MiB) && (prmrr_size < 32*MiB))<br>+ die("PRMRR Sizes that are > 1MB and < 32MB are not"<br>+ "supported!\n");<br>+<br>+ prmrr_base = dram_base - prmrr_size;<br>+ if (prmrr_size >= 32*MiB)<br>+ prmrr_base = ALIGN_DOWN(prmrr_base, 128*MiB);<br>+ dram_base = prmrr_base;<br>+ } else if (config->enable_c6dram && prmrr_size == 0) {<br>+ /* Allocate PRMRR memory for C6DRAM */<br>+ dram_base -= 1*MiB;<br>+ }<br>+<br>+ /* ME stolen memory */<br>+ imr_size = MCHBAR32(IMRLIMIT) - MCHBAR32(IMRBASE);<br>+ if (imr_size > 0)<br>+ dram_base -= imr_size;<br>+<br>+ if (is_ptt_enable())<br>+ dram_base -= 4*KiB; /* Allocate 4KB for PTT if enable */<br>+<br>+ return dram_base;<br>+}<br>+<br> void cbmem_top_init(void)<br> {<br>- struct range_entry fsp_mem;<br> uintptr_t top;<br> <br>- if (fsp_find_reserved_memory(&fsp_mem))<br>- die("Can't file top of ram.\n");<br>+ top = calculate_dram_base();<br> <br>- top = ALIGN_UP(range_entry_base(&fsp_mem), 16 * MiB);<br> write32(top_of_ram_register(), top);<br> }<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21235">change 21235</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2 </div>
<div style="display:none"> Gerrit-Change-Number: 21235 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>