<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21201">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Remove ABASE lock down programming<br><br>FSP is doing PMC ABASE lock inside Post PCI bus enumeration<br>NotifyPhase(). Hence remove ABASE Lock down programming<br>from coreboot.<br><br>TEST= Ensure GEN_PMCON_B offset 0xA4 bit 17, 18 is set.<br><br>Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/skylake/finalize.c<br>1 file changed, 1 insertion(+), 7 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/21201/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c<br>index a793e95..2fb37ca 100644<br>--- a/src/soc/intel/skylake/finalize.c<br>+++ b/src/soc/intel/skylake/finalize.c<br>@@ -126,12 +126,6 @@<br>     tcocnt |= TCO_LOCK;<br>   outw(tcocnt, tcobase + TCO1_CNT);<br> <br>- /* Lock down ABASE and sleep stretching policy */<br>-    dev = PCH_DEV_PMC;<br>-   reg32 = pci_read_config32(dev, GEN_PMCON_B);<br>- reg32 |= (SLP_STR_POL_LOCK | ACPI_BASE_LOCK);<br>-        pci_write_config32(dev, GEN_PMCON_B, reg32);<br>-<br>       /* PMSYNC */<br>  pmcbase = pmc_mmio_regs();<br>    pmsyncreg = read32(pmcbase + PMSYNC_TPR_CFG);<br>@@ -141,7 +135,7 @@<br>    /* Display me status before we hide it */<br>     intel_me_status();<br> <br>-        /* we should disable Heci1 based on the devicetree policy */<br>+ dev = PCH_DEV_PMC;<br>    config = dev->chip_info;<br> <br>        /*<br></pre><p>To view, visit <a href="https://review.coreboot.org/21201">change 21201</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21201"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I800e654c7d8dc55cc0e8299501c1f85c57882e9d </div>
<div style="display:none"> Gerrit-Change-Number: 21201 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma@intel.com> </div>