<p>Patrick Rudolph has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21158">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/*/nvs: Rename register<br><br>Rename register to match recent intel models.<br>Required for Lenovo H8 to operate on all generations.<br><br>Change-Id: I48a869adb1da2e33156968c4b7597edf99902c1a<br>Signed-off-by: Patrick Rudolph <siro@das-labor.org><br>---<br>M src/southbridge/intel/i82801gx/acpi/globalnvs.asl<br>M src/southbridge/intel/i82801gx/nvs.h<br>M src/southbridge/intel/i82801ix/acpi/globalnvs.asl<br>M src/southbridge/intel/i82801ix/nvs.h<br>4 files changed, 8 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/21158/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl<br>index fdd120e..9df2252 100644<br>--- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl<br>+++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl<br>@@ -50,11 +50,11 @@<br> /* Thermal policy */<br> Offset (0x14),<br> ACTT, 8, // 0x14 - active trip point<br>- PSVT, 8, // 0x15 - passive trip point<br>+ TPSV, 8, // 0x15 - passive trip point<br> TC1V, 8, // 0x16 - passive trip point TC1<br> TC2V, 8, // 0x17 - passive trip point TC2<br> TSPV, 8, // 0x18 - passive trip point TSP<br>- CRTT, 8, // 0x19 - critical trip point<br>+ TCRT, 8, // 0x19 - critical trip point<br> DTSE, 8, // 0x1a - Digital Thermal Sensor enable<br> DTS1, 8, // 0x1b - DT sensor 1<br> DTS2, 8, // 0x1c - DT sensor 2<br>diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/nvs.h<br>index c3a3920..decea53 100644<br>--- a/src/southbridge/intel/i82801gx/nvs.h<br>+++ b/src/southbridge/intel/i82801gx/nvs.h<br>@@ -35,11 +35,11 @@<br> u8 dckn; /* 0x13 - PCIe docking state */<br> /* Thermal policy */<br> u8 actt; /* 0x14 - active trip point */<br>- u8 psvt; /* 0x15 - passive trip point */<br>+ u8 tpsv; /* 0x15 - passive trip point */<br> u8 tc1v; /* 0x16 - passive trip point TC1 */<br> u8 tc2v; /* 0x17 - passive trip point TC2 */<br> u8 tspv; /* 0x18 - passive trip point TSP */<br>- u8 crtt; /* 0x19 - critical trip point */<br>+ u8 tcrt; /* 0x19 - critical trip point */<br> u8 dtse; /* 0x1a - Digital Thermal Sensor enable */<br> u8 dts1; /* 0x1b - DT sensor 1 */<br> u8 dts2; /* 0x1c - DT sensor 2 */<br>diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl<br>index df83064..97d9fa9 100644<br>--- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl<br>+++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl<br>@@ -51,11 +51,11 @@<br> /* Thermal policy */<br> Offset (0x14),<br> ACTT, 8, // 0x14 - active trip point<br>- PSVT, 8, // 0x15 - passive trip point<br>+ TPSV, 8, // 0x15 - passive trip point<br> TC1V, 8, // 0x16 - passive trip point TC1<br> TC2V, 8, // 0x17 - passive trip point TC2<br> TSPV, 8, // 0x18 - passive trip point TSP<br>- CRTT, 8, // 0x19 - critical trip point<br>+ TCRT, 8, // 0x19 - critical trip point<br> DTSE, 8, // 0x1a - Digital Thermal Sensor enable<br> DTS1, 8, // 0x1b - DT sensor 1<br> DTS2, 8, // 0x1c - DT sensor 2<br>diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/nvs.h<br>index c3a3920..decea53 100644<br>--- a/src/southbridge/intel/i82801ix/nvs.h<br>+++ b/src/southbridge/intel/i82801ix/nvs.h<br>@@ -35,11 +35,11 @@<br> u8 dckn; /* 0x13 - PCIe docking state */<br> /* Thermal policy */<br> u8 actt; /* 0x14 - active trip point */<br>- u8 psvt; /* 0x15 - passive trip point */<br>+ u8 tpsv; /* 0x15 - passive trip point */<br> u8 tc1v; /* 0x16 - passive trip point TC1 */<br> u8 tc2v; /* 0x17 - passive trip point TC2 */<br> u8 tspv; /* 0x18 - passive trip point TSP */<br>- u8 crtt; /* 0x19 - critical trip point */<br>+ u8 tcrt; /* 0x19 - critical trip point */<br> u8 dtse; /* 0x1a - Digital Thermal Sensor enable */<br> u8 dts1; /* 0x1b - DT sensor 1 */<br> u8 dts2; /* 0x1c - DT sensor 2 */<br></pre><p>To view, visit <a href="https://review.coreboot.org/21158">change 21158</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21158"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I48a869adb1da2e33156968c4b7597edf99902c1a </div>
<div style="display:none"> Gerrit-Change-Number: 21158 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Patrick Rudolph <siro@das-labor.org> </div>