<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21155">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Fix Coverity scan error<br><br>Add dummy PMC pci driver to avoid coverity scan error.<br><br>Bug:CID 1379849<br><br>Change-Id: Ica19735307736c8a55c29af88db8b1372f8779e4<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/Makefile.inc<br>A src/soc/intel/cannonlake/pmc.c<br>2 files changed, 39 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/21155/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 10d444b..e1a37f3 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -27,6 +27,7 @@<br> ramstage-y += chip.c<br> ramstage-y += gspi.c<br> ramstage-y += memmap.c<br>+ramstage-y += pmc.c<br> ramstage-y += pmutil.c<br> ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c<br> ramstage-y += spi.c<br>diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c<br>new file mode 100644<br>index 0000000..9043805<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/pmc.c<br>@@ -0,0 +1,38 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pci_ids.h><br>+#include <soc/ramstage.h><br>+<br>+static struct device_operations device_ops = {<br>+   .read_resources         = &pci_dev_read_resources,<br>+       .set_resources          = &pci_dev_set_resources,<br>+        .enable_resources       = &pci_dev_enable_resources,<br>+};<br>+<br>+static const unsigned short pci_device_ids[] = {<br>+  PCI_DEVICE_ID_INTEL_CNL_PMC,<br>+ 0<br>+};<br>+<br>+static const struct pci_driver pch_lpc __pci_driver = {<br>+  .ops     = &device_ops,<br>+  .vendor  = PCI_VENDOR_ID_INTEL,<br>+      .devices = pci_device_ids,<br>+};<br></pre><p>To view, visit <a href="https://review.coreboot.org/21155">change 21155</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21155"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ica19735307736c8a55c29af88db8b1372f8779e4 </div>
<div style="display:none"> Gerrit-Change-Number: 21155 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>