<p>John Zhao would like John Zhao to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/21139">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">src/mainboard/intel/cannonlake: Add gpio support for cannonlake<br><br>Add gpio pins configuration for cannonlake rvp u/y boards.<br><br>Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc<br>Signed-off-by: john zhao <john.zhao@intel.com><br>---<br>M src/mainboard/intel/cannonlake_rvp/Kconfig<br>M src/mainboard/intel/cannonlake_rvp/Makefile.inc<br>A src/mainboard/intel/cannonlake_rvp/bootblock.c<br>A src/mainboard/intel/cannonlake_rvp/chromeos.c<br>A src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc<br>A src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c<br>A src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h<br>A src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h<br>A src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variants/gpio.h<br>A src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h<br>10 files changed, 548 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/21139/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig<br>index c59abcf..7715b72 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/Kconfig<br>+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig<br>@@ -4,6 +4,7 @@<br> def_bool y<br> select BOARD_ROMSIZE_KB_16384<br> select SOC_INTEL_CANNONLAKE<br>+ select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS<br> select GENERIC_SPD_BIN<br> <br> config MAINBOARD_DIR<br>diff --git a/src/mainboard/intel/cannonlake_rvp/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/Makefile.inc<br>index dd8303f..91820b2 100644<br>--- a/src/mainboard/intel/cannonlake_rvp/Makefile.inc<br>+++ b/src/mainboard/intel/cannonlake_rvp/Makefile.inc<br>@@ -16,5 +16,10 @@<br> <br> subdirs-y += spd<br> <br>+bootblock-y += bootblock.c<br>+<br>+subdirs-y += variants/baseboard<br>+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include<br>+<br> subdirs-y += variants/$(VARIANT_DIR)<br> CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include<br>diff --git a/src/mainboard/intel/cannonlake_rvp/bootblock.c b/src/mainboard/intel/cannonlake_rvp/bootblock.c<br>new file mode 100644<br>index 0000000..781273f<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/bootblock.c<br>@@ -0,0 +1,28 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <baseboard/variants.h><br>+#include <bootblock_common.h><br>+#include <soc/gpio.h><br>+#include <variant/gpio.h><br>+<br>+void bootblock_mainboard_init(void)<br>+{<br>+ const struct pad_config *pads;<br>+ size_t num;<br>+<br>+ pads = variant_early_gpio_table(&num);<br>+ gpio_configure_pads(pads, num);<br>+}<br>diff --git a/src/mainboard/intel/cannonlake_rvp/chromeos.c b/src/mainboard/intel/cannonlake_rvp/chromeos.c<br>new file mode 100644<br>index 0000000..6067aed<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/chromeos.c<br>@@ -0,0 +1,65 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/acpi.h><br>+#include <baseboard/variants.h><br>+#include <gpio.h><br>+#include <rules.h><br>+#include <soc/gpio.h><br>+#include <vendorcode/google/chromeos/chromeos.h><br>+<br>+#include <variant/gpio.h><br>+<br>+#if ENV_RAMSTAGE<br>+#include <boot/coreboot_tables.h><br>+<br>+void fill_lb_gpios(struct lb_gpios *gpios)<br>+{<br>+ struct lb_gpio chromeos_gpios[] = {<br>+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},<br>+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},<br>+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},<br>+ {-1, ACTIVE_HIGH, 0, "power"},<br>+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},<br>+ };<br>+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));<br>+}<br>+#endif /* ENV_RAMSTAGE */<br>+<br>+int get_lid_switch(void)<br>+{<br>+ /* Lid always open */<br>+ return 1;<br>+}<br>+<br>+int get_recovery_mode_switch(void)<br>+{<br>+ return 0;<br>+}<br>+<br>+int get_write_protect_state(void)<br>+{<br>+ /* No write protect */<br>+ return 0;<br>+}<br>+<br>+void mainboard_chromeos_acpi_generate(void)<br>+{<br>+ const struct cros_gpio *gpios;<br>+ size_t num;<br>+<br>+ gpios = variant_cros_gpios(&num);<br>+ chromeos_acpi_gpio_generate(gpios, num);<br>+}<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc<br>new file mode 100644<br>index 0000000..9fb63f5<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/Makefile.inc<br>@@ -0,0 +1,3 @@<br>+bootblock-y += gpio.c<br>+<br>+ramstage-y += gpio.c<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c<br>new file mode 100644<br>index 0000000..7c0909e<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c<br>@@ -0,0 +1,348 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <baseboard/gpio.h><br>+#include <baseboard/variants.h><br>+#include <commonlib/helpers.h><br>+<br>+/* Pad configuration in ramstage*/<br>+static const struct pad_config gpio_table[] = {<br>+ /* GPPC */<br>+ /* A0 : RCINB_TIME_SYNC_1 */<br>+ /* A1 : ESPI_IO_0 */<br>+ /* A2 : ESPI_IO_1 */<br>+ /* A3 : ESPI_IO_2 */<br>+ /* A4 : ESPI_IO_3 */<br>+ /* A5 : ESPI_CSB */<br>+ /* A6 : SERIRQ */<br>+ /* A7 : PRIQAB_GSP10_CS1B */<br>+ PAD_CFG_GPI_ACPI_SCI(GPP_A7, 20K_PU, PLTRST, NONE),<br>+ /* A8 : CLKRUNB */<br>+#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)<br>+ PAD_CFG_GPO(GPP_A8, 1, PLTRST),<br>+#endif<br>+ /* A9 : CLKOUT_LPC_0_ESPI_CLK */<br>+ /* A10 : CLKOUT_LPC_1 */<br>+ /* A11 : PMEB_GSP11_CS1B */<br>+ PAD_CFG_GPI_SCI_LOW(GPP_A11, 20K_PU, DEEP, LEVEL),<br>+ /* A12 : BM_BUSYB_ISH__GP_6 */<br>+ /* A13 : SUSWARNB_SUSPWRDNACK */<br>+ PAD_CFG_GPO(GPP_A13, 1, PLTRST),<br>+ /* A14 : SUS_STATB_ESPI_RESETB */<br>+ /* A15 : SUSACKB */<br>+ PAD_CFG_GPO(GPP_A15, 1, PLTRST),<br>+ /* A16 : SD_1P8_SEL */<br>+ PAD_CFG_GPO(GPP_A16, 0, PLTRST),<br>+ /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */<br>+ /* A18 : ISH_GP_0 */<br>+ PAD_CFG_NF(GPP_A18, 20K_PU, DEEP, GPIO),<br>+ /* A19 : ISH_GP_1 */<br>+ PAD_CFG_NF(GPP_A18, 20K_PU, DEEP, GPIO),<br>+ /* A20 : ISH_GP_2 */<br>+ PAD_CFG_NF(GPP_A18, 20K_PU, DEEP, GPIO),<br>+ /* A21 : ISH_GP_3 */<br>+ PAD_CFG_NF(GPP_A18, 20K_PU, DEEP, GPIO),<br>+ /* A22 : ISH_GP_4 */<br>+ PAD_CFG_NF(GPP_A23, 20K_PU, DEEP, GPIO),<br>+ /* A23 : ISH_GP_5 */<br>+ PAD_CFG_NF(GPP_A23, 20K_PU, DEEP, GPIO),<br>+<br>+ /* B0 : CORE_VID_0 */<br>+ /* B1 : CORE_VID_1 */<br>+ /* B2 : VRALERTB */<br>+ PAD_CFG_GPI_APIC(GPP_B2, NONE, DEEP),<br>+ /* B3 : CPU_GP_2 */<br>+ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),<br>+ /* B4 : CPU_GP_3 */<br>+ PAD_CFG_GPO(GPP_B4, 1, DEEP),<br>+ /* B5 : SRCCLKREQB_0 */<br>+ /* B6 : SRCCLKREQB_1 */ <br>+ /* B7 : SRCCLKREQB_2 */ <br>+ /* B8 : SRCCLKREQB_3 */ <br>+ /* B9 : SRCCLKREQB_4 */ <br>+ /* B10 : SRCCLKREQB_5 */ <br>+ /* B11 : EXT_PWR_GATEB */<br>+#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)<br>+ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),<br>+#else<br>+ PAD_CFG_GPO(GPP_B11, 1, PLTRST),<br>+#endif<br>+ /* B12 : SLP_S0B */<br>+ /* B13 : PLTRSTB */<br>+ /* B14 : SPKR */<br>+ PAD_CFG_GPO(GPP_B14, 1, PLTRST),<br>+ /* B15 : GSPI0_CS0B */<br>+ PAD_CFG_NF(GPP_B15, NONE, DEEP, GPIO),<br>+ /* B16 : GSPI0_CLK */<br>+ PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST),<br>+ /* B17 : GSPI0_MISO */<br>+ PAD_CFG_GPO(GPP_B17, 1, PLTRST),<br>+ /* B18 : GSPI0_MOSI */<br>+ PAD_CFG_GPO(GPP_B18, 1, PLTRST),<br>+ /* B19 : GSPI1_CS0B */<br>+ /* B20 : GSPI1_CLK_NFC_CLK */<br>+ /* B21 : GSPI1_MISO_NFC_CLKREQ */<br>+ /* B22 : GSP1_MOSI */<br>+ /* B23 : SML1ALERTB_PCHHOTB */<br>+ PAD_CFG_GPO(GPP_B23, 1, DEEP),<br>+<br>+ /* C0 : SMBCLK */<br>+ /* C1 : SMBDATA */<br>+ /* C2 : SMBALERTB */<br>+ PAD_CFG_GPO(GPP_C2, 1, DEEP),<br>+ /* C3 : SML0CLK */<br>+ /* C4 : SML0DATA */<br>+ /* C5 : SML0ALERTB */<br>+ PAD_CFG_GPI_SCI_LOW(GPP_C5, NONE, DEEP, LEVEL),<br>+ /* C6 : SML1CLK */<br>+ /* C7 : SML1DATA */<br>+ /* C8 : UART0_RXD */<br>+ PAD_CFG_GPI_APIC_INVERT(GPP_C8, 20K_PU, DEEP),<br>+ /* C9 : UART0_TXD */<br>+ PAD_CFG_GPI_SCI_LOW(GPP_C9, 20K_PU, PLTRST, EDGE_SINGLE),<br>+ /* C10 : UART0_RTSB */<br>+ PAD_CFG_GPO(GPP_C10, 0, PLTRST),<br>+ /* C11 : UART0_CTSB */<br>+ PAD_CFG_GPI_SCI_LOW(GPP_C11, 20K_PU, DEEP, LEVEL),<br>+ /* C12 : UART1_RXD_ISH_UART1_RXD */<br>+ PAD_CFG_GPO(GPP_C12, 1, PLTRST),<br>+ /* C13 : UART1_RXD_ISH_UART1_TXD */<br>+ /* C14 : UART1_RXD_ISH_UART1_RTSB */<br>+ /* C15 : UART1_RXD_ISH_UART1_CTSB */<br>+ PAD_CFG_GPO(GPP_C15, 1, PLTRST),<br>+ /* C16 : I2C0_SDA */<br>+ /* C17 : I2C0_SCL */<br>+ /* C18 : I2C1_SDA */<br>+ /* C19 : I2C1_SCL */<br>+ /* C20 : UART2_RXD */<br>+ /* C21 : UART2_TXD */<br>+ /* C22 : UART2_RTSB */<br>+ /* C23 : UART2_CTSB */<br>+ <br>+ /* D0 : SPI1_CSB_BK_0 */<br>+ /* D1 : SPI1_CLK_BK_1 */<br>+ /* D2 : SPI1_MISO_IO_1_BK_2 */<br>+ /* D3 : SPI1_MOSI_IO_0_BK_3 */<br>+ /* D4 : IMGCLKOUT_0_BK_4 */<br>+ /* D5 : ISH_I2C0_SDA */<br>+ /* D6 : ISH_I2C0_SCL */<br>+ /* D7 : ISH_I2C1_SDA */<br>+ /* D8 : ISH_I2C1_SCL */<br>+ /* D9 : ISH_SPI_CSB */<br>+ PAD_CFG_GPO(GPP_D9, 1, PLTRST),<br>+ /* D10 : ISH_SPI_CLK */<br>+ PAD_CFG_GPI_APIC(GPP_D10, NONE, PLTRST),<br>+ /* D11 : ISH_SPI_MISO_GP_BSSB_CLK */<br>+ PAD_CFG_GPI_SCI_LOW(GPP_D11, NONE, DEEP, LEVEL),<br>+ /* D12 : ISH_SPI_MOSI_GP_BSSB_DI */<br>+ /* D13 : ISH_UART0_RXD_SML0BDATA */<br>+ PAD_CFG_GPO(GPP_D13, 1, DEEP),<br>+ /* D14 : ISH_UART0_TXD_SML0BCLK */<br>+ PAD_CFG_GPO(GPP_D14, 1, PLTRST),<br>+ /* D15 : ISH_UART0_RTSB_GPSPI2_CS1B */<br>+ /* D16 : ISH_UART0_CTSB_SML0BALERTB */<br>+ PAD_CFG_GPI_SCI_HIGH(GPP_D16, NONE, DEEP, LEVEL),<br>+ /* D17 : DMIC_CLK_1_SNDW3_CLK */<br>+ /* D18 : DMIC_DATA_1_SNDW3_DATA */<br>+ /* D19 : DMIC_CLK_0_SNDW4_CLK */<br>+ /* D20 : DMIC_DATA_0_SNDW4_DATA */<br>+ /* D21 : SPI1_IO_2 */<br>+ PAD_CFG_NF(GPP_D21, NONE, PLTRST, NF1),<br>+ /* D22 : SPI1_IO_3 */<br>+ PAD_CFG_NF(GPP_D22, NONE, PLTRST, NF1),<br>+ /* D23 : SPP_MCLK */<br>+<br>+ /* E0 : SATAXPCIE_0_SATAGP_0 */<br>+#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)<br>+ PAD_CFG_NF(GPP_E0, 20K_PU, DEEP, NF1),<br>+#endif<br>+ /* E1 : SATAXPCIE_1_SATAGP_1 */<br>+ /* E2 : SATAXPCIE_2_SATAGP_2 */<br>+ PAD_CFG_GPI_APIC(GPP_E2, 20K_PU, PLTRST),<br>+ /* E3 : CPU_GP_0 */<br>+ PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),<br>+ /* E4 : SATA_DEVSLP_0 */<br>+#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)<br>+ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1),<br>+#else<br>+ PAD_CFG_GPI_SCI_HIGH(GPP_E4, NONE, PLTRST, LEVEL),<br>+#endif<br>+ /* E5 : SATA_DEVSLP_1 */<br>+ /* E6 : SATA_DEVSLP_2 */<br>+#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)<br>+ PAD_CFG_GPI_ACPI_SCI(GPP_E6, NONE, DEEP, NONE),<br>+#endif<br>+ /* E7 : CPU_GP_1 */<br>+ //PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, EDGE, NONE),<br>+ /* E8 : SATA_LEDB */<br>+ /* E9 : USB2_OCB_0_GP_BSSB_CLK */<br>+ /* E10 : USB2_OCB_1_GP_BSSB_DI */<br>+ /* E11 : USB2_OCB_2 */<br>+ /* E12 : USB2_OCB_3 */<br>+ /* E13 : DDSP_HPD_0_DISP_MISC_0 */<br>+ /* E14 : DDSP_HPD_0_DISP_MISC_1 */<br>+ /* E15 : DDSP_HPD_0_DISP_MISC_2 */<br>+ /* E16 : DDSP_HPD_0_DISP_MISC_3 */<br>+#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)<br>+ PAD_CFG_GPO(GPP_E16, 1, DEEP),<br>+#else<br>+ PAD_CFG_GPI_SCI_HIGH(GPP_E16, NONE, DEEP, LEVEL),<br>+#endif<br>+ /* E17 : EDP_HPD_DISP_MISC_4 */<br>+ /* E18 : DDPB_CTRLCLK */<br>+ /* E19 : DDPB_CTRLDATA */<br>+ /* E20 : DDPC_CTRLCLK */<br>+ /* E21 : DDPC_CTRLDATA */<br>+ /* E22 : DDPD_CTRLCLK */<br>+ /* E23 : DDPD_CTRLDATA */<br>+<br>+ /* F0 : CNV_GNSS_PA_BLANKING */<br>+ PAD_CFG_NF(GPP_F0, NONE, DEEP, GPIO),<br>+ /* F1 : CNV_GNSS_FAT */<br>+ PAD_CFG_TERM_GPO(GPP_F1, 1, 20K_PU, DEEP),<br>+ /* F2 : CNV_GNSS_SYSCK */<br>+ PAD_CFG_TERM_GPO(GPP_F2, 1, 20K_PU, PLTRST),<br>+ /* F3 : GPP_F_3 */<br>+ PAD_CFG_TERM_GPO(GPP_F3, 0, 20K_PU, PLTRST),<br>+ /* F4 : CNV_BRI_DT_UART0_RTSB */<br>+ PAD_CFG_NF(GPP_F4, 20K_PU, DEEP, GPIO),<br>+ /* F5 : CNV_BRI_RSP_UART0_RXD */<br>+ PAD_CFG_NF(GPP_F5, 20K_PU, DEEP, GPIO),<br>+ /* F6 : CNV_RGI_DT_UART0_TXD */<br>+ PAD_CFG_NF(GPP_F6, 20K_PU, DEEP, GPIO),<br>+ /* F7 : CNV_RGI_DT_RSP_UART9_CTSB */<br>+ PAD_CFG_NF(GPP_F7, 20K_PU, DEEP, GPIO),<br>+ /* F8 : CNV_MFUART2_RXD */<br>+ PAD_CFG_NF(GPP_F8, 20K_PU, DEEP, NF1),<br>+ /* F9 : CNV_MFUART2_TXD */<br>+ PAD_CFG_NF(GPP_F9, 20K_PU, DEEP, NF1),<br>+ /* F10 : GPP_F_10 */<br>+#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)<br>+ PAD_CFG_GPO(GPP_F10, 1, DEEP),<br>+#endif<br>+ PAD_CFG_GPI_APIC(GPP_F11, 20K_PU, PLTRST),<br>+ /* F11 : EMMC_CMD */<br>+ /* F12 : EMMC_DATA0 */<br>+ /* F13 : EMMC_DATA1 */<br>+ /* F14 : EMMC_DATA2 */<br>+ /* F15 : EMMC_DATA3 */<br>+ /* F16 : EMMC_DATA4 */<br>+ /* F17 : EMMC_DATA5 */<br>+ /* F18 : EMMC_DATA6 */<br>+ /* F19 : EMMC_DATA9 */<br>+ /* F20 : EMMC_RCLK */<br>+ /* F21 : EMMC_CLK */<br>+ /* F22 : EMMC_RESETB */<br>+ /* F23 : EMMC_PRESENT */<br>+#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)<br>+ PAD_CFG_GPI(GPP_F23, 20K_PU, DEEP),<br>+#endif<br>+ /* G0 : SD3_D2 */<br>+ /* G1 : SD3_D0_SD4_RCLK_P */<br>+ /* G2 : SD3_D1_SD4_RCLK_N */<br>+ /* G3 : SD3_D2 */<br>+ /* G4 : SD3_D3 */<br>+ /* G5 : SD3_CDB */<br>+ PAD_CFG_NF(GPP_G5, 20K_PU, DEEP, GPIO),<br>+ /* G6 : SD3_CLK */<br>+ /* G7 : SD3_WP */<br>+ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, GPIO), <br>+<br>+ /* H0 : SSP2_SCLK */<br>+ PAD_CFG_NF(GPP_H0, 20K_PU, DEEP, GPIO),<br>+ /* H1 : SSP2_SFRM */<br>+ PAD_CFG_NF(GPP_H1, 20K_PU, DEEP, GPIO),<br>+ /* H2 : SSP2_TXD */<br>+ PAD_CFG_NF(GPP_H2, 20K_PU, DEEP, GPIO),<br>+ /* H3 : SSP2_RXD */<br>+ PAD_CFG_NF(GPP_H3, 20K_PU, DEEP, GPIO),<br>+ /* H4 : I2C2_SDA */<br>+ /* H5 : I2C2_SCL */<br>+ /* H6 : I2C3_SDA */<br>+ /* H7 : I2C3_SCL */<br>+ /* H8 : I2C4_SDA */<br>+ /* H9 : I2C4_SCL */<br>+ /* H10 : I2C5_SDA_ISH_I2C2_SDA */<br>+ PAD_CFG_GPO(GPP_H10, 1, PLTRST),<br>+ /* H11 : I2C5_SCL_ISH_I2C2_SCL */<br>+ PAD_CFG_GPO(GPP_H11, 1, PLTRST),<br>+ /* H12 : M2_SKT2_CFG_0_DFLEXIO_0 */<br>+ PAD_CFG_GPO(GPP_H12, 1, PLTRST),<br>+ /* H13 : M2_SKT2_CFG_1_DFLEXIO_1 */<br>+ PAD_CFG_GPO(GPP_H13, 1, PLTRST),<br>+ /* H14 : M2_SKT2_CFG_2 */<br>+ PAD_CFG_GPO(GPP_H14, 0, PLTRST),<br>+ /* H15 : M2_SKT2_CFG_3 */<br>+ PAD_CFG_GPO(GPP_H15, 1, PLTRST),<br>+ /* H16 : DDPF_CTRLCLK */<br>+#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)<br>+ PAD_CFG_GPO(GPP_H16, 1, DEEP),<br>+#endif<br>+ /* H17 : DDPF_CTRLDATA */<br>+#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY)<br>+ PAD_CFG_GPO(GPP_H17, 1, DEEP),<br>+#endif<br>+ /* H18 : BOOTMPC */<br>+ /* H19 : TIMESYNC_0 */<br>+ PAD_CFG_GPO(GPP_H19, 1, PLTRST),<br>+ /* H20 : IMGCLKOUT_1 */<br>+ /* H21 : GPPC_H_21 */<br>+ /* H22 : GPPC_H_22 */<br>+ PAD_CFG_GPO(GPP_H22, 1, PLTRST),<br>+ /* H23 : GPPC_H_23 */<br>+<br>+ /* GPD */<br>+ /* GPD_0 : BATLOWB */<br>+ /* GPD_1 : ACPRESENT */<br>+ /* GPD_2 : LAN_WAKEB */<br>+ /* GPD_3 : PWRBTNB */<br>+ /* GPD_4 : SLP_S3B */<br>+ /* GPD_5 : SLP_S4B */<br>+ /* GPD_6 : SLP_AB */<br>+ /* GPD_7 : GPD_7 */<br>+ /* GPD-8 : SUSCLK */<br>+ /* GPD-9 : SLP_WLANB */<br>+ /* GPD-10 : SLP_5B */<br>+ /* GPD_11 : LANPHYPC */<br>+};<br>+<br>+/* Early pad configuration in bootblock */<br>+static const struct pad_config early_gpio_table[] = {<br>+<br>+<br>+};<br>+<br>+const struct pad_config *__attribute__((weak)) variant_gpio_table(size_t *num)<br>+{<br>+ *num = ARRAY_SIZE(gpio_table);<br>+ return gpio_table;<br>+}<br>+<br>+const struct pad_config *__attribute__((weak))<br>+ variant_early_gpio_table(size_t *num)<br>+{<br>+ *num = ARRAY_SIZE(early_gpio_table);<br>+ return early_gpio_table;<br>+}<br>+<br>+static const struct cros_gpio cros_gpios[] = {<br>+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),<br>+};<br>+<br>+const struct cros_gpio * __attribute__((weak)) variant_cros_gpios(size_t *num)<br>+{<br>+ *num = ARRAY_SIZE(cros_gpios);<br>+ return cros_gpios;<br>+}<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h<br>new file mode 100644<br>index 0000000..323a904<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/gpio.h<br>@@ -0,0 +1,21 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __BASEBOARD_GPIO_H__<br>+#define __BASEBOARD_GPIO_H__<br>+<br>+#include <soc/gpio.h><br>+<br>+#endif /* __BASEBOARD_GPIO_H__ */<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h<br>new file mode 100644<br>index 0000000..19dfc89<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/include/baseboard/variants.h<br>@@ -0,0 +1,33 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __BASEBOARD_VARIANTS_H__<br>+#define __BASEBOARD_VARIANTS_H__<br>+<br>+#include <soc/gpio.h><br>+#include <stdint.h><br>+#include <vendorcode/google/chromeos/chromeos.h><br>+<br>+/* <br>+ * The next set of functions return the gpio table and fill in the number of<br>+ * entries for each table. <br>+ */<br>+const struct pad_config *variant_gpio_table(size_t *num);<br>+const struct pad_config *variant_early_gpio_table(size_t *num);<br>+<br>+const struct cros_gpio *variant_cros_gpios(size_t *num);<br>+<br>+<br>+#endif /*__BASEBOARD_VARIANTS_H__ */<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variants/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variants/gpio.h<br>new file mode 100644<br>index 0000000..6c824b3<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/include/variants/gpio.h<br>@@ -0,0 +1,22 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __MAINBOARD_GPIO_H__<br>+#define __MAINBOARD_GPIO_H__<br>+<br>+#include <baseboard/gpio.h><br>+<br>+#endif /* __MAINBOARD_GPIO_H__ */<br>+<br>diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h<br>new file mode 100644<br>index 0000000..6c824b3<br>--- /dev/null<br>+++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/include/variant/gpio.h<br>@@ -0,0 +1,22 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#ifndef __MAINBOARD_GPIO_H__<br>+#define __MAINBOARD_GPIO_H__<br>+<br>+#include <baseboard/gpio.h><br>+<br>+#endif /* __MAINBOARD_GPIO_H__ */<br>+<br></pre><p>To view, visit <a href="https://review.coreboot.org/21139">change 21139</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21139"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia077a070979401fe7bd23bda110d2b66a038d9fc </div>
<div style="display:none"> Gerrit-Change-Number: 21139 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: John Zhao <john.zhao@intel.corp-partner.google.com> </div>
<div style="display:none"> Gerrit-Reviewer: John Zhao <john.zhao@intel.com> </div>