<p>Subrata Banik has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21150">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Usable dram top calculation based on HW registers<br><br>This patch ensures that entire system memory calculation is done<br>based on host bridge registers.<br><br>BRANCH=none<br>BUG=b:63974384<br>TEST=Build and boot eve and poppy successfully with below configurations<br>1. Booting to OS with no UPD change<br>2. Enable ProbelessTrace UPD and boot to OS.<br>3. Enable PRMRR with size 1MB and boot to OS.<br>4. Enable PRMRR with size 32MB and boot to OS.<br>5. Enable PRMRR with size 2MB and unable to boot to OS due to<br>unsupported PRMRR size.<br><br>Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d<br>Signed-off-by: Subrata Banik <subrata.banik@intel.com><br>---<br>M src/soc/intel/skylake/include/soc/iomap.h<br>M src/soc/intel/skylake/memmap.c<br>2 files changed, 89 insertions(+), 24 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/21150/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h<br>index 52ef640..a7c159a 100644<br>--- a/src/soc/intel/skylake/include/soc/iomap.h<br>+++ b/src/soc/intel/skylake/include/soc/iomap.h<br>@@ -59,6 +59,15 @@<br> /* CPU Trace reserved memory size */<br> #define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */<br> <br>+/* Probeless Trace memory size */<br>+#define GDXC_MOT_MEMORY_SIZE 0x6000000 /* 96MiB */<br>+#define GDXC_IOT_MEMORY_SIZE 0x2000000 /* 32MiB */<br>+#define PSMI_BUFFER_AREA_SIZE 0x4000000 /* 64MiB */<br>+<br>+/* PTT registers */<br>+#define PTT_TXT_BASE_ADDRESS 0xfed30800<br>+#define PTT_PRESENT 0x00070000<br>+<br> /*<br> * I/O port address space<br> */<br>diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c<br>index 43faabb..34d2e10 100644<br>--- a/src/soc/intel/skylake/memmap.c<br>+++ b/src/soc/intel/skylake/memmap.c<br>@@ -17,8 +17,10 @@<br> #include <arch/io.h><br> #include <cbmem.h><br> #include <chip.h><br>+#include <console/console.h><br> #include <device/device.h><br> #include <device/pci.h><br>+#include <intelblocks/systemagent.h><br> #include <soc/msr.h><br> #include <soc/pci_devs.h><br> #include <soc/smm.h><br>@@ -106,6 +108,15 @@<br> return 0;<br> }<br> <br>+static bool is_ptt_enable(void)<br>+{<br>+ if ((read32((void *)PTT_TXT_BASE_ADDRESS) & PTT_PRESENT) ==<br>+ PTT_PRESENT)<br>+ return true;<br>+<br>+ return false;<br>+}<br>+<br> /*<br> * Host Memory Map:<br> *<br>@@ -125,6 +136,8 @@<br> * | PRM (C6DRAM/SGX) |<br> * +--------------------------+ PRMRR<br> * | Trace Memory |<br>+ * +--------------------------+ Probless Trace<br>+ * | PTT |<br> * +--------------------------+ top_of_ram<br> * | Reserved - FSP/CBMEM |<br> * +--------------------------+ TOLUM<br>@@ -136,41 +149,84 @@<br> * the base registers from each other to determine sizes of the regions. In<br> * other words, the memory map is in a fixed order no matter what.<br> */<br>+static u32 calculate_dram_base(void)<br>+{<br>+ const struct soc_intel_skylake_config *config;<br>+ const struct device *dev;<br>+ uint32_t tolud_base;<br>+ uint32_t dram_base;<br>+ uint32_t prmrr_base;<br>+ size_t prmrr_size;<br> <br>+ dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));<br>+<br>+ /* Read TOLUD from Host Bridge offset */<br>+ dram_base = tolud_base = sa_get_tolud_base();<br>+<br>+ if (dev->enabled) {<br>+ /* Read BDSM from Host Bridge */<br>+ dram_base -= sa_get_dsm_size();<br>+<br>+ /* Read BGSM from Host Bridge */<br>+ dram_base -= sa_get_gsm_size();<br>+ }<br>+ /* Get TSEG size */<br>+ dram_base -= smm_region_size();<br>+<br>+ /* Get DPR size */<br>+ if (IS_ENABLED(CONFIG_SA_ENABLE_DPR))<br>+ dram_base -= sa_get_dpr_size();<br>+<br>+ dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0));<br>+ config = dev->chip_info;<br>+ prmrr_size = config->PrmrrSize;<br>+<br>+ /*<br>+ * PRMRR Sizes that are > 1MB and < 32MB are<br>+ * not supported and will fail out.<br>+ */<br>+ if ((prmrr_size > (1*MiB)) && (prmrr_size < (32*MiB)))<br>+ die("PRMRR Sizes that are > 1MB and < 32MB are not"<br>+ "supported!\n");<br>+<br>+ if (prmrr_size > 0) {<br>+ prmrr_base = dram_base - prmrr_size;<br>+ if (prmrr_size >= 32*MiB)<br>+ /* Make 128 MB align code */<br>+ prmrr_base &= ~(128*MiB - 1);<br>+ dram_base = prmrr_base;<br>+ }<br>+<br>+ if (config->ProbelessTrace) {<br>+ /* GDXC MOT */<br>+ dram_base -= GDXC_MOT_MEMORY_SIZE;<br>+ /* Round down to natual boundary accroding to PSMI size */<br>+ dram_base &= ~(PSMI_BUFFER_AREA_SIZE - 1);<br>+ /* GDXC IOT */<br>+ dram_base -= GDXC_IOT_MEMORY_SIZE;<br>+ /* PSMI buffer area */<br>+ dram_base -= PSMI_BUFFER_AREA_SIZE;<br>+ }<br>+<br>+ if (is_ptt_enable())<br>+ dram_base -= 4*KiB; /* Allocate 4KB for PTT if enable */<br>+<br>+ return dram_base;<br>+}<br>+<br>+/* Get usable system memory start address */<br> static u32 top_of_32bit_ram(void)<br> {<br>- msr_t prmrr_base;<br>- u32 top_of_ram;<br>- const struct device *dev;<br>- const struct soc_intel_skylake_config *config;<br>-<br> /*<br> * Check if Tseg has been initialized, we will use this as a flag<br> * to check if the MRC is done, and only then continue to read the<br> * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before<br> * PRMRR_MASK MSR lock bit is set.<br> */<br>- top_of_ram = smm_region_start();<br>- if (top_of_ram == 0)<br>+ if (smm_region_start() == 0)<br> return 0;<br> <br>- dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0));<br>- config = dev->chip_info;<br>-<br>- /*<br>- * On Skylake, cbmem_top is offset down from PRMRR_BASE by reserved<br>- * memory (128MiB) for CPU trace if enabled, then reserved memory (4KB)<br>- * for PTT if enabled. PTT is in fact not used on Skylake platforms.<br>- * Refer to Fsp Integration Guide for the memory mapping layout.<br>- */<br>- prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR);<br>- if (prmrr_base.lo)<br>- top_of_ram = prmrr_base.lo;<br>-<br>- if (config->ProbelessTrace)<br>- top_of_ram -= TRACE_MEMORY_SIZE;<br>-<br>- return top_of_ram;<br>+ return calculate_dram_base();<br> }<br> <br> void *cbmem_top(void)<br></pre><p>To view, visit <a href="https://review.coreboot.org/21150">change 21150</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d </div>
<div style="display:none"> Gerrit-Change-Number: 21150 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Subrata Banik <subrata.banik@intel.com> </div>