<p>Naresh Solanki would like Rizwan Qureshi to <strong>review</strong> this change.</p><p><a href="https://review.coreboot.org/20741">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mb/google/soraka: Camera PMIC runtime power control<br><br>Currently PMIC(tps68470) is in active state even when cameras are not<br>in use. PMIC is put into SLEEP mode only when entering S3 via<br>smihandler.<br><br>With this change PMIC will be put into SLEEP mode as soon as sensors &<br>VCM voltage outputs are turned off. This will allow runtime power saving when<br>camera is not in use.<br><br>PMIC will be reset in first boot & not in S3 & S0ix resume.<br><br>Also remove the smihandler for PMIC power management & handle it as part<br>of sensor and VCM ACPI PowerResource.<br><br>BUG=b:63903239<br>TEST= Build for Saraka. Check Camera probe, Capture image before & after<br>S3 & S0ix resume.<br><br>Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0<br>Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com><br>Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com><br>---<br>M src/mainboard/google/poppy/acpi/mipi_camera.asl<br>M src/mainboard/google/poppy/smihandler.c<br>M src/mainboard/google/poppy/variants/soraka/gpio.c<br>3 files changed, 52 insertions(+), 8 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/20741/8</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/poppy/acpi/mipi_camera.asl b/src/mainboard/google/poppy/acpi/mipi_camera.asl<br>index 5c75122..68122a6 100644<br>--- a/src/mainboard/google/poppy/acpi/mipi_camera.asl<br>+++ b/src/mainboard/google/poppy/acpi/mipi_camera.asl<br>@@ -27,6 +27,55 @@<br>                       Return (0x0F)<br>                 }<br> <br>+         Method (PMON, 0, Serialized) {<br>+                       /*<br>+                    * Turn on 3V3_VDD. It takes around 1 ms<br>+                      * for volatge to settle to 3.3 Volt.<br>+                         * Provide additional 2 ms before we<br>+                  * enable regulators.<br>+                         */<br>+                  STXS(EN_PP3300_DX_CAM)<br>+                       Sleep (3)<br>+            }<br>+<br>+         Method (PMOF, 0, Serialized) {<br>+                       /*<br>+                    * Make Sure all PMIC outputs are off.<br>+                        */<br>+                  If (LEqual (VSIC, Zero)) {<br>+                           CTXS(EN_PP3300_DX_CAM)<br>+                       }<br>+            }<br>+<br>+         Name (_PR0, Package (0x01) { CPMC })<br>+         Name (_PR3, Package (0x01) { CPMC })<br>+<br>+              /* Power resource methods for PMIC */<br>+                PowerResource (CPMC, 0, 0) {<br>+                 Name (RSTO, 1)<br>+                       Method (_ON, 0, Serialized) {<br>+                        /*<br>+                    * Reset PMIC once during first boot.<br>+                         * This reset is avoided in S3 & S0ix resume.<br>+                     */<br>+                  if (Lequal (RSTO, 1))<br>+                        {<br>+                            CTXS(EN_CAM_PMIC_RST_L)<br>+                              Sleep(1)<br>+                             STXS(EN_CAM_PMIC_RST_L)<br>+                              RSTO = 0<br>+                     }<br>+                    PMON()<br>+                       }<br>+                    Method (_OFF, 0, Serialized) {<br>+                               PMOF()<br>+                       }<br>+                    Method (_STA, 0, Serialized) {<br>+                               Local0 = GTXS(EN_PP3300_DX_CAM)<br>+                              Return (Local0)<br>+                      }<br>+            }<br>+<br>          /* Marks the availability of all the operation regions */<br>             Name (AVBL, Zero)<br>             Name (AVGP, Zero)<br>@@ -289,6 +338,7 @@<br>                                                Decrement (VSIC)<br>                                              If (LEqual (VSIC, Zero)) {<br>                                                    VSIO = 0<br>+                                                     PMOF()<br>                                                }<br>                                     }<br>                             } ElseIf (LEqual (Arg0, 1)) {<br>@@ -296,6 +346,7 @@<br>                                    If (LLess (VSIC, 3)) {<br>                                                /* Turn on VSIO */<br>                                            If (LEqual (VSIC, Zero)) {<br>+                                                   PMON()<br>                                                        VSIO = 3<br>                                              }<br>                                             Increment (VSIC)<br>diff --git a/src/mainboard/google/poppy/smihandler.c b/src/mainboard/google/poppy/smihandler.c<br>index 1a86d0f..70d0ab4 100644<br>--- a/src/mainboard/google/poppy/smihandler.c<br>+++ b/src/mainboard/google/poppy/smihandler.c<br>@@ -27,17 +27,10 @@<br>    chromeec_smi_process_events();<br> }<br> <br>-static void mainboard_gpio_smi_sleep(void)<br>-{<br>-       /* Power down camera PMIC */<br>- gpio_set(EN_PP3300_DX_CAM, 0);<br>-}<br>-<br> void mainboard_smi_sleep(u8 slp_typ)<br> {<br>      chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,<br>                      MAINBOARD_EC_S5_WAKE_EVENTS);<br>-        mainboard_gpio_smi_sleep();<br> }<br> <br> int mainboard_smi_apmc(u8 apmc)<br>diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c<br>index 6e0a54f..bf11894 100644<br>--- a/src/mainboard/google/poppy/variants/soraka/gpio.c<br>+++ b/src/mainboard/google/poppy/variants/soraka/gpio.c<br>@@ -143,7 +143,7 @@<br>        /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */<br>       PAD_CFG_GPO(GPP_C10, 1, DEEP),<br>        /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */<br>-       PAD_CFG_GPO(GPP_C11, 1, DEEP),<br>+       PAD_CFG_GPO(GPP_C11, 0, DEEP),<br>        /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */<br>        PAD_CFG_GPI(GPP_C12, NONE, DEEP),<br>     /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */<br></pre><p>To view, visit <a href="https://review.coreboot.org/20741">change 20741</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20741"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0 </div>
<div style="display:none"> Gerrit-Change-Number: 20741 </div>
<div style="display:none"> Gerrit-PatchSet: 8 </div>
<div style="display:none"> Gerrit-Owner: Naresh Solanki <naresh.solanki@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Divagar Mohandass <divagar.mohandass@intel.corp-partner.google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Furquan Shaikh <furquan@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lakshmi G Prasad <lakshmi.g.prasad@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Naresh Solanki <naresh.solanki@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Ricky Liang <jcliang@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Tomasz Figa <tfiga@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: V Sowmya <v.sowmya@intel.com> </div>