<p>Gaggery Tsai has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21147">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/fizz: Enable support for DPTF<br><br>This patch adds the DPTF settings specfic to the mainboard and enables<br>the CPU and other thermal sensors as participant device for fizz.<br>It also enables the DPTF flag in the device tree for fizz.<br><br>BUG=b:64915426<br>BRANCH=None<br>TEST=emerge-fizz coreboot and run DPTF observation tool to make sure<br> DPTF is up and running.<br><br>Change-Id: Ic7d125a763f539158aa425fbba1d8a000a3465ca<br>Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com><br>---<br>M src/mainboard/google/fizz/acpi/dptf.asl<br>M src/mainboard/google/fizz/devicetree.cb<br>2 files changed, 110 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/21147/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/fizz/acpi/dptf.asl b/src/mainboard/google/fizz/acpi/dptf.asl<br>index e69de29..7f8e362 100644<br>--- a/src/mainboard/google/fizz/acpi/dptf.asl<br>+++ b/src/mainboard/google/fizz/acpi/dptf.asl<br>@@ -0,0 +1,107 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2014 Google Inc.<br>+ * Copyright (C) 2015 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#define DPTF_CPU_PASSIVE 85<br>+#define DPTF_CPU_CRITICAL 99<br>+#define DPTF_CPU_ACTIVE_AC0 90<br>+#define DPTF_CPU_ACTIVE_AC1 77<br>+<br>+#define DPTF_TSR0_SENSOR_ID 0<br>+#define DPTF_TSR0_SENSOR_NAME "TMP431_Internal"<br>+#define DPTF_TSR0_PASSIVE 66<br>+#define DPTF_TSR0_CRITICAL 71<br>+#define DPTF_TSR0_ACTIVE_AC0 95<br>+#define DPTF_TSR0_ACTIVE_AC1 85<br>+#define DPTF_TSR0_ACTIVE_AC2 60<br>+#define DPTF_TSR0_ACTIVE_AC3 52<br>+#define DPTF_TSR0_ACTIVE_AC4 44<br>+#define DPTF_TSR0_ACTIVE_AC5 38<br>+#define DPTF_TSR0_ACTIVE_AC6 35<br>+<br>+#define DPTF_ENABLE_FAN_CONTROL<br>+<br>+#ifdef DPTF_ENABLE_FAN_CONTROL<br>+/* DFPS: Fan Performance States */<br>+Name (DFPS, Package () {<br>+ 0, // Revision<br>+ /*<br>+ * TODO : Need to update this Table after characterization.<br>+ * These are initial reference values.<br>+ */<br>+ /* Control, Trip Point, Speed, NoiseLevel, Power */<br>+ Package () {100, 0xFFFFFFFF, 4986, 220, 2200},<br>+ Package () {90, 0xFFFFFFFF, 4804, 180, 1800},<br>+ Package () {80, 0xFFFFFFFF, 4512, 145, 1450},<br>+ Package () {70, 0xFFFFFFFF, 4204, 115, 1150},<br>+ Package () {60, 0xFFFFFFFF, 3838, 90, 900},<br>+ Package () {50, 0xFFFFFFFF, 3402, 65, 650},<br>+ Package () {40, 0xFFFFFFFF, 2904, 45, 450},<br>+ Package () {30, 0xFFFFFFFF, 2337, 30, 300},<br>+ Package () {20, 0xFFFFFFFF, 1608, 15, 150},<br>+ Package () {10, 0xFFFFFFFF, 800, 10, 100},<br>+ Package () {0, 0xFFFFFFFF, 0, 0, 50}<br>+})<br>+<br>+Name (DART, Package () {<br>+ /* Fan effect on CPU */<br>+ 0, // Revision<br>+ Package () {<br>+ /*<br>+ * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,<br>+ * AC7, AC8, AC9<br>+ */<br>+ \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 72, 0, 0, 0, 0, 0,<br>+ 0, 0, 0<br>+ },<br>+ Package () {<br>+ \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 72, 68, 49, 39, 38,<br>+ 37, 0, 0, 0<br>+ }<br>+})<br>+#endif<br>+<br>+Name (DTRT, Package () {<br>+ /* CPU Throttle Effect on CPU */<br>+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },<br>+<br>+ /* CPU Effect on Temp Sensor 0 */<br>+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },<br>+<br>+})<br>+<br>+Name (MPPC, Package ()<br>+{<br>+ 0x2, /* Revision */<br>+ Package () { /* Power Limit 1 */<br>+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */<br>+ 1600, /* PowerLimitMinimum */<br>+ 15000, /* PowerLimitMaximum */<br>+ 1000, /* TimeWindowMinimum */<br>+ 1000, /* TimeWindowMaximum */<br>+ 200 /* StepSize */<br>+ },<br>+ Package () { /* Power Limit 2 */<br>+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */<br>+ 8000, /* PowerLimitMinimum */<br>+ 8000, /* PowerLimitMaximum */<br>+ 1000, /* TimeWindowMinimum */<br>+ 1000, /* TimeWindowMaximum */<br>+ 1000 /* StepSize */<br>+ }<br>+})<br>+<br>+/* Include DPTF */<br>+#include <soc/intel/skylake/acpi/dptf/dptf.asl><br>diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb<br>index bf9f0c9..03e0724 100644<br>--- a/src/mainboard/google/fizz/devicetree.cb<br>+++ b/src/mainboard/google/fizz/devicetree.cb<br>@@ -21,6 +21,9 @@<br> # EC memory map range is 0x900-0x9ff<br> register "gen3_dec" = "0x00fc0901"<br> <br>+ # Enable DPTF<br>+ register "dptf_enable" = "1"<br>+<br> # FSP Configuration<br> register "ProbelessTrace" = "0"<br> register "EnableLan" = "1"<br></pre><p>To view, visit <a href="https://review.coreboot.org/21147">change 21147</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ic7d125a763f539158aa425fbba1d8a000a3465ca </div>
<div style="display:none"> Gerrit-Change-Number: 21147 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Gaggery Tsai <gaggery.tsai@intel.com> </div>