<p>Martin Roth <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/20989">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Arthur Heymans: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">Boards w/ Winbond superios: Use common config entry code<br><br>Six mainboards with Winbond superios directly configure<br>them in romstage.c. All use the common Winbond romstage<br>code. Change them to use the common config entry code to<br>allow for code refactoring such as [1]. Build tested.<br><br>[1] https://review.coreboot.org/20988<br><br>Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562<br>Signed-off-by: Keith Hui <buurin@gmail.com><br>Reviewed-on: https://review.coreboot.org/20989<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net><br>Reviewed-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/asus/a8v-e_deluxe/romstage.c<br>M src/mainboard/asus/a8v-e_se/romstage.c<br>M src/mainboard/ibase/mb899/romstage.c<br>M src/mainboard/msi/ms7260/romstage.c<br>M src/mainboard/msi/ms9652_fam10/romstage.c<br>M src/mainboard/nvidia/l1_2pvv/romstage.c<br>6 files changed, 20 insertions(+), 20 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c<br>index 87fec55..2ead963 100644<br>--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c<br>+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c<br>@@ -94,7 +94,7 @@<br> {<br> u8 reg;<br> <br>- pnp_enter_ext_func_mode(SERIAL_DEV);<br>+ pnp_enter_conf_state(SERIAL_DEV);<br> /* We have 24MHz input. */<br> reg = pnp_read_config(SERIAL_DEV, 0x24);<br> pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));<br>@@ -104,9 +104,9 @@<br> /* We have all RESTOUT and even some reserved bits, too. */<br> reg = pnp_read_config(SERIAL_DEV, 0x2c);<br> pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));<br>- pnp_exit_ext_func_mode(SERIAL_DEV);<br>+ pnp_exit_conf_state(SERIAL_DEV);<br> <br>- pnp_enter_ext_func_mode(ACPI_DEV);<br>+ pnp_enter_conf_state(ACPI_DEV);<br> pnp_set_logical_device(ACPI_DEV);<br> /*<br> * Set the delay rising time from PWROK_LP to PWROK_ST to<br>@@ -117,9 +117,9 @@<br> /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */<br> reg = pnp_read_config(ACPI_DEV, 0xe4);<br> pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));<br>- pnp_exit_ext_func_mode(ACPI_DEV);<br>+ pnp_exit_conf_state(ACPI_DEV);<br> <br>- pnp_enter_ext_func_mode(GPIO_DEV);<br>+ pnp_enter_conf_state(GPIO_DEV);<br> pnp_set_logical_device(GPIO_DEV);<br> /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */<br> pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */<br>@@ -129,7 +129,7 @@<br> pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */<br> pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */<br> pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */<br>- pnp_exit_ext_func_mode(GPIO_DEV);<br>+ pnp_exit_conf_state(GPIO_DEV);<br> }<br> <br> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)<br>diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c<br>index adcf381..d893cf5 100644<br>--- a/src/mainboard/asus/a8v-e_se/romstage.c<br>+++ b/src/mainboard/asus/a8v-e_se/romstage.c<br>@@ -94,7 +94,7 @@<br> {<br> u8 reg;<br> <br>- pnp_enter_ext_func_mode(SERIAL_DEV);<br>+ pnp_enter_conf_state(SERIAL_DEV);<br> /* We have 24MHz input. */<br> reg = pnp_read_config(SERIAL_DEV, 0x24);<br> pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));<br>@@ -104,9 +104,9 @@<br> /* We have all RESTOUT and even some reserved bits, too. */<br> reg = pnp_read_config(SERIAL_DEV, 0x2c);<br> pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));<br>- pnp_exit_ext_func_mode(SERIAL_DEV);<br>+ pnp_exit_conf_state(SERIAL_DEV);<br> <br>- pnp_enter_ext_func_mode(ACPI_DEV);<br>+ pnp_enter_conf_state(ACPI_DEV);<br> pnp_set_logical_device(ACPI_DEV);<br> /*<br> * Set the delay rising time from PWROK_LP to PWROK_ST to<br>@@ -117,9 +117,9 @@<br> /* 1 Use external suspend clock source 32.768KHz. Undocumented?? */<br> reg = pnp_read_config(ACPI_DEV, 0xe4);<br> pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));<br>- pnp_exit_ext_func_mode(ACPI_DEV);<br>+ pnp_exit_conf_state(ACPI_DEV);<br> <br>- pnp_enter_ext_func_mode(GPIO_DEV);<br>+ pnp_enter_conf_state(GPIO_DEV);<br> pnp_set_logical_device(GPIO_DEV);<br> /* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */<br> pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */<br>@@ -129,7 +129,7 @@<br> pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0 = output 1 = input */<br> pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */<br> pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */<br>- pnp_exit_ext_func_mode(GPIO_DEV);<br>+ pnp_exit_conf_state(GPIO_DEV);<br> }<br> <br> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)<br>diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c<br>index 7088f1d..43c5677 100644<br>--- a/src/mainboard/ibase/mb899/romstage.c<br>+++ b/src/mainboard/ibase/mb899/romstage.c<br>@@ -62,7 +62,7 @@<br> pnp_devfn_t dev;<br> <br> dev = DUMMY_DEV;<br>- pnp_enter_ext_func_mode(dev);<br>+ pnp_enter_conf_state(dev);<br> <br> pnp_write_config(dev, 0x24, 0xc4); // PNPCSV<br> <br>@@ -121,7 +121,7 @@<br> pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);<br> pnp_set_enable(dev, 1);<br> <br>- pnp_exit_ext_func_mode(dev);<br>+ pnp_exit_conf_state(dev);<br> }<br> <br> static void rcba_config(void)<br>diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c<br>index 878a79e..8ddfdd6 100644<br>--- a/src/mainboard/msi/ms7260/romstage.c<br>+++ b/src/mainboard/msi/ms7260/romstage.c<br>@@ -126,11 +126,11 @@<br> bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);<br> <br> /* FIXME: This should be part of the Super I/O code/config. */<br>- pnp_enter_ext_func_mode(SERIAL_DEV);<br>+ pnp_enter_conf_state(SERIAL_DEV);<br> /* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */<br> pnp_write_config(SERIAL_DEV, 0x24, 0);<br> winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>- pnp_exit_ext_func_mode(SERIAL_DEV);<br>+ pnp_exit_conf_state(SERIAL_DEV);<br> <br> setup_mb_resource_map();<br> console_init();<br>diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c<br>index 11e9bc0..ec11dd6 100644<br>--- a/src/mainboard/msi/ms9652_fam10/romstage.c<br>+++ b/src/mainboard/msi/ms9652_fam10/romstage.c<br>@@ -129,11 +129,11 @@<br> <br> post_code(0x32);<br> <br>- pnp_enter_ext_func_mode(SERIAL_DEV);<br>+ pnp_enter_conf_state(SERIAL_DEV);<br> /* We have 24MHz input. */<br> reg = pnp_read_config(SERIAL_DEV, 0x24);<br> pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));<br>- pnp_exit_ext_func_mode(SERIAL_DEV);<br>+ pnp_exit_conf_state(SERIAL_DEV);<br> <br> winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br> console_init();<br>diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c<br>index d8076f0..c2fd798 100644<br>--- a/src/mainboard/nvidia/l1_2pvv/romstage.c<br>+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c<br>@@ -124,9 +124,9 @@<br> if (bist == 0)<br> bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);<br> <br>- pnp_enter_ext_func_mode(SERIAL_DEV);<br>+ pnp_enter_conf_state(SERIAL_DEV);<br> pnp_write_config(SERIAL_DEV, 0x24, 0);<br>- pnp_exit_ext_func_mode(SERIAL_DEV);<br>+ pnp_exit_conf_state(SERIAL_DEV);<br> <br> setup_mb_resource_map();<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/20989">change 20989</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20989"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: Icecd52ec622b9da86edb07c52893f4db001e5562 </div>
<div style="display:none"> Gerrit-Change-Number: 20989 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Keith Hui <buurin@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Keith Hui <buurin@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Paul Menzel <paulepanter@users.sourceforge.net> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>