<p>Tim Chen has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21130">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/google/coral: Add devicetree.cb file for coral<br><br>It is a copy from baseboard/devicetree.cb (coreboot.org ToT)<br><br>BUG=b:64880573<br>BRANCH=master<br>TEST=emerge-coral coreboot chromeos-bootimage<br><br>Change-Id: I5db730c1974a96547fe7fda63689b7c5bfaefc66<br>Signed-off-by: Tim Chen <Tim-Chen@quantatw.com><br>---<br>M src/mainboard/google/reef/Kconfig<br>A src/mainboard/google/reef/variants/coral/devicetree.cb<br>2 files changed, 232 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/21130/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig<br>index f3360ca..5a6bae3 100644<br>--- a/src/mainboard/google/reef/Kconfig<br>+++ b/src/mainboard/google/reef/Kconfig<br>@@ -61,6 +61,7 @@<br> <br> config DEVICETREE<br> string<br>+ default "variants/coral/devicetree.cb" if BOARD_GOOGLE_CORAL<br> default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO<br> default "variants/sand/devicetree.cb" if BOARD_GOOGLE_SAND<br> default "variants/snappy/devicetree.cb" if BOARD_GOOGLE_SNAPPY<br>diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb<br>new file mode 100644<br>index 0000000..d5f546c<br>--- /dev/null<br>+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb<br>@@ -0,0 +1,231 @@<br>+chip soc/intel/apollolake<br>+<br>+ device cpu_cluster 0 on<br>+ device lapic 0 on end<br>+ end<br>+<br>+ register "pcie_rp0_clkreq_pin" = "0" # wifi/bt<br>+ # Disable unused clkreq of PCIe root ports<br>+ register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"<br>+ register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"<br>+ register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"<br>+ register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"<br>+ register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"<br>+<br>+ # GPIO for PERST_0<br>+ # If the Board has PERST_0 signal, assign the GPIO<br>+ # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF<br>+ register "prt0_gpio" = "GPIO_122"<br>+<br>+ # GPIO for SD card detect<br>+ register "sdcard_cd_gpio" = "GPIO_177"<br>+<br>+ # EMMC TX DATA Delay 1<br>+ # Refer to EDS-Vol2-22.3.<br>+ # [14:8] steps of delay for HS400, each 125ps.<br>+ # [6:0] steps of delay for SDR104/HS200, each 125ps.<br>+ register "emmc_tx_data_cntl1" = "0x0C16"<br>+<br>+ # EMMC TX DATA Delay 2<br>+ # Refer to EDS-Vol2-22.3.<br>+ # [30:24] steps of delay for SDR50, each 125ps.<br>+ # [22:16] steps of delay for DDR50, each 125ps.<br>+ # [14:8] steps of delay for SDR25/HS50, each 125ps.<br>+ # [6:0] steps of delay for SDR12, each 125ps.<br>+ register "emmc_tx_data_cntl2" = "0x28162828"<br>+<br>+ # EMMC RX CMD/DATA Delay 1<br>+ # Refer to EDS-Vol2-22.3.<br>+ # [30:24] steps of delay for SDR50, each 125ps.<br>+ # [22:16] steps of delay for DDR50, each 125ps.<br>+ # [14:8] steps of delay for SDR25/HS50, each 125ps.<br>+ # [6:0] steps of delay for SDR12, each 125ps.<br>+ register "emmc_rx_cmd_data_cntl1" = "0x00181717"<br>+<br>+ # EMMC RX CMD/DATA Delay 2<br>+ # Refer to EDS-Vol2-22.3.<br>+ # [17:16] stands for Rx Clock before Output Buffer<br>+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps.<br>+ # [6:0] steps of delay for HS200, each 125ps.<br>+ register "emmc_rx_cmd_data_cntl2" = "0x10008"<br>+<br>+ # Enable DPTF<br>+ register "dptf_enable" = "1"<br>+<br>+ # PL1 override 12000 mW: the energy calculation is wrong with the<br>+ # current VR solution. Experiments show that SoC TDP max (6W) can<br>+ # be reached when RAPL PL1 is set to 12W.<br>+ register "tdp_pl1_override_mw" = "12000"<br>+ # Set RAPL PL2 to 15W.<br>+ register "tdp_pl2_override_mw" = "15000"<br>+<br>+ # Enable Audio Clock and Power gating<br>+ register "hdaudio_clk_gate_enable" = "1"<br>+ register "hdaudio_pwr_gate_enable" = "1"<br>+ register "hdaudio_bios_config_lockdown" = "1"<br>+<br>+ # Enable lpss s0ix<br>+ register "lpss_s0ix_enable" = "1"<br>+<br>+ # GPE configuration<br>+ # Note that GPE events called out in ASL code rely on this<br>+ # route, i.e., if this route changes then the affected GPE<br>+ # offset bits also need to be changed. This sets the PMC register<br>+ # GPE_CFG fields.<br>+ register "gpe0_dw1" = "PMC_GPE_N_31_0"<br>+ register "gpe0_dw2" = "PMC_GPE_N_63_32"<br>+ register "gpe0_dw3" = "PMC_GPE_SW_31_0"<br>+<br>+ # Enable I2C0 for audio codec at 400kHz<br>+ register "i2c[0]" = "{<br>+ .speed = I2C_SPEED_FAST,<br>+ .rise_time_ns = 104,<br>+ .fall_time_ns = 52,<br>+ }"<br>+<br>+ # Enable I2C2 bus early for TPM at 400kHz<br>+ register "i2c[2]" = "{<br>+ .early_init = 1,<br>+ .speed = I2C_SPEED_FAST,<br>+ .rise_time_ns = 57,<br>+ .fall_time_ns = 28,<br>+ }"<br>+<br>+ # touchscreen at 400kHz<br>+ register "i2c[3]" = "{<br>+ .speed = I2C_SPEED_FAST,<br>+ .rise_time_ns = 76,<br>+ .fall_time_ns = 164,<br>+ }"<br>+<br>+ # trackpad at 400kHz<br>+ register "i2c[4]" = "{<br>+ .speed = I2C_SPEED_FAST,<br>+ .rise_time_ns = 114,<br>+ .fall_time_ns = 164,<br>+ .data_hold_time_ns = 350,<br>+ }"<br>+<br>+ # digitizer at 400kHz<br>+ register "i2c[5]" = "{<br>+ .speed = I2C_SPEED_FAST,<br>+ .rise_time_ns = 152,<br>+ .fall_time_ns = 30,<br>+ }"<br>+<br>+ # Minimum SLP S3 assertion width 28ms.<br>+ register "slp_s3_assertion_width_usecs" = "28000"<br>+<br>+ device domain 0 on<br>+ device pci 00.0 on end # - Host Bridge<br>+ device pci 00.1 on end # - DPTF<br>+ device pci 00.2 on end # - NPK<br>+ device pci 02.0 on end # - Gen<br>+ device pci 03.0 on end # - Iunit<br>+ device pci 0d.0 on end # - P2SB<br>+ device pci 0d.1 on end # - PMC<br>+ device pci 0d.2 on end # - SPI<br>+ device pci 0d.3 on end # - Shared SRAM<br>+ device pci 0e.0 on # - Audio<br>+ chip drivers/generic/max98357a<br>+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)"<br>+ register "sdmode_delay" = "5"<br>+ device generic 0 on end<br>+ end<br>+ end<br>+ device pci 11.0 off end # - ISH<br>+ device pci 12.0 off end # - SATA<br>+ device pci 13.0 off end # - Root Port 2 - PCIe-A 0<br>+ device pci 13.1 off end # - Root Port 3 - PCIe-A 1<br>+ device pci 13.2 off end # - Root Port 4 - PCIe-A 2<br>+ device pci 13.3 off end # - Root Port 5 - PCIe-A 3<br>+ device pci 14.0 on<br>+ chip drivers/intel/wifi<br>+ register "wake" = "GPE0_DW3_00"<br>+ device pci 00.0 on end<br>+ end<br>+ end # - Root Port 0 - PCIe-B 0 - Wifi<br>+ device pci 14.1 off end # - Root Port 1 - PCIe-B 1<br>+ device pci 15.0 on end # - XHCI<br>+ device pci 15.1 off end # - XDCI<br>+ device pci 16.0 on # - I2C 0<br>+ chip drivers/i2c/da7219<br>+ register "irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_116_IRQ)"<br>+ register "btn_cfg" = "50"<br>+ register "mic_det_thr" = "500"<br>+ register "jack_ins_deb" = "20"<br>+ register "jack_det_rate" = ""32ms_64ms""<br>+ register "jack_rem_deb" = "1"<br>+ register "a_d_btn_thr" = "0xa"<br>+ register "d_b_btn_thr" = "0x16"<br>+ register "b_c_btn_thr" = "0x21"<br>+ register "c_mic_btn_thr" = "0x3e"<br>+ register "btn_avg" = "4"<br>+ register "adc_1bit_rpt" = "1"<br>+ register "micbias_lvl" = "2600"<br>+ register "mic_amp_in_sel" = ""diff""<br>+ device i2c 1a on end<br>+ end<br>+ end<br>+ device pci 16.1 on end # - I2C 1<br>+ device pci 16.2 on<br>+ chip drivers/i2c/tpm<br>+ register "hid" = ""GOOG0005""<br>+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_28_IRQ)"<br>+ device i2c 50 on end<br>+ end<br>+ end # - I2C 2<br>+ device pci 16.3 on<br>+ chip drivers/i2c/generic<br>+ register "hid" = ""ELAN0001""<br>+ register "desc" = ""ELAN Touchscreen""<br>+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_21_IRQ)"<br>+ register "probed" = "1"<br>+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)"<br>+ register "reset_delay_ms" = "20"<br>+ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)"<br>+ register "enable_delay_ms" = "1"<br>+ register "has_power_resource" = "1"<br>+ device i2c 10 on end<br>+ end<br>+ end # - I2C 3<br>+ device pci 17.0 on<br>+ chip drivers/i2c/generic<br>+ register "hid" = ""ELAN0000""<br>+ register "desc" = ""ELAN Touchpad""<br>+ register "irq" = "ACPI_IRQ_EDGE_LOW(GPIO_18_IRQ)"<br>+ register "wake" = "GPE0_DW1_15"<br>+ register "probed" = "1"<br>+ device i2c 15 on end<br>+ end<br>+ end # - I2C 4<br>+ device pci 17.1 on<br>+ chip drivers/i2c/hid<br>+ register "generic.hid" = ""WCOM50C1""<br>+ register "generic.desc" = ""WCOM Digitizer""<br>+ register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPIO_13_IRQ)"<br>+ register "hid_desc_reg_offset" = "0x1"<br>+ device i2c 0x9 on end<br>+ end<br>+ end # - I2C 5<br>+ device pci 17.2 off end # - I2C 6<br>+ device pci 17.3 off end # - I2C 7<br>+ device pci 18.0 on end # - UART 0<br>+ device pci 18.1 on end # - UART 1<br>+ device pci 18.2 on end # - UART 2<br>+ device pci 18.3 off end # - UART 3<br>+ device pci 19.0 on end # - SPI 0<br>+ device pci 19.1 off end # - SPI 1<br>+ device pci 19.2 off end # - SPI 2<br>+ device pci 1a.0 on end # - PWM<br>+ device pci 1b.0 on end # - SDCARD<br>+ device pci 1c.0 on end # - eMMC<br>+ device pci 1e.0 off end # - SDIO<br>+ device pci 1f.0 on # - LPC<br>+ chip ec/google/chromeec<br>+ device pnp 0c09.0 on end<br>+ end<br>+ end<br>+ device pci 1f.1 on end # - SMBUS<br>+ end<br>+end<br></pre><p>To view, visit <a href="https://review.coreboot.org/21130">change 21130</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21130"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I5db730c1974a96547fe7fda63689b7c5bfaefc66 </div>
<div style="display:none"> Gerrit-Change-Number: 21130 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Tim Chen <Tim-Chen@quantatw.com> </div>