<p>Bill XIE has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21129">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">nb/intel/*/northbridge.c: add a final() to trigger finalize_smm() at boot time<br><br>Several registers inside intel northbridge from nehalem should be locked<br>down during boot and s3 resume. coreboot do have a function implemented<br>in src/northbridge/intel/*/finalize.c to be called during an #SMI triggered<br>with outb(APM_CNT_FINALIZE, APM_CNT), but currently this #SMI is only<br>triggered during s3 resume, and not during boot. This problem has beed<br>discussed in<br>https://mail.coreboot.org/pipermail/coreboot/2017-August/084924.html .<br><br>I believe that a final() function inside struct chip_operations is a good<br>place to do the lockdown during boot time.<br><br>Only the change on sandybridge is well tested.<br><br>Change-Id: I43d4142291c8737b29738c41e8c484328b297b55<br>Signed-off-by: Bill XIE <persmule@gmail.com><br>---<br>M src/northbridge/intel/fsp_sandybridge/northbridge.c<br>M src/northbridge/intel/haswell/northbridge.c<br>M src/northbridge/intel/nehalem/northbridge.c<br>M src/northbridge/intel/sandybridge/northbridge.c<br>4 files changed, 44 insertions(+), 1 deletion(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/21129/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c<br>index a565b8d..d3eb670 100644<br>--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c<br>+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c<br>@@ -33,6 +33,7 @@<br> #include "northbridge.h"<br> #include <fsp_util.h><br> #include <cpu/intel/smm/gen1/smi.h><br>+#include <cpu/x86/smm.h><br> <br> static int bridge_revision_id = -1;<br> <br>@@ -352,7 +353,17 @@<br> }<br> }<br> <br>+static void final(void *chip_info)<br>+{<br>+ /*<br>+ * Trigger APM_CNT_FINALIZE to lock down several<br>+ * registers on the northbridge.<br>+ */<br>+ outb(APM_CNT_FINALIZE, APM_CNT);<br>+}<br>+<br> struct chip_operations northbridge_intel_fsp_sandybridge_ops = {<br> CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge")<br> .enable_dev = enable_dev,<br>+ .final = final,<br> };<br>diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c<br>index 32be916..5defba2 100644<br>--- a/src/northbridge/intel/haswell/northbridge.c<br>+++ b/src/northbridge/intel/haswell/northbridge.c<br>@@ -480,7 +480,17 @@<br> }<br> }<br> <br>+static void final(void *chip_info)<br>+{<br>+ /*<br>+ * Trigger APM_CNT_FINALIZE to lock down several<br>+ * registers on the northbridge.<br>+ */<br>+ outb(APM_CNT_FINALIZE, APM_CNT);<br>+}<br>+<br> struct chip_operations northbridge_intel_haswell_ops = {<br> CHIP_NAME("Intel i7 (Haswell) integrated Northbridge")<br> .enable_dev = enable_dev,<br>+ .final = final,<br> };<br>diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c<br>index b09460c..581c3a2 100644<br>--- a/src/northbridge/intel/nehalem/northbridge.c<br>+++ b/src/northbridge/intel/nehalem/northbridge.c<br>@@ -33,6 +33,7 @@<br> #include "chip.h"<br> #include "nehalem.h"<br> #include <cpu/intel/smm/gen1/smi.h><br>+#include <cpu/x86/smm.h><br> <br> static int bridge_revision_id = -1;<br> <br>@@ -322,7 +323,17 @@<br> }<br> }<br> <br>+static void final(void *chip_info)<br>+{<br>+ /*<br>+ * Trigger APM_CNT_FINALIZE to lock down several<br>+ * registers on the northbridge.<br>+ */<br>+ outb(APM_CNT_FINALIZE, APM_CNT);<br>+}<br>+<br> struct chip_operations northbridge_intel_nehalem_ops = {<br> CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge")<br>- .enable_dev = enable_dev,<br>+ .enable_dev = enable_dev,<br>+ .final = final,<br> };<br>diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c<br>index 3c0b9ec..aa67db7 100644<br>--- a/src/northbridge/intel/sandybridge/northbridge.c<br>+++ b/src/northbridge/intel/sandybridge/northbridge.c<br>@@ -32,6 +32,7 @@<br> #include "chip.h"<br> #include "sandybridge.h"<br> #include <cpu/intel/smm/gen1/smi.h><br>+#include <cpu/x86/smm.h><br> <br> static int bridge_revision_id = -1;<br> <br>@@ -540,7 +541,17 @@<br> }<br> }<br> <br>+static void final(void *chip_info)<br>+{<br>+ /*<br>+ * Trigger APM_CNT_FINALIZE to lock down several<br>+ * registers on the northbridge.<br>+ */<br>+ outb(APM_CNT_FINALIZE, APM_CNT);<br>+}<br>+<br> struct chip_operations northbridge_intel_sandybridge_ops = {<br> CHIP_NAME("Intel SandyBridge/IvyBridge integrated Northbridge")<br> .enable_dev = enable_dev,<br>+ .final = final,<br> };<br></pre><p>To view, visit <a href="https://review.coreboot.org/21129">change 21129</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I43d4142291c8737b29738c41e8c484328b297b55 </div>
<div style="display:none"> Gerrit-Change-Number: 21129 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Bill XIE <persmule@gmail.com> </div>