<p>Nicola Corna has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21107">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[WIP] sb/intel: Fix flashconsole on older architectures<br><br>Building coreboot with CONSOLE_SPI_FLASH on Sandybridge (and others) fails<br>with the following errors:<br><br>build/romstage/drivers/spi/spi-generic.o: In function `spi_setup_slave':<br>src/drivers/spi/spi-generic.c:119: undefined reference to `spi_ctrlr_bus_map'<br>src/drivers/spi/spi-generic.c:121: undefined reference to `spi_ctrlr_bus_map_count'<br>src/drivers/spi/spi-generic.c:124: undefined reference to `spi_ctrlr_bus_map'<br><br>This is due to the fact that sb/intel/common/spi.c is currently not built<br>in romstage, but drivers/spi/spi-generic.c requires it.<br><br>In this commit sb/intel/common/spi.c is adapted to the romstage and it is<br>added to it.<br><br>Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55<br>Signed-off-by: Nicola Corna <nicola@corna.info><br>---<br>M src/southbridge/intel/bd82x6x/Makefile.inc<br>M src/southbridge/intel/common/spi.c<br>2 files changed, 91 insertions(+), 74 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/21107/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc<br>index a570640..ae67b31 100644<br>--- a/src/southbridge/intel/bd82x6x/Makefile.inc<br>+++ b/src/southbridge/intel/bd82x6x/Makefile.inc<br>@@ -45,6 +45,7 @@<br> romstage-y += reset.c<br> romstage-y += early_spi.c early_pch_common.c<br> romstage-y += early_rcba.c<br>+romstage-y += ../common/spi.c<br> <br> ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)<br> romstage-y += early_thermal.c early_pch.c early_me.c early_usb.c<br>diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c<br>index a6a9ae5..ed0021b 100644<br>--- a/src/southbridge/intel/common/spi.c<br>+++ b/src/southbridge/intel/common/spi.c<br>@@ -15,6 +15,7 @@<br> */<br> <br> /* This file is derived from the flashrom project. */<br>+#include <arch/early_variables.h><br> #include <stdint.h><br> #include <stdlib.h><br> #include <string.h><br>@@ -71,7 +72,7 @@<br> <br> typedef struct spi_slave ich_spi_slave;<br> <br>-static int ichspi_lock = 0;<br>+static int g_ichspi_lock CAR_GLOBAL = 0;<br> <br> typedef struct ich7_spi_regs {<br> uint16_t spis;<br>@@ -136,7 +137,7 @@<br> uint32_t *bbar;<br> } ich_spi_controller;<br> <br>-static ich_spi_controller cntlr;<br>+static ich_spi_controller g_cntlr CAR_GLOBAL;<br> <br> enum {<br> SPIS_SCIP = 0x0001,<br>@@ -278,17 +279,19 @@<br> <br> static void ich_set_bbar(uint32_t minaddr)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> const uint32_t bbar_mask = 0x00ffff00;<br> uint32_t ichspi_bbar;<br> <br> minaddr &= bbar_mask;<br>- ichspi_bbar = readl_(cntlr.bbar) & ~bbar_mask;<br>+ ichspi_bbar = readl_(cntlr->bbar) & ~bbar_mask;<br> ichspi_bbar |= minaddr;<br>- writel_(ichspi_bbar, cntlr.bbar);<br>+ writel_(ichspi_bbar, cntlr->bbar);<br> }<br> <br> void spi_init(void)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> uint8_t *rcrb; /* Root Complex Register Block */<br> uint32_t rcba; /* Root Complex Base Address */<br> uint8_t bios_cntl;<br>@@ -299,32 +302,32 @@<br> #ifdef __SMM__<br> dev = PCI_DEV(0, 31, 0);<br> #else<br>- dev = dev_find_slot(0, PCI_DEVFN(31, 0));<br>+ dev = (device_t)(dev_find_slot(0, PCI_DEVFN(31, 0)));<br> #endif<br> <br> pci_read_config_dword(dev, 0xf0, &rcba);<br> /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable. */<br> rcrb = (uint8_t *)(rcba & 0xffffc000);<br> ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);<br>- cntlr.ich9_spi = ich9_spi;<br>+ cntlr->ich9_spi = ich9_spi;<br> hsfs = readw_(&ich9_spi->hsfs);<br>- ichspi_lock = hsfs & HSFS_FLOCKDN;<br>- cntlr.hsfs = hsfs;<br>- cntlr.opmenu = ich9_spi->opmenu;<br>- cntlr.menubytes = sizeof(ich9_spi->opmenu);<br>- cntlr.optype = &ich9_spi->optype;<br>- cntlr.addr = &ich9_spi->faddr;<br>- cntlr.data = (uint8_t *)ich9_spi->fdata;<br>- cntlr.databytes = sizeof(ich9_spi->fdata);<br>- cntlr.status = &ich9_spi->ssfs;<br>- cntlr.control = (uint16_t *)ich9_spi->ssfc;<br>- cntlr.bbar = &ich9_spi->bbar;<br>- cntlr.preop = &ich9_spi->preop;<br>+ car_set_var(g_ichspi_lock, hsfs & HSFS_FLOCKDN);<br>+ cntlr->hsfs = hsfs;<br>+ cntlr->opmenu = ich9_spi->opmenu;<br>+ cntlr->menubytes = sizeof(ich9_spi->opmenu);<br>+ cntlr->optype = &ich9_spi->optype;<br>+ cntlr->addr = &ich9_spi->faddr;<br>+ cntlr->data = (uint8_t *)ich9_spi->fdata;<br>+ cntlr->databytes = sizeof(ich9_spi->fdata);<br>+ cntlr->status = &ich9_spi->ssfs;<br>+ cntlr->control = (uint16_t *)ich9_spi->ssfc;<br>+ cntlr->bbar = &ich9_spi->bbar;<br>+ cntlr->preop = &ich9_spi->preop;<br> <br>- if (cntlr.hsfs & HSFS_FDV)<br>+ if (cntlr->hsfs & HSFS_FDV)<br> {<br> writel_ (4, &ich9_spi->fdoc);<br>- cntlr.flmap0 = readl_(&ich9_spi->fdod);<br>+ cntlr->flmap0 = readl_(&ich9_spi->fdod);<br> }<br> <br> ich_set_bbar(0);<br>@@ -401,17 +404,18 @@<br> <br> static int spi_setup_opcode(spi_transaction *trans)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> uint16_t optypes;<br>- uint8_t opmenu[cntlr.menubytes];<br>+ uint8_t opmenu[cntlr->menubytes];<br> <br> trans->opcode = trans->out[0];<br> spi_use_out(trans, 1);<br>- if (!ichspi_lock) {<br>+ if (!car_get_var(g_ichspi_lock)) {<br> /* The lock is off, so just use index 0. */<br>- writeb_(trans->opcode, cntlr.opmenu);<br>- optypes = readw_(cntlr.optype);<br>+ writeb_(trans->opcode, cntlr->opmenu);<br>+ optypes = readw_(cntlr->optype);<br> optypes = (optypes & 0xfffc) | (trans->type & 0x3);<br>- writew_(optypes, cntlr.optype);<br>+ writew_(optypes, cntlr->optype);<br> return 0;<br> } else {<br> /* The lock is on. See if what we need is on the menu. */<br>@@ -422,20 +426,20 @@<br> if (trans->opcode == SPI_OPCODE_WREN)<br> return 0;<br> <br>- read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));<br>- for (opcode_index = 0; opcode_index < cntlr.menubytes;<br>+ read_reg(cntlr->opmenu, opmenu, sizeof(opmenu));<br>+ for (opcode_index = 0; opcode_index < cntlr->menubytes;<br> opcode_index++) {<br> if (opmenu[opcode_index] == trans->opcode)<br> break;<br> }<br> <br>- if (opcode_index == cntlr.menubytes) {<br>+ if (opcode_index == cntlr->menubytes) {<br> printk(BIOS_DEBUG, "ICH SPI: Opcode %x not found\n",<br> trans->opcode);<br> return -1;<br> }<br> <br>- optypes = readw_(cntlr.optype);<br>+ optypes = readw_(cntlr->optype);<br> optype = (optypes >> (opcode_index * 2)) & 0x3;<br> if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&<br> optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&<br>@@ -481,14 +485,15 @@<br> */<br> static int ich_status_poll(u16 bitmask, int wait_til_set)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> int timeout = 600000; /* This will result in 6 seconds */<br> u16 status = 0;<br> <br> while (timeout--) {<br>- status = readw_(cntlr.status);<br>+ status = readw_(cntlr->status);<br> if (wait_til_set ^ ((status & bitmask) == 0)) {<br> if (wait_til_set)<br>- writew_((status & bitmask), cntlr.status);<br>+ writew_((status & bitmask), cntlr->status);<br> return status;<br> }<br> udelay(10);<br>@@ -501,14 +506,17 @@<br> <br> static int spi_is_multichip (void)<br> {<br>- if (!(cntlr.hsfs & HSFS_FDV))<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br>+<br>+ if (!(cntlr->hsfs & HSFS_FDV))<br> return 0;<br>- return !!((cntlr.flmap0 >> 8) & 3);<br>+ return !!((cntlr->flmap0 >> 8) & 3);<br> }<br> <br> static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,<br> size_t bytesout, void *din, size_t bytesin)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> uint16_t control;<br> int16_t opcode_index;<br> int with_address;<br>@@ -534,7 +542,7 @@<br> if (ich_status_poll(SPIS_SCIP, 0) == -1)<br> return -1;<br> <br>- writew_(SPIS_CDS | SPIS_FCERR, cntlr.status);<br>+ writew_(SPIS_CDS | SPIS_FCERR, cntlr->status);<br> <br> spi_setup_type(&trans);<br> if ((opcode_index = spi_setup_opcode(&trans)) < 0)<br>@@ -548,8 +556,8 @@<br> * in order to prevent the Management Engine from<br> * issuing a transaction between WREN and DATA.<br> */<br>- if (!ichspi_lock)<br>- writew_(trans.opcode, cntlr.preop);<br>+ if (!car_get_var(g_ichspi_lock))<br>+ writew_(trans.opcode, cntlr->preop);<br> return 0;<br> }<br> <br>@@ -557,13 +565,13 @@<br> control = SPIC_SCGO | ((opcode_index & 0x07) << 4);<br> <br> /* Issue atomic preop cycle if needed */<br>- if (readw_(cntlr.preop))<br>+ if (readw_(cntlr->preop))<br> control |= SPIC_ACS;<br> <br> if (!trans.bytesout && !trans.bytesin) {<br> /* SPI addresses are 24 bit only */<br> if (with_address)<br>- writel_(trans.offset & 0x00FFFFFF, cntlr.addr);<br>+ writel_(trans.offset & 0x00FFFFFF, cntlr->addr);<br> <br> /*<br> * This is a 'no data' command (like Write Enable), its<br>@@ -571,7 +579,7 @@<br> * spi_setup_opcode() above. Tell the chip to send the<br> * command.<br> */<br>- writew_(control, cntlr.control);<br>+ writew_(control, cntlr->control);<br> <br> /* wait for the result */<br> status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);<br>@@ -593,7 +601,7 @@<br> * and followed by other SPI commands, and this sequence is controlled<br> * by the SPI chip driver.<br> */<br>- if (trans.bytesout > cntlr.databytes) {<br>+ if (trans.bytesout > cntlr->databytes) {<br> printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use"<br> " spi_crop_chunk()?\n");<br> return -1;<br>@@ -607,28 +615,28 @@<br> uint32_t data_length;<br> <br> /* SPI addresses are 24 bit only */<br>- writel_(trans.offset & 0x00FFFFFF, cntlr.addr);<br>+ writel_(trans.offset & 0x00FFFFFF, cntlr->addr);<br> <br> if (trans.bytesout)<br>- data_length = min(trans.bytesout, cntlr.databytes);<br>+ data_length = min(trans.bytesout, cntlr->databytes);<br> else<br>- data_length = min(trans.bytesin, cntlr.databytes);<br>+ data_length = min(trans.bytesin, cntlr->databytes);<br> <br> /* Program data into FDATA0 to N */<br> if (trans.bytesout) {<br>- write_reg(trans.out, cntlr.data, data_length);<br>+ write_reg(trans.out, cntlr->data, data_length);<br> spi_use_out(&trans, data_length);<br> if (with_address)<br> trans.offset += data_length;<br> }<br> <br> /* Add proper control fields' values */<br>- control &= ~((cntlr.databytes - 1) << 8);<br>+ control &= ~((cntlr->databytes - 1) << 8);<br> control |= SPIC_DS;<br> control |= (data_length - 1) << 8;<br> <br> /* write it */<br>- writew_(control, cntlr.control);<br>+ writew_(control, cntlr->control);<br> <br> /* Wait for Cycle Done Status or Flash Cycle Error. */<br> status = ich_status_poll(SPIS_CDS | SPIS_FCERR, 1);<br>@@ -641,7 +649,7 @@<br> }<br> <br> if (trans.bytesin) {<br>- read_reg(cntlr.data, trans.in, data_length);<br>+ read_reg(cntlr->data, trans.in, data_length);<br> spi_use_in(&trans, data_length);<br> if (with_address)<br> trans.offset += data_length;<br>@@ -649,7 +657,7 @@<br> }<br> <br> /* Clear atomic preop now that xfer is done */<br>- writew_(0, cntlr.preop);<br>+ writew_(0, cntlr->preop);<br> <br> return 0;<br> }<br>@@ -657,8 +665,9 @@<br> /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */<br> static void ich_hwseq_set_addr(uint32_t addr)<br> {<br>- uint32_t addr_old = readl_(&cntlr.ich9_spi->faddr) & ~0x01FFFFFF;<br>- writel_((addr & 0x01FFFFFF) | addr_old, &cntlr.ich9_spi->faddr);<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br>+ uint32_t addr_old = readl_(&cntlr->ich9_spi->faddr) & ~0x01FFFFFF;<br>+ writel_((addr & 0x01FFFFFF) | addr_old, &cntlr->ich9_spi->faddr);<br> }<br> <br> /* Polls for Cycle Done Status, Flash Cycle Error or timeout in 8 us intervals.<br>@@ -668,21 +677,22 @@<br> static int ich_hwseq_wait_for_cycle_complete(unsigned int timeout,<br> unsigned int len)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> uint16_t hsfs;<br> uint32_t addr;<br> <br> timeout /= 8; /* scale timeout duration to counter */<br>- while ((((hsfs = readw_(&cntlr.ich9_spi->hsfs)) &<br>+ while ((((hsfs = readw_(&cntlr->ich9_spi->hsfs)) &<br> (HSFS_FDONE | HSFS_FCERR)) == 0) &&<br> --timeout) {<br> udelay(8);<br> }<br>- writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);<br>+ writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);<br> <br> if (!timeout) {<br> uint16_t hsfc;<br>- addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF;<br>- hsfc = readw_(&cntlr.ich9_spi->hsfc);<br>+ addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF;<br>+ hsfc = readw_(&cntlr->ich9_spi->hsfc);<br> printk(BIOS_ERR, "Transaction timeout between offset 0x%08x and "<br> "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",<br> addr, addr + len - 1, addr, len - 1,<br>@@ -692,8 +702,8 @@<br> <br> if (hsfs & HSFS_FCERR) {<br> uint16_t hsfc;<br>- addr = readl_(&cntlr.ich9_spi->faddr) & 0x01FFFFFF;<br>- hsfc = readw_(&cntlr.ich9_spi->hsfc);<br>+ addr = readl_(&cntlr->ich9_spi->faddr) & 0x01FFFFFF;<br>+ hsfc = readw_(&cntlr->ich9_spi->hsfc);<br> printk(BIOS_ERR, "Transaction error between offset 0x%08x and "<br> "0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n",<br> addr, addr + len - 1, addr, len - 1,<br>@@ -707,6 +717,7 @@<br> static int ich_hwseq_erase(const struct spi_flash *flash, u32 offset,<br> size_t len)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> u32 start, end, erase_size;<br> int ret;<br> uint16_t hsfc;<br>@@ -729,17 +740,17 @@<br> <br> while (offset < end) {<br> /* make sure FDONE, FCERR, AEL are cleared by writing 1 to them */<br>- writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);<br>+ writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);<br> <br> ich_hwseq_set_addr(offset);<br> <br> offset += erase_size;<br> <br>- hsfc = readw_(&cntlr.ich9_spi->hsfc);<br>+ hsfc = readw_(&cntlr->ich9_spi->hsfc);<br> hsfc &= ~HSFC_FCYCLE; /* clear operation */<br> hsfc |= (0x3 << HSFC_FCYCLE_OFF); /* set erase operation */<br> hsfc |= HSFC_FGO; /* start */<br>- writew_(hsfc, &cntlr.ich9_spi->hsfc);<br>+ writew_(hsfc, &cntlr->ich9_spi->hsfc);<br> if (ich_hwseq_wait_for_cycle_complete(timeout, len))<br> {<br> printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size);<br>@@ -757,12 +768,13 @@<br> <br> static void ich_read_data(uint8_t *data, int len)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> int i;<br> uint32_t temp32 = 0;<br> <br> for (i = 0; i < len; i++) {<br> if ((i % 4) == 0)<br>- temp32 = readl_(cntlr.data + i);<br>+ temp32 = readl_(cntlr->data + i);<br> <br> data[i] = (temp32 >> ((i % 4) * 8)) & 0xff;<br> }<br>@@ -771,6 +783,7 @@<br> static int ich_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len,<br> void *buf)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> uint16_t hsfc;<br> uint16_t timeout = 100 * 60;<br> uint8_t block_len;<br>@@ -784,20 +797,20 @@<br> }<br> <br> /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */<br>- writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);<br>+ writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);<br> <br> while (len > 0) {<br>- block_len = min(len, cntlr.databytes);<br>+ block_len = min(len, cntlr->databytes);<br> if (block_len > (~addr & 0xff))<br> block_len = (~addr & 0xff) + 1;<br> ich_hwseq_set_addr(addr);<br>- hsfc = readw_(&cntlr.ich9_spi->hsfc);<br>+ hsfc = readw_(&cntlr->ich9_spi->hsfc);<br> hsfc &= ~HSFC_FCYCLE; /* set read operation */<br> hsfc &= ~HSFC_FDBC; /* clear byte count */<br> /* set byte count */<br> hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);<br> hsfc |= HSFC_FGO; /* start */<br>- writew_(hsfc, &cntlr.ich9_spi->hsfc);<br>+ writew_(hsfc, &cntlr->ich9_spi->hsfc);<br> <br> if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))<br> return 1;<br>@@ -816,6 +829,7 @@<br> */<br> static void ich_fill_data(const uint8_t *data, int len)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> uint32_t temp32 = 0;<br> int i;<br> <br>@@ -829,16 +843,17 @@<br> temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8);<br> <br> if ((i % 4) == 3) /* 32 bits are full, write them to regs. */<br>- writel_(temp32, cntlr.data + (i - (i % 4)));<br>+ writel_(temp32, cntlr->data + (i - (i % 4)));<br> }<br> i--;<br> if ((i % 4) != 3) /* Write remaining data to regs. */<br>- writel_(temp32, cntlr.data + (i - (i % 4)));<br>+ writel_(temp32, cntlr->data + (i - (i % 4)));<br> }<br> <br> static int ich_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len,<br> const void *buf)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> uint16_t hsfc;<br> uint16_t timeout = 100 * 60;<br> uint8_t block_len;<br>@@ -852,24 +867,24 @@<br> }<br> <br> /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */<br>- writew_(readw_(&cntlr.ich9_spi->hsfs), &cntlr.ich9_spi->hsfs);<br>+ writew_(readw_(&cntlr->ich9_spi->hsfs), &cntlr->ich9_spi->hsfs);<br> <br> while (len > 0) {<br>- block_len = min(len, cntlr.databytes);<br>+ block_len = min(len, cntlr->databytes);<br> if (block_len > (~addr & 0xff))<br> block_len = (~addr & 0xff) + 1;<br> <br> ich_hwseq_set_addr(addr);<br> <br> ich_fill_data(buf, block_len);<br>- hsfc = readw_(&cntlr.ich9_spi->hsfc);<br>+ hsfc = readw_(&cntlr->ich9_spi->hsfc);<br> hsfc &= ~HSFC_FCYCLE; /* clear operation */<br> hsfc |= (0x2 << HSFC_FCYCLE_OFF); /* set write operation */<br> hsfc &= ~HSFC_FDBC; /* clear byte count */<br> /* set byte count */<br> hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC);<br> hsfc |= HSFC_FGO; /* start */<br>- writew_(hsfc, &cntlr.ich9_spi->hsfc);<br>+ writew_(hsfc, &cntlr->ich9_spi->hsfc);<br> <br> if (ich_hwseq_wait_for_cycle_complete(timeout, block_len))<br> {<br>@@ -895,6 +910,7 @@<br> static int spi_flash_programmer_probe(const struct spi_slave *spi,<br> struct spi_flash *flash)<br> {<br>+ ich_spi_controller *cntlr = car_get_var_ptr(&g_cntlr);<br> uint32_t flcomp;<br> <br> /* Try generic probing first if spi_is_multichip returns 0. */<br>@@ -905,7 +921,7 @@<br> flash->name = "Opaque HW-sequencing";<br> <br> ich_hwseq_set_addr (0);<br>- switch ((cntlr.hsfs >> 3) & 3)<br>+ switch ((cntlr->hsfs >> 3) & 3)<br> {<br> case 0:<br> flash->sector_size = 256;<br>@@ -921,14 +937,14 @@<br> break;<br> }<br> <br>- writel_ (0x1000, &cntlr.ich9_spi->fdoc);<br>- flcomp = readl_(&cntlr.ich9_spi->fdod);<br>+ writel_ (0x1000, &cntlr->ich9_spi->fdoc);<br>+ flcomp = readl_(&cntlr->ich9_spi->fdod);<br> <br> flash->size = 1 << (19 + (flcomp & 7));<br> <br> flash->ops = &spi_flash_ops;<br> <br>- if ((cntlr.hsfs & HSFS_FDV) && ((cntlr.flmap0 >> 8) & 3))<br>+ if ((cntlr->hsfs & HSFS_FDV) && ((cntlr->flmap0 >> 8) & 3))<br> flash->size += 1 << (19 + ((flcomp >> 3) & 7));<br> printk (BIOS_DEBUG, "flash size 0x%x bytes\n", flash->size);<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/21107">change 21107</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21107"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 </div>
<div style="display:none"> Gerrit-Change-Number: 21107 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Nicola Corna <nicola@corna.info> </div>