<p>Arthur Heymans has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21110">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/nvidia/mcp55: Link early_setup_car.c<br><br>Change-Id: I99170936b8a9851ca088a190b002da9de8ba6022<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>M src/mainboard/asus/m2n-e/romstage.c<br>M src/mainboard/gigabyte/m57sli/romstage.c<br>M src/mainboard/msi/ms7260/romstage.c<br>M src/mainboard/msi/ms9282/romstage.c<br>M src/mainboard/msi/ms9652_fam10/romstage.c<br>M src/mainboard/nvidia/l1_2pvv/romstage.c<br>M src/mainboard/sunw/ultra40m2/romstage.c<br>M src/mainboard/supermicro/h8dme/romstage.c<br>M src/mainboard/supermicro/h8dmr/romstage.c<br>M src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>M src/mainboard/supermicro/h8qme_fam10/romstage.c<br>M src/mainboard/tyan/s2912/romstage.c<br>M src/mainboard/tyan/s2912_fam10/romstage.c<br>M src/southbridge/nvidia/mcp55/Makefile.inc<br>M src/southbridge/nvidia/mcp55/early_setup_car.c<br>M src/southbridge/nvidia/mcp55/mcp55.h<br>16 files changed, 9 insertions(+), 14 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/21110/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c<br>index 2ca0fbc..88b817d 100644<br>--- a/src/mainboard/asus/m2n-e/romstage.c<br>+++ b/src/mainboard/asus/m2n-e/romstage.c<br>@@ -68,7 +68,6 @@<br> #include "resourcemap.c"<br> #include "cpu/amd/dualcore/dualcore.c"<br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> #include "cpu/amd/model_fxx/init_cpus.c"<br> #include "northbridge/amd/amdk8/early_ht.c"<br> <br>diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c<br>index 12939ca..0acb9c2 100644<br>--- a/src/mainboard/gigabyte/m57sli/romstage.c<br>+++ b/src/mainboard/gigabyte/m57sli/romstage.c<br>@@ -68,7 +68,6 @@<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */<br> <br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> #include <northbridge/amd/amdk8/f.h><br> #include "northbridge/amd/amdk8/incoherent_ht.c"<br> #include "lib/generic_sdram.c"<br>diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c<br>index 0569365..3402b81 100644<br>--- a/src/mainboard/msi/ms7260/romstage.c<br>+++ b/src/mainboard/msi/ms7260/romstage.c<br>@@ -76,7 +76,6 @@<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */<br> <br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> #include "cpu/amd/model_fxx/init_cpus.c"<br> #include "cpu/amd/model_fxx/fidvid.c"<br> #include "northbridge/amd/amdk8/early_ht.c"<br>diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c<br>index 2334c11..f8e7e4b 100644<br>--- a/src/mainboard/msi/ms9282/romstage.c<br>+++ b/src/mainboard/msi/ms9282/romstage.c<br>@@ -84,7 +84,6 @@<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0 << 4)|(0 << 2)|(0 << 0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \<br> <br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> #include "cpu/amd/model_fxx/init_cpus.c"<br> #include "northbridge/amd/amdk8/early_ht.c"<br> <br>diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c<br>index 11e9bc0..7ec5bb0 100644<br>--- a/src/mainboard/msi/ms9652_fam10/romstage.c<br>+++ b/src/mainboard/msi/ms9652_fam10/romstage.c<br>@@ -79,7 +79,6 @@<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */<br> <br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> <br> static void sio_setup(void)<br> {<br>diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c<br>index 3aa261b..a1665f8 100644<br>--- a/src/mainboard/nvidia/l1_2pvv/romstage.c<br>+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c<br>@@ -75,7 +75,6 @@<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */<br> <br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> #include "cpu/amd/model_fxx/init_cpus.c"<br> #include "cpu/amd/model_fxx/fidvid.c"<br> #include "northbridge/amd/amdk8/early_ht.c"<br>diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c<br>index 1dd09f6..589cee1 100644<br>--- a/src/mainboard/sunw/ultra40m2/romstage.c<br>+++ b/src/mainboard/sunw/ultra40m2/romstage.c<br>@@ -72,7 +72,6 @@<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+61, 0x00, 0x05,/* GPIO62: enable/not-disable on-board TSB43AB22A Firewire */<br> <br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> #include "cpu/amd/model_fxx/init_cpus.c"<br> #include "cpu/amd/model_fxx/fidvid.c"<br> #include "northbridge/amd/amdk8/early_ht.c"<br>diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c<br>index 0255242..edf717c 100644<br>--- a/src/mainboard/supermicro/h8dme/romstage.c<br>+++ b/src/mainboard/supermicro/h8dme/romstage.c<br>@@ -75,7 +75,6 @@<br> #include "resourcemap.c"<br> #include "cpu/amd/dualcore/dualcore.c"<br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> #include "cpu/amd/model_fxx/init_cpus.c"<br> #include "cpu/amd/model_fxx/fidvid.c"<br> #include "northbridge/amd/amdk8/early_ht.c"<br>diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c<br>index a57be62..9cd3311 100644<br>--- a/src/mainboard/supermicro/h8dmr/romstage.c<br>+++ b/src/mainboard/supermicro/h8dmr/romstage.c<br>@@ -67,7 +67,6 @@<br> #include "resourcemap.c"<br> #include "cpu/amd/dualcore/dualcore.c"<br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> #include "cpu/amd/model_fxx/init_cpus.c"<br> #include "cpu/amd/model_fxx/fidvid.c"<br> #include "northbridge/amd/amdk8/early_ht.c"<br>diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>index e100876..c4be7e4 100644<br>--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c<br>@@ -47,7 +47,6 @@<br> #include "resourcemap.c"<br> #include "cpu/amd/quadcore/quadcore.c"<br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> <br> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)<br> #define DUMMY_DEV PNP_DEV(0x2e, 0)<br>diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c<br>index 3554a05..86077c7 100644<br>--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c<br>+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c<br>@@ -46,7 +46,6 @@<br> #include "resourcemap.c"<br> #include "cpu/amd/quadcore/quadcore.c"<br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> <br> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)<br> #define DUMMY_DEV PNP_DEV(0x2e, 0)<br>diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c<br>index c4804c5..fb89141 100644<br>--- a/src/mainboard/tyan/s2912/romstage.c<br>+++ b/src/mainboard/tyan/s2912/romstage.c<br>@@ -75,7 +75,6 @@<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */<br> <br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> #include "cpu/amd/model_fxx/init_cpus.c"<br> #include "cpu/amd/model_fxx/fidvid.c"<br> #include "northbridge/amd/amdk8/early_ht.c"<br>diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c<br>index b449f77..bec9741 100644<br>--- a/src/mainboard/tyan/s2912_fam10/romstage.c<br>+++ b/src/mainboard/tyan/s2912_fam10/romstage.c<br>@@ -68,7 +68,6 @@<br> RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */<br> <br> #include <southbridge/nvidia/mcp55/early_setup_ss.h><br>-#include "southbridge/nvidia/mcp55/early_setup_car.c"<br> <br> unsigned get_sbdn(unsigned bus)<br> {<br>diff --git a/src/southbridge/nvidia/mcp55/Makefile.inc b/src/southbridge/nvidia/mcp55/Makefile.inc<br>index 7073b69..33d6106 100644<br>--- a/src/southbridge/nvidia/mcp55/Makefile.inc<br>+++ b/src/southbridge/nvidia/mcp55/Makefile.inc<br>@@ -21,6 +21,7 @@<br> ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c<br> romstage-y += early_smbus.c<br> romstage-y += early_ctrl.c<br>+romstage-y += early_setup_car.c<br> <br> ifeq ($(CONFIG_MCP55_USE_AZA),y)<br> ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c<br>diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c<br>index 44a330c..8095a98 100644<br>--- a/src/southbridge/nvidia/mcp55/early_setup_car.c<br>+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c<br>@@ -15,9 +15,15 @@<br> * GNU General Public License for more details.<br> */<br> <br>+#include <arch/io.h><br>+#include <console/console.h><br>+#include <device/pci_def.h><br>+#include <delay.h><br> #if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AMDK8)<br> #include <northbridge/amd/amdk8/amdk8.h><br> #endif<br>+<br>+#include "mcp55.h"<br> <br> #ifdef UNUSED_CODE<br> int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val);<br>@@ -339,7 +345,7 @@<br> <br> #endif<br> <br>-static int mcp55_early_setup_x(void)<br>+int mcp55_early_setup_x(void)<br> {<br> /* Find out how many MCP55 we have. */<br> unsigned busn[HT_CHAIN_NUM_MAX] = {0};<br>diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h<br>index a244b82..67bc1db 100644<br>--- a/src/southbridge/nvidia/mcp55/mcp55.h<br>+++ b/src/southbridge/nvidia/mcp55/mcp55.h<br>@@ -40,6 +40,7 @@<br> int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address);<br> int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address,<br> unsigned char val);<br>+int mcp55_early_setup_x(void);<br> #endif<br> <br> #endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/21110">change 21110</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21110"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I99170936b8a9851ca088a190b002da9de8ba6022 </div>
<div style="display:none"> Gerrit-Change-Number: 21110 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>