<p>Martin Roth <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/20501">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Arthur Heymans: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">mainboard/hp: Add HP Elitebook 8460p<br><br>The code is based on autoport. I'm using a machine with discrete GPU,<br>and gfx.* in devicetree.cb is from 2760p.<br><br>It can be debug with serial port on dock.<br><br>Tested:<br>- CPU and memory: i5-2540M, 4G+0<br>- Arch Linux (Linux 4.11.7, SeaBIOS payload, with ATOM BIOS extracted<br> from vendor UEFI firmware)<br>- USB ports<br>- SD card reader<br>- WLAN<br>- DP display<br>- S3<br><br>Change-Id: I9c42723ba240a2e9b46998c1a8a708aebc66c604<br>Signed-off-by: Iru Cai <mytbk920423@gmail.com><br>Reviewed-on: https://review.coreboot.org/20501<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Arthur Heymans <arthur@aheymans.xyz><br>---<br>A src/mainboard/hp/8460p/Kconfig<br>A src/mainboard/hp/8460p/Kconfig.name<br>A src/mainboard/hp/8460p/Makefile.inc<br>A src/mainboard/hp/8460p/acpi/ec.asl<br>A src/mainboard/hp/8460p/acpi/platform.asl<br>A src/mainboard/hp/8460p/acpi/superio.asl<br>A src/mainboard/hp/8460p/acpi_tables.c<br>A src/mainboard/hp/8460p/board_info.txt<br>A src/mainboard/hp/8460p/devicetree.cb<br>A src/mainboard/hp/8460p/dsdt.asl<br>A src/mainboard/hp/8460p/gma-mainboard.ads<br>A src/mainboard/hp/8460p/gpio.c<br>A src/mainboard/hp/8460p/hda_verb.c<br>A src/mainboard/hp/8460p/mainboard.c<br>A src/mainboard/hp/8460p/romstage.c<br>15 files changed, 842 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/mainboard/hp/8460p/Kconfig b/src/mainboard/hp/8460p/Kconfig<br>new file mode 100644<br>index 0000000..6a035ae<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/Kconfig<br>@@ -0,0 +1,76 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com><br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; version 2 of the License.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+if BOARD_HP_8460P<br>+<br>+config BOARD_SPECIFIC_OPTIONS # dummy<br>+ def_bool y<br>+ select BOARD_ROMSIZE_KB_8192<br>+ select CPU_INTEL_SOCKET_RPGA989<br>+ select HAVE_ACPI_RESUME<br>+ select HAVE_ACPI_TABLES<br>+ select INTEL_INT15<br>+ select NORTHBRIDGE_INTEL_SANDYBRIDGE<br>+ select SANDYBRIDGE_IVYBRIDGE_LVDS<br>+ select SERIRQ_CONTINUOUS_MODE<br>+ select SOUTHBRIDGE_INTEL_BD82X6X<br>+ select SYSTEM_TYPE_LAPTOP<br>+ select USE_NATIVE_RAMINIT<br>+ select MAINBOARD_HAS_LIBGFXINIT<br>+ select GFX_GMA_INTERNAL_IS_LVDS<br>+ select EC_HP_KBC1126<br>+ select SUPERIO_SMSC_LPC47N217<br>+<br>+config HAVE_IFD_BIN<br>+ bool<br>+ default n<br>+<br>+config HAVE_ME_BIN<br>+ bool<br>+ default n<br>+<br>+config MAINBOARD_DIR<br>+ string<br>+ default hp/8460p<br>+<br>+config MAINBOARD_PART_NUMBER<br>+ string<br>+ default "EliteBook 8460p"<br>+<br>+config VGA_BIOS_FILE<br>+ string<br>+ default "pci8086,0116.rom"<br>+<br>+config VGA_BIOS_ID<br>+ string<br>+ default "8086,0116"<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID<br>+ hex<br>+ default 0x161c<br>+<br>+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID<br>+ hex<br>+ default 0x103c<br>+<br>+config MAX_CPUS<br>+ int<br>+ default 8<br>+<br>+config USBDEBUG_HCD_INDEX<br>+ int<br>+ default 1<br>+<br>+endif<br>diff --git a/src/mainboard/hp/8460p/Kconfig.name b/src/mainboard/hp/8460p/Kconfig.name<br>new file mode 100644<br>index 0000000..94f2fe9<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/Kconfig.name<br>@@ -0,0 +1,2 @@<br>+config BOARD_HP_8460P<br>+ bool "EliteBook 8460p"<br>diff --git a/src/mainboard/hp/8460p/Makefile.inc b/src/mainboard/hp/8460p/Makefile.inc<br>new file mode 100644<br>index 0000000..7a00cce<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/Makefile.inc<br>@@ -0,0 +1,18 @@<br>+##<br>+## This file is part of the coreboot project.<br>+##<br>+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.<br>+##<br>+## This program is free software; you can redistribute it and/or modify<br>+## it under the terms of the GNU General Public License as published by<br>+## the Free Software Foundation; version 2 of the License.<br>+##<br>+## This program is distributed in the hope that it will be useful,<br>+## but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+## GNU General Public License for more details.<br>+##<br>+<br>+romstage-y += gpio.c<br>+<br>+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads<br>diff --git a/src/mainboard/hp/8460p/acpi/ec.asl b/src/mainboard/hp/8460p/acpi/ec.asl<br>new file mode 100644<br>index 0000000..ac65fb3<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/acpi/ec.asl<br>@@ -0,0 +1,16 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <ec/hp/kbc1126/acpi/ec.asl><br>diff --git a/src/mainboard/hp/8460p/acpi/platform.asl b/src/mainboard/hp/8460p/acpi/platform.asl<br>new file mode 100644<br>index 0000000..79eddcb<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/acpi/platform.asl<br>@@ -0,0 +1,23 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+Method(_WAK,1)<br>+{<br>+ Return(Package(){0,0})<br>+}<br>+<br>+Method(_PTS,1)<br>+{<br>+}<br>diff --git a/src/mainboard/hp/8460p/acpi/superio.asl b/src/mainboard/hp/8460p/acpi/superio.asl<br>new file mode 100644<br>index 0000000..b3ea115<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/acpi/superio.asl<br>@@ -0,0 +1,16 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <drivers/pc80/pc/ps2_controller.asl><br>diff --git a/src/mainboard/hp/8460p/acpi_tables.c b/src/mainboard/hp/8460p/acpi_tables.c<br>new file mode 100644<br>index 0000000..7d634a0<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/acpi_tables.c<br>@@ -0,0 +1,35 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <southbridge/intel/bd82x6x/nvs.h><br>+<br>+void acpi_create_gnvs(global_nvs_t *gnvs)<br>+{<br>+ /* Disable USB ports in S3 by default */<br>+ gnvs->s3u0 = 0;<br>+ gnvs->s3u1 = 0;<br>+<br>+ /* Disable USB ports in S5 by default */<br>+ gnvs->s5u0 = 0;<br>+ gnvs->s5u1 = 0;<br>+<br>+ // the lid is open by default.<br>+ gnvs->lids = 1;<br>+<br>+ gnvs->tcrt = 100;<br>+ gnvs->tpsv = 90;<br>+}<br>diff --git a/src/mainboard/hp/8460p/board_info.txt b/src/mainboard/hp/8460p/board_info.txt<br>new file mode 100644<br>index 0000000..024040b<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/board_info.txt<br>@@ -0,0 +1,7 @@<br>+Category: laptop<br>+Board URL: https://support.hp.com/us-en/product/HP-EliteBook-8460p-Notebook-PC/5056942<br>+ROM package: SOIC-8<br>+ROM protocol: SPI<br>+ROM socketed: n<br>+Flashrom support: n<br>+Release year: 2011<br>diff --git a/src/mainboard/hp/8460p/devicetree.cb b/src/mainboard/hp/8460p/devicetree.cb<br>new file mode 100644<br>index 0000000..4b1df4a<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/devicetree.cb<br>@@ -0,0 +1,153 @@<br>+#<br>+# This file is part of the coreboot project.<br>+#<br>+# Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com><br>+#<br>+# This program is free software; you can redistribute it and/or modify<br>+# it under the terms of the GNU General Public License as published by<br>+# the Free Software Foundation; either version 2 of the License, or<br>+# (at your option) any later version.<br>+#<br>+# This program is distributed in the hope that it will be useful,<br>+# but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+# GNU General Public License for more details.<br>+#<br>+<br>+chip northbridge/intel/sandybridge<br>+ register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }"<br>+ register "gfx.link_frequency_270_mhz" = "1"<br>+ register "gfx.ndid" = "3"<br>+ register "gfx.use_spread_spectrum_clock" = "1"<br>+ register "gpu_cpu_backlight" = "0x00000129"<br>+ register "gpu_dp_b_hotplug" = "4"<br>+ register "gpu_dp_c_hotplug" = "4"<br>+ register "gpu_dp_d_hotplug" = "4"<br>+ register "gpu_panel_port_select" = "0"<br>+ register "gpu_panel_power_backlight_off_delay" = "2000"<br>+ register "gpu_panel_power_backlight_on_delay" = "2000"<br>+ register "gpu_panel_power_cycle_delay" = "5"<br>+ register "gpu_panel_power_down_delay" = "230"<br>+ register "gpu_panel_power_up_delay" = "300"<br>+ register "gpu_pch_backlight" = "0x02880288"<br>+ device cpu_cluster 0x0 on<br>+ chip cpu/intel/socket_rPGA989<br>+ device lapic 0x0 on<br>+ end<br>+ end<br>+ chip cpu/intel/model_206ax<br>+ register "c1_acpower" = "1"<br>+ register "c1_battery" = "1"<br>+ register "c2_acpower" = "3"<br>+ register "c2_battery" = "3"<br>+ register "c3_acpower" = "5"<br>+ register "c3_battery" = "5"<br>+ device lapic 0xacac off<br>+ end<br>+ end<br>+ end<br>+ device domain 0x0 on<br>+ device pci 00.0 on # Host bridge<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 01.0 on # PCIe Bridge for discrete graphics<br>+ end<br>+ device pci 02.0 on # Internal graphics<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH<br>+ register "c2_latency" = "0x0065"<br>+ register "docking_supported" = "0"<br>+ register "gen1_dec" = "0x007c0201"<br>+ register "gen2_dec" = "0x000c0101"<br>+ register "gen3_dec" = "0x00fcfe01"<br>+ register "gen4_dec" = "0x000402e9"<br>+ register "gpi6_routing" = "2"<br>+ register "p_cnt_throttling_supported" = "1"<br>+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"<br>+ register "pcie_port_coalesce" = "1"<br>+ register "sata_interface_speed_support" = "0x3"<br>+ register "sata_port_map" = "0x3b"<br>+<br>+ register "spi_uvscc" = "0x2005"<br>+ register "spi_lvscc" = "0"<br>+<br>+ device pci 16.0 on # Management Engine Interface 1<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 16.1 off # Management Engine Interface 2<br>+ end<br>+ device pci 16.2 off # Management Engine IDE-R<br>+ end<br>+ device pci 16.3 on # Management Engine KT<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 19.0 on # Intel Gigabit Ethernet<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 1a.0 on # USB2 EHCI #2<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 1b.0 on # High Definition Audio Audio controller<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 1c.0 on # PCIe Port #1<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 1c.1 on # PCIe Port #2<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 1c.2 on # PCIe Port #3<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 1c.3 on # PCIe Port #4<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 1c.4 off # PCIe Port #5<br>+ end<br>+ device pci 1c.5 off # PCIe Port #6<br>+ end<br>+ device pci 1c.6 off # PCIe Port #7<br>+ end<br>+ device pci 1c.7 on # PCIe Port #8<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 1d.0 on # USB2 EHCI #1<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 1e.0 off # PCI bridge<br>+ end<br>+ device pci 1f.0 on # LPC bridge PCI-LPC bridge<br>+ subsystemid 0x103c 0x161c<br>+ chip ec/hp/kbc1126<br>+ register "ec_data_port" = "0x60"<br>+ register "ec_cmd_port" = "0x64"<br>+ register "ec_ctrl_reg" = "0xca"<br>+ register "ec_fan_ctrl_value" = "0x6b"<br>+ device pnp ff.1 off end<br>+ end # kbc1126<br>+ chip superio/smsc/lpc47n217<br>+ device pnp 4e.3 on # Parallel<br>+ io 0x60 = 0x378<br>+ irq 0x70 = 7<br>+ end<br>+ device pnp 4e.4 on # Com1<br>+ io 0x60 = 0x3f8<br>+ irq 0x70 = 4<br>+ end<br>+ device pnp 4e.5 off # Com2<br>+ end<br>+ end #chip superio/smsc/lpc47n217<br>+ end<br>+ device pci 1f.2 on # SATA Controller 1<br>+ subsystemid 0x103c 0x161c<br>+ end<br>+ device pci 1f.3 off # SMBus<br>+ end<br>+ device pci 1f.5 off # SATA Controller 2<br>+ end<br>+ device pci 1f.6 off # Thermal<br>+ end<br>+ end<br>+ end<br>+end<br>diff --git a/src/mainboard/hp/8460p/dsdt.asl b/src/mainboard/hp/8460p/dsdt.asl<br>new file mode 100644<br>index 0000000..d4fab7a<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/dsdt.asl<br>@@ -0,0 +1,45 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2007-2009 coresystems GmbH<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB<br>+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB<br>+#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0<br>+DefinitionBlock(<br>+ "dsdt.aml",<br>+ "DSDT",<br>+ 0x03, // DSDT revision: ACPI v3.0<br>+ "COREv4", // OEM id<br>+ "COREBOOT", // OEM table id<br>+ 0x20141018 // OEM revision<br>+)<br>+{<br>+ // Some generic macros<br>+ #include "acpi/platform.asl"<br>+ #include <cpu/intel/model_206ax/acpi/cpu.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/platform.asl><br>+ /* global NVS and variables. */<br>+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl><br>+<br>+ Scope (\_SB) {<br>+ Device (PCI0)<br>+ {<br>+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl><br>+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/pch.asl><br>+ #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl><br>+ }<br>+ }<br>+}<br>diff --git a/src/mainboard/hp/8460p/gma-mainboard.ads b/src/mainboard/hp/8460p/gma-mainboard.ads<br>new file mode 100644<br>index 0000000..da495f6<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/gma-mainboard.ads<br>@@ -0,0 +1,34 @@<br>+--<br>+-- Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com><br>+--<br>+-- This program is free software; you can redistribute it and/or modify<br>+-- it under the terms of the GNU General Public License as published by<br>+-- the Free Software Foundation; either version 2 of the License, or<br>+-- (at your option) any later version.<br>+--<br>+-- This program is distributed in the hope that it will be useful,<br>+-- but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+-- GNU General Public License for more details.<br>+--<br>+<br>+with HW.GFX.GMA;<br>+with HW.GFX.GMA.Display_Probing;<br>+<br>+use HW.GFX.GMA;<br>+use HW.GFX.GMA.Display_Probing;<br>+<br>+private package GMA.Mainboard is<br>+<br>+ ports : constant Port_List :=<br>+ (DP1,<br>+ DP2,<br>+ DP3,<br>+ HDMI1,<br>+ HDMI2,<br>+ HDMI3,<br>+ Analog,<br>+ Internal,<br>+ others => Disabled);<br>+<br>+end GMA.Mainboard;<br>diff --git a/src/mainboard/hp/8460p/gpio.c b/src/mainboard/hp/8460p/gpio.c<br>new file mode 100644<br>index 0000000..3951d88<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/gpio.c<br>@@ -0,0 +1,240 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <southbridge/intel/common/gpio.h><br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_mode = {<br>+ .gpio0 = GPIO_MODE_GPIO,<br>+ .gpio1 = GPIO_MODE_GPIO,<br>+ .gpio2 = GPIO_MODE_GPIO,<br>+ .gpio3 = GPIO_MODE_GPIO,<br>+ .gpio4 = GPIO_MODE_GPIO,<br>+ .gpio5 = GPIO_MODE_NATIVE,<br>+ .gpio6 = GPIO_MODE_GPIO,<br>+ .gpio7 = GPIO_MODE_GPIO,<br>+ .gpio8 = GPIO_MODE_GPIO,<br>+ .gpio9 = GPIO_MODE_NATIVE,<br>+ .gpio10 = GPIO_MODE_GPIO,<br>+ .gpio11 = GPIO_MODE_GPIO,<br>+ .gpio12 = GPIO_MODE_NATIVE,<br>+ .gpio13 = GPIO_MODE_GPIO,<br>+ .gpio14 = GPIO_MODE_GPIO,<br>+ .gpio15 = GPIO_MODE_GPIO,<br>+ .gpio16 = GPIO_MODE_GPIO,<br>+ .gpio17 = GPIO_MODE_GPIO,<br>+ .gpio18 = GPIO_MODE_NATIVE,<br>+ .gpio19 = GPIO_MODE_NATIVE,<br>+ .gpio20 = GPIO_MODE_NATIVE,<br>+ .gpio21 = GPIO_MODE_GPIO,<br>+ .gpio22 = GPIO_MODE_GPIO,<br>+ .gpio23 = GPIO_MODE_GPIO,<br>+ .gpio24 = GPIO_MODE_GPIO,<br>+ .gpio25 = GPIO_MODE_NATIVE,<br>+ .gpio26 = GPIO_MODE_NATIVE,<br>+ .gpio27 = GPIO_MODE_GPIO,<br>+ .gpio28 = GPIO_MODE_GPIO,<br>+ .gpio29 = GPIO_MODE_GPIO,<br>+ .gpio30 = GPIO_MODE_NATIVE,<br>+ .gpio31 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_direction = {<br>+ .gpio0 = GPIO_DIR_OUTPUT,<br>+ .gpio1 = GPIO_DIR_INPUT,<br>+ .gpio2 = GPIO_DIR_INPUT,<br>+ .gpio3 = GPIO_DIR_INPUT,<br>+ .gpio4 = GPIO_DIR_INPUT,<br>+ .gpio6 = GPIO_DIR_INPUT,<br>+ .gpio7 = GPIO_DIR_INPUT,<br>+ .gpio8 = GPIO_DIR_INPUT,<br>+ .gpio10 = GPIO_DIR_INPUT,<br>+ .gpio11 = GPIO_DIR_OUTPUT,<br>+ .gpio13 = GPIO_DIR_INPUT,<br>+ .gpio14 = GPIO_DIR_INPUT,<br>+ .gpio15 = GPIO_DIR_INPUT,<br>+ .gpio16 = GPIO_DIR_INPUT,<br>+ .gpio17 = GPIO_DIR_OUTPUT,<br>+ .gpio21 = GPIO_DIR_INPUT,<br>+ .gpio22 = GPIO_DIR_OUTPUT,<br>+ .gpio23 = GPIO_DIR_INPUT,<br>+ .gpio24 = GPIO_DIR_OUTPUT,<br>+ .gpio27 = GPIO_DIR_OUTPUT,<br>+ .gpio28 = GPIO_DIR_OUTPUT,<br>+ .gpio29 = GPIO_DIR_OUTPUT,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_level = {<br>+ .gpio0 = GPIO_LEVEL_LOW,<br>+ .gpio11 = GPIO_LEVEL_LOW,<br>+ .gpio17 = GPIO_LEVEL_HIGH,<br>+ .gpio22 = GPIO_LEVEL_HIGH,<br>+ .gpio24 = GPIO_LEVEL_HIGH,<br>+ .gpio27 = GPIO_LEVEL_LOW,<br>+ .gpio28 = GPIO_LEVEL_LOW,<br>+ .gpio29 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_reset = {<br>+ .gpio24 = GPIO_RESET_RSMRST,<br>+ .gpio30 = GPIO_RESET_RSMRST,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_invert = {<br>+ .gpio1 = GPIO_INVERT,<br>+ .gpio3 = GPIO_INVERT,<br>+ .gpio6 = GPIO_INVERT,<br>+ .gpio7 = GPIO_INVERT,<br>+ .gpio10 = GPIO_INVERT,<br>+ .gpio13 = GPIO_INVERT,<br>+ .gpio14 = GPIO_INVERT,<br>+};<br>+<br>+static const struct pch_gpio_set1 pch_gpio_set1_blink = {<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_mode = {<br>+ .gpio32 = GPIO_MODE_NATIVE,<br>+ .gpio33 = GPIO_MODE_GPIO,<br>+ .gpio34 = GPIO_MODE_GPIO,<br>+ .gpio35 = GPIO_MODE_GPIO,<br>+ .gpio36 = GPIO_MODE_GPIO,<br>+ .gpio37 = GPIO_MODE_GPIO,<br>+ .gpio38 = GPIO_MODE_GPIO,<br>+ .gpio39 = GPIO_MODE_GPIO,<br>+ .gpio40 = GPIO_MODE_NATIVE,<br>+ .gpio41 = GPIO_MODE_NATIVE,<br>+ .gpio42 = GPIO_MODE_NATIVE,<br>+ .gpio43 = GPIO_MODE_NATIVE,<br>+ .gpio44 = GPIO_MODE_GPIO,<br>+ .gpio45 = GPIO_MODE_NATIVE,<br>+ .gpio46 = GPIO_MODE_GPIO,<br>+ .gpio47 = GPIO_MODE_NATIVE,<br>+ .gpio48 = GPIO_MODE_GPIO,<br>+ .gpio49 = GPIO_MODE_GPIO,<br>+ .gpio50 = GPIO_MODE_GPIO,<br>+ .gpio51 = GPIO_MODE_GPIO,<br>+ .gpio52 = GPIO_MODE_GPIO,<br>+ .gpio53 = GPIO_MODE_GPIO,<br>+ .gpio54 = GPIO_MODE_GPIO,<br>+ .gpio55 = GPIO_MODE_GPIO,<br>+ .gpio56 = GPIO_MODE_NATIVE,<br>+ .gpio57 = GPIO_MODE_GPIO,<br>+ .gpio58 = GPIO_MODE_NATIVE,<br>+ .gpio59 = GPIO_MODE_NATIVE,<br>+ .gpio60 = GPIO_MODE_GPIO,<br>+ .gpio61 = GPIO_MODE_GPIO,<br>+ .gpio62 = GPIO_MODE_NATIVE,<br>+ .gpio63 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_direction = {<br>+ .gpio33 = GPIO_DIR_OUTPUT,<br>+ .gpio34 = GPIO_DIR_INPUT,<br>+ .gpio35 = GPIO_DIR_OUTPUT,<br>+ .gpio36 = GPIO_DIR_OUTPUT,<br>+ .gpio37 = GPIO_DIR_OUTPUT,<br>+ .gpio38 = GPIO_DIR_INPUT,<br>+ .gpio39 = GPIO_DIR_INPUT,<br>+ .gpio44 = GPIO_DIR_INPUT,<br>+ .gpio46 = GPIO_DIR_INPUT,<br>+ .gpio48 = GPIO_DIR_INPUT,<br>+ .gpio49 = GPIO_DIR_OUTPUT,<br>+ .gpio50 = GPIO_DIR_INPUT,<br>+ .gpio51 = GPIO_DIR_INPUT,<br>+ .gpio52 = GPIO_DIR_INPUT,<br>+ .gpio53 = GPIO_DIR_OUTPUT,<br>+ .gpio54 = GPIO_DIR_INPUT,<br>+ .gpio55 = GPIO_DIR_INPUT,<br>+ .gpio57 = GPIO_DIR_OUTPUT,<br>+ .gpio60 = GPIO_DIR_OUTPUT,<br>+ .gpio61 = GPIO_DIR_OUTPUT,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_level = {<br>+ .gpio33 = GPIO_LEVEL_LOW,<br>+ .gpio35 = GPIO_LEVEL_LOW,<br>+ .gpio36 = GPIO_LEVEL_LOW,<br>+ .gpio37 = GPIO_LEVEL_LOW,<br>+ .gpio49 = GPIO_LEVEL_LOW,<br>+ .gpio53 = GPIO_LEVEL_HIGH,<br>+ .gpio57 = GPIO_LEVEL_HIGH,<br>+ .gpio60 = GPIO_LEVEL_HIGH,<br>+ .gpio61 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+static const struct pch_gpio_set2 pch_gpio_set2_reset = {<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_mode = {<br>+ .gpio64 = GPIO_MODE_NATIVE,<br>+ .gpio65 = GPIO_MODE_NATIVE,<br>+ .gpio66 = GPIO_MODE_NATIVE,<br>+ .gpio67 = GPIO_MODE_NATIVE,<br>+ .gpio68 = GPIO_MODE_GPIO,<br>+ .gpio69 = GPIO_MODE_GPIO,<br>+ .gpio70 = GPIO_MODE_GPIO,<br>+ .gpio71 = GPIO_MODE_GPIO,<br>+ .gpio72 = GPIO_MODE_GPIO,<br>+ .gpio73 = GPIO_MODE_GPIO,<br>+ .gpio74 = GPIO_MODE_GPIO,<br>+ .gpio75 = GPIO_MODE_NATIVE,<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_direction = {<br>+ .gpio68 = GPIO_DIR_OUTPUT,<br>+ .gpio69 = GPIO_DIR_INPUT,<br>+ .gpio70 = GPIO_DIR_OUTPUT,<br>+ .gpio71 = GPIO_DIR_OUTPUT,<br>+ .gpio72 = GPIO_DIR_OUTPUT,<br>+ .gpio73 = GPIO_DIR_OUTPUT,<br>+ .gpio74 = GPIO_DIR_OUTPUT,<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_level = {<br>+ .gpio68 = GPIO_LEVEL_HIGH,<br>+ .gpio70 = GPIO_LEVEL_HIGH,<br>+ .gpio71 = GPIO_LEVEL_HIGH,<br>+ .gpio72 = GPIO_LEVEL_LOW,<br>+ .gpio73 = GPIO_LEVEL_HIGH,<br>+ .gpio74 = GPIO_LEVEL_HIGH,<br>+};<br>+<br>+static const struct pch_gpio_set3 pch_gpio_set3_reset = {<br>+};<br>+<br>+const struct pch_gpio_map mainboard_gpio_map = {<br>+ .set1 = {<br>+ .mode = &pch_gpio_set1_mode,<br>+ .direction = &pch_gpio_set1_direction,<br>+ .level = &pch_gpio_set1_level,<br>+ .blink = &pch_gpio_set1_blink,<br>+ .invert = &pch_gpio_set1_invert,<br>+ .reset = &pch_gpio_set1_reset,<br>+ },<br>+ .set2 = {<br>+ .mode = &pch_gpio_set2_mode,<br>+ .direction = &pch_gpio_set2_direction,<br>+ .level = &pch_gpio_set2_level,<br>+ .reset = &pch_gpio_set2_reset,<br>+ },<br>+ .set3 = {<br>+ .mode = &pch_gpio_set3_mode,<br>+ .direction = &pch_gpio_set3_direction,<br>+ .level = &pch_gpio_set3_level,<br>+ .reset = &pch_gpio_set3_reset,<br>+ },<br>+};<br>diff --git a/src/mainboard/hp/8460p/hda_verb.c b/src/mainboard/hp/8460p/hda_verb.c<br>new file mode 100644<br>index 0000000..8436707<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/hda_verb.c<br>@@ -0,0 +1,67 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2008-2009 coresystems GmbH<br>+ * Copyright (C) 2014 Vladimir Serbinenko<br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/azalia_device.h><br>+<br>+const u32 cim_verb_data[] = {<br>+ 0x111d7605, /* Codec Vendor / Device ID: IDT */<br>+ 0x103c3588, /* Subsystem ID */<br>+<br>+ 0x0000000b, /* Number of 4 dword sets */<br>+ /* NID 0x01: Subsystem ID. */<br>+ AZALIA_SUBVENDOR(0x0, 0x103c3588),<br>+<br>+ /* NID 0x0a. */<br>+ AZALIA_PIN_CFG(0x0, 0x0a, 0x40f000f0),<br>+<br>+ /* NID 0x0b. */<br>+ AZALIA_PIN_CFG(0x0, 0x0b, 0x0421401f),<br>+<br>+ /* NID 0x0c. */<br>+ AZALIA_PIN_CFG(0x0, 0x0c, 0x04a11020),<br>+<br>+ /* NID 0x0d. */<br>+ AZALIA_PIN_CFG(0x0, 0x0d, 0x90170110),<br>+<br>+ /* NID 0x0e. */<br>+ AZALIA_PIN_CFG(0x0, 0x0e, 0x40f000f0),<br>+<br>+ /* NID 0x0f. */<br>+ AZALIA_PIN_CFG(0x0, 0x0f, 0x40f000f0),<br>+<br>+ /* NID 0x10. */<br>+ AZALIA_PIN_CFG(0x0, 0x10, 0x40f000f0),<br>+<br>+ /* NID 0x11. */<br>+ AZALIA_PIN_CFG(0x0, 0x11, 0x90a60130),<br>+<br>+ /* NID 0x1f. */<br>+ AZALIA_PIN_CFG(0x0, 0x1f, 0x40f000f0),<br>+<br>+ /* NID 0x20. */<br>+ AZALIA_PIN_CFG(0x0, 0x20, 0x40f000f0),<br>+ 0x11c11040, /* Codec Vendor / Device ID: LSI */<br>+ 0x103c3066, /* Subsystem ID */<br>+<br>+ 0x00000001, /* Number of 4 dword sets */<br>+ /* NID 0x01: Subsystem ID. */<br>+ AZALIA_SUBVENDOR(0x1, 0x103c3066),<br>+};<br>+<br>+const u32 pc_beep_verbs[0] = {};<br>+<br>+AZALIA_ARRAY_SIZES;<br>diff --git a/src/mainboard/hp/8460p/mainboard.c b/src/mainboard/hp/8460p/mainboard.c<br>new file mode 100644<br>index 0000000..b5fdecc<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/mainboard.c<br>@@ -0,0 +1,28 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <device/device.h><br>+#include <drivers/intel/gma/int15.h><br>+<br>+static void mainboard_enable(device_t dev)<br>+{<br>+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,<br>+ GMA_INT15_PANEL_FIT_DEFAULT,<br>+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);<br>+}<br>+<br>+struct chip_operations mainboard_ops = {<br>+ .enable_dev = mainboard_enable,<br>+};<br>diff --git a/src/mainboard/hp/8460p/romstage.c b/src/mainboard/hp/8460p/romstage.c<br>new file mode 100644<br>index 0000000..7d228e9<br>--- /dev/null<br>+++ b/src/mainboard/hp/8460p/romstage.c<br>@@ -0,0 +1,82 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Iru Cai <mytbk920423@gmail.com><br>+ *<br>+ * This program is free software; you can redistribute it and/or<br>+ * modify it under the terms of the GNU General Public License as<br>+ * published by the Free Software Foundation; version 2 of<br>+ * the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <arch/io.h><br>+#include <northbridge/intel/sandybridge/sandybridge.h><br>+#include <northbridge/intel/sandybridge/raminit_native.h><br>+#include <southbridge/intel/bd82x6x/pch.h><br>+#include <superio/smsc/lpc47n217/lpc47n217.h><br>+#include <ec/hp/kbc1126/ec.h><br>+<br>+#define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)<br>+<br>+void pch_enable_lpc(void)<br>+{<br>+ /*<br>+ * CNF2 and CNF1 for Super I/O<br>+ * MC and LPC (0x60,0x64,0x62,0x66) for KBC and EC<br>+ * Enable parallel port and serial port<br>+ */<br>+ pci_write_config16(PCH_LPC_DEV, LPC_EN,<br>+ CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |<br>+ LPT_LPC_EN | COMA_LPC_EN);<br>+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);<br>+ /* Enable mailbox at 0x200/0x201 and PM1 at 0x220 */<br>+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x007c0201);<br>+}<br>+<br>+void rcba_config(void)<br>+{<br>+ RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0;<br>+}<br>+<br>+const struct southbridge_usb_port mainboard_usb_ports[] = {<br>+ { 1, 1, 0 },<br>+ { 1, 0, 0 },<br>+ { 0, 1, 1 },<br>+ { 1, 1, 1 },<br>+ { 1, 0, 2 },<br>+ { 1, 0, 2 },<br>+ { 0, 0, 3 },<br>+ { 1, 0, 3 },<br>+ { 1, 1, 4 },<br>+ { 1, 1, 4 },<br>+ { 1, 0, 5 },<br>+ { 1, 0, 5 },<br>+ { 1, 0, 6 },<br>+ { 1, 0, 6 },<br>+};<br>+<br>+void mainboard_early_init(int s3resume)<br>+{<br>+}<br>+<br>+void mainboard_config_superio(void)<br>+{<br>+ lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);<br>+ kbc1126_enter_conf();<br>+ kbc1126_mailbox_init();<br>+ kbc1126_kbc_init();<br>+ kbc1126_ec_init();<br>+ kbc1126_pm1_init();<br>+ kbc1126_exit_conf();<br>+}<br>+<br>+void mainboard_get_spd(spd_raw_data *spd, bool id_only)<br>+{<br>+ read_spd(&spd[0], 0x50, id_only);<br>+ read_spd(&spd[2], 0x52, id_only);<br>+}<br></pre><p>To view, visit <a href="https://review.coreboot.org/20501">change 20501</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/20501"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I9c42723ba240a2e9b46998c1a8a708aebc66c604 </div>
<div style="display:none"> Gerrit-Change-Number: 20501 </div>
<div style="display:none"> Gerrit-PatchSet: 12 </div>
<div style="display:none"> Gerrit-Owner: Iru Cai <mytbk920423@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Iru Cai <mytbk920423@gmail.com> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>