<p>Pratikkumar V Prajapati has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21081">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">[wip]soc/intel/cannonlake: Add cpu.c and MP init support<br><br>WIP.<br><br>Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d<br>Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com><br>---<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/chip.c<br>A src/soc/intel/cannonlake/cpu.c<br>M src/soc/intel/cannonlake/include/soc/ramstage.h<br>4 files changed, 297 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/21081/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 8a83eb0..414a8be 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -23,6 +23,7 @@<br> romstage-$(CONFIG_UART_DEBUG) += uart.c<br> <br> ramstage-y += chip.c<br>+ramstage-y += cpu.c<br> ramstage-y += gspi.c<br> ramstage-y += memmap.c<br> ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c<br>diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c<br>index 62181a3..b9b1560 100644<br>--- a/src/soc/intel/cannonlake/chip.c<br>+++ b/src/soc/intel/cannonlake/chip.c<br>@@ -29,6 +29,11 @@<br> fsp_silicon_init(romstage_handoff_is_resume());<br> }<br> <br>+void soc_fsp_load(void)<br>+{<br>+ fsps_load(romstage_handoff_is_resume());<br>+}<br>+<br> static void pci_domain_set_resources(device_t dev)<br> {<br> assign_resources(dev->link_list);<br>diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c<br>new file mode 100755<br>index 0000000..22cb7cd<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/cpu.c<br>@@ -0,0 +1,290 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright (C) 2017 Intel Corporation.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; version 2 of the License.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <assert.h><br>+#include <bootstate.h><br>+#include <console/console.h><br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <string.h><br>+#include <chip.h><br>+#include <cpu/cpu.h><br>+#include <cpu/x86/mtrr.h><br>+#include <cpu/x86/msr.h><br>+#include <cpu/x86/lapic.h><br>+#include <cpu/x86/mp.h><br>+#include <cpu/intel/microcode.h><br>+#include <cpu/intel/speedstep.h><br>+#include <cpu/intel/turbo.h><br>+#include <cpu/x86/cache.h><br>+#include <cpu/x86/name.h><br>+#include <cpu/x86/smm.h><br>+#include <delay.h><br>+#include <intelblocks/cpulib.h><br>+#include <intelblocks/fast_spi.h><br>+#include <intelblocks/mp_init.h><br>+#include <intelblocks/msr.h><br>+#include <intelblocks/sgx.h><br>+#include <pc80/mc146818rtc.h><br>+#include <romstage_handoff.h><br>+#include <soc/cpu.h><br>+#include <soc/msr.h><br>+#include <soc/pci_devs.h><br>+#include <soc/pm.h><br>+#include <soc/ramstage.h><br>+#include <intelblocks/smm.h><br>+#include <soc/systemagent.h><br>+<br>+#define EMULATE_DELAY_VALUE 0x13<br>+#define CTC_FREQ 19200000<br>+<br>+static void configure_isst(void)<br>+{<br>+ device_t dev = SA_DEV_ROOT;<br>+ config_t *conf = dev->chip_info;<br>+ msr_t msr;<br>+<br>+ if (conf->speed_shift_enable) {<br>+ /*<br>+ * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP<br>+ * is supported or not. coreboot needs to configure MSR 0x1AA<br>+ * which is then reflected in the CPUID register.<br>+ */<br>+ msr = rdmsr(MSR_MISC_PWR_MGMT);<br>+ msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */<br>+ msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */<br>+ msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */<br>+ wrmsr(MSR_MISC_PWR_MGMT, msr);<br>+ } else {<br>+ msr = rdmsr(MSR_MISC_PWR_MGMT);<br>+ msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */<br>+ msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */<br>+ msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */<br>+ wrmsr(MSR_MISC_PWR_MGMT, msr);<br>+ }<br>+}<br>+<br>+static void configure_misc(void)<br>+{<br>+ device_t dev = SA_DEV_ROOT;<br>+ config_t *conf = dev->chip_info;<br>+ msr_t msr;<br>+<br>+ msr = rdmsr(IA32_MISC_ENABLE);<br>+ msr.lo |= (1 << 0); /* Fast String enable */<br>+ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */<br>+ if (conf->eist_enable)<br>+ cpu_enable_eist();<br>+ else<br>+ cpu_disable_eist();<br>+ wrmsr(IA32_MISC_ENABLE, msr);<br>+<br>+ /* Disable Thermal interrupts */<br>+ msr.lo = 0;<br>+ msr.hi = 0;<br>+ wrmsr(IA32_THERM_INTERRUPT, msr);<br>+<br>+ /* Enable package critical interrupt only */<br>+ msr.lo = 1 << 4;<br>+ msr.hi = 0;<br>+ wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);<br>+<br>+ /* Enable PROCHOT */<br>+ msr = rdmsr(MSR_POWER_CTL);<br>+ msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/<br>+ msr.lo |= (1 << 23); /* Lock it */<br>+ wrmsr(MSR_POWER_CTL, msr);<br>+}<br>+<br>+static void enable_lapic_tpr(void)<br>+{<br>+ msr_t msr;<br>+<br>+ msr = rdmsr(MSR_PIC_MSG_CONTROL);<br>+ msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */<br>+ wrmsr(MSR_PIC_MSG_CONTROL, msr);<br>+}<br>+<br>+static void configure_dca_cap(void)<br>+{<br>+ struct cpuid_result cpuid_regs;<br>+ msr_t msr;<br>+<br>+ /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */<br>+ cpuid_regs = cpuid(1);<br>+ if (cpuid_regs.ecx & (1 << 18)) {<br>+ msr = rdmsr(IA32_PLATFORM_DCA_CAP);<br>+ msr.lo |= 1;<br>+ wrmsr(IA32_PLATFORM_DCA_CAP, msr);<br>+ }<br>+}<br>+<br>+static void set_energy_perf_bias(u8 policy)<br>+{<br>+ msr_t msr;<br>+ int ecx;<br>+<br>+ /* Determine if energy efficient policy is supported. */<br>+ ecx = cpuid_ecx(0x6);<br>+ if (!(ecx & (1 << 3)))<br>+ return;<br>+<br>+ /* Energy Policy is bits 3:0 */<br>+ msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);<br>+ msr.lo &= ~0xf;<br>+ msr.lo |= policy & 0xf;<br>+ wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);<br>+}<br>+<br>+static void configure_mca(void)<br>+{<br>+ msr_t msr;<br>+ int i;<br>+ int num_banks;<br>+<br>+ msr = rdmsr(IA32_MCG_CAP);<br>+ num_banks = msr.lo & 0xff;<br>+ msr.lo = msr.hi = 0;<br>+ /*<br>+ * TODO(adurbin): This should only be done on a cold boot. Also, some<br>+ * of these banks are core vs package scope. For now every CPU clears<br>+ * every bank.<br>+ */<br>+ for (i = 0; i < num_banks; i++) {<br>+ /* Clear the machine check status */<br>+ wrmsr(IA32_MC0_STATUS + (i * 4), msr);<br>+ /* Initialize machine checks */<br>+ wrmsr(IA32_MC0_CTL + i * 4,<br>+ (msr_t) {.lo = 0xffffffff, .hi = 0xffffffff});<br>+ }<br>+}<br>+<br>+static void configure_c_states(void)<br>+{<br>+ msr_t msr;<br>+<br>+ /* C-state Interrupt Response Latency Control 0 - package C3 latency */<br>+ msr.hi = 0;<br>+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT;<br>+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr);<br>+<br>+ /* C-state Interrupt Response Latency Control 1 - package C6/C7 short */<br>+ msr.hi = 0;<br>+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT;<br>+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr);<br>+<br>+ /* C-state Interrupt Response Latency Control 2 - package C6/C7 long */<br>+ msr.hi = 0;<br>+ msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT;<br>+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);<br>+<br>+ /* C-state Interrupt Response Latency Control 3 - package C8 */<br>+ msr.hi = 0;<br>+ msr.lo = IRTL_VALID | IRTL_1024_NS |<br>+ C_STATE_LATENCY_CONTROL_3_LIMIT;<br>+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr);<br>+<br>+ /* C-state Interrupt Response Latency Control 4 - package C9 */<br>+ msr.hi = 0;<br>+ msr.lo = IRTL_VALID | IRTL_1024_NS |<br>+ C_STATE_LATENCY_CONTROL_4_LIMIT;<br>+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr);<br>+<br>+ /* C-state Interrupt Response Latency Control 5 - package C10 */<br>+ msr.hi = 0;<br>+ msr.lo = IRTL_VALID | IRTL_1024_NS |<br>+ C_STATE_LATENCY_CONTROL_5_LIMIT;<br>+ wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);<br>+}<br>+<br>+/* All CPUs including BSP will run the following function. */<br>+void soc_core_init(device_t cpu, const void *microcode)<br>+{<br>+<br>+ /* Clear out pending MCEs */<br>+ configure_mca();<br>+<br>+ /* Enable the local CPU apics */<br>+ enable_lapic_tpr();<br>+ setup_lapic();<br>+<br>+ /* Configure c-state interrupt response time */<br>+ configure_c_states();<br>+<br>+ /* Configure Enhanced SpeedStep and Thermal Sensors */<br>+ configure_misc();<br>+<br>+ /* Configure Intel Speed Shift */<br>+ configure_isst();<br>+<br>+ /* Enable Direct Cache Access */<br>+ configure_dca_cap();<br>+<br>+ /* Set energy policy */<br>+ set_energy_perf_bias(ENERGY_POLICY_NORMAL);<br>+<br>+ /* Enable Turbo */<br>+ enable_turbo();<br>+<br>+}<br>+<br>+static int adjust_apic_id(int index, int apic_id)<br>+{<br>+ unsigned int num_cores, num_threads;<br>+<br>+ if (cpu_read_topology(&num_cores, &num_threads))<br>+ return 2 * index;<br>+ else<br>+ return index;<br>+}<br>+<br>+static void post_mp_init(void)<br>+{<br>+ /* Set Max Ratio */<br>+ cpu_set_max_ratio();<br>+<br>+ /*<br>+ * Now that all APs have been relocated as well as the BSP let SMIs<br>+ * start flowing.<br>+ */<br>+ //southbridge_smm_enable_smi();<br>+<br>+ /* Lock down the SMRAM space. */<br>+#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)<br>+ smm_lock();<br>+#endif<br>+}<br>+<br>+<br>+static const struct mp_ops mp_ops = {<br>+ /*<br>+ * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,<br>+ * that are set prior to ramstage.<br>+ * Real MTRRs programming are being done after resource allocation.<br>+ */<br>+ .pre_mp_init = soc_fsp_load,<br>+ .get_cpu_count = get_cpu_count,<br>+ .get_microcode_info = get_microcode_info,<br>+ .adjust_cpu_apic_entry = adjust_apic_id,<br>+ .post_mp_init = post_mp_init,<br>+};<br>+<br>+void soc_init_cpus(struct bus *cpu_bus, const void *microcode)<br>+{<br>+ if (mp_init_with_smm(cpu_bus, &mp_ops))<br>+ printk(BIOS_ERR, "MP initialization failure.");<br>+<br>+}<br>+<br>diff --git a/src/soc/intel/cannonlake/include/soc/ramstage.h b/src/soc/intel/cannonlake/include/soc/ramstage.h<br>index 4a96185..29ad9d2 100644<br>--- a/src/soc/intel/cannonlake/include/soc/ramstage.h<br>+++ b/src/soc/intel/cannonlake/include/soc/ramstage.h<br>@@ -24,5 +24,6 @@<br> <br> void mainboard_silicon_init_params(FSP_S_CONFIG *params);<br> void soc_init_pre_device(void *chip_info);<br>+void soc_fsp_load(void);<br> <br> #endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/21081">change 21081</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21081"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ia33691c17c663d704abf65320d4bf1262239524d </div>
<div style="display:none"> Gerrit-Change-Number: 21081 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>