<p>Barnali Sarkar has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21064">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/skylake: Move SPI lock down config after PCI enumeration<br><br>This patch to ensures that coreboot is meeting Intel Silicon<br>recommendation to performing register lockdown.<br><br>TEST=Ensure SPIBAR+HSFSTS(0x04) register FLOCKDN bit and WRSDIS<br>bit is set. Also, Bits 8-12 of SPIBAR+DLOCK(0x0C) register is set.<br><br>Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5<br>Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com><br>---<br>M src/soc/intel/skylake/finalize.c<br>M src/soc/intel/skylake/lockdown.c<br>2 files changed, 38 insertions(+), 19 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/21064/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c<br>index aed7e87..42d67ec 100644<br>--- a/src/soc/intel/skylake/finalize.c<br>+++ b/src/soc/intel/skylake/finalize.c<br>@@ -21,7 +21,6 @@<br> #include <console/post_codes.h><br> #include <cpu/x86/smm.h><br> #include <device/pci.h><br>-#include <intelblocks/fast_spi.h><br> #include <intelblocks/pcr.h><br> #include <reg_script.h><br> #include <spi-generic.h><br>@@ -90,12 +89,6 @@<br> config_t *config;<br> u8 reg8;<br> <br>- /* Set FAST_SPI opcode menu */<br>- fast_spi_set_opcode_menu();<br>-<br>- /* Lock FAST_SPIBAR */<br>- fast_spi_lock_bar();<br>-<br> /* Display me status before we hide it */<br> intel_me_status();<br> <br>@@ -142,18 +135,6 @@<br> reg8 |= SMI_LOCK;<br> pci_write_config8(dev, GEN_PMCON_A, reg8);<br> }<br>-<br>- /* Bios Interface Lock */<br>- if (config->LockDownConfigBiosInterface == 0)<br>- fast_spi_set_bios_interface_lock_down();<br>-<br>- /* Bios Lock */<br>- if (config->LockDownConfigBiosLock == 0)<br>- fast_spi_set_lock_enable();<br>-<br>- /* SPIEiss */<br>- if (config->LockDownConfigSpiEiss == 0)<br>- fast_spi_set_eiss();<br> }<br> <br> static void soc_finalize(void *unused)<br>diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c<br>index e31cf09..cddb87b 100644<br>--- a/src/soc/intel/skylake/lockdown.c<br>+++ b/src/soc/intel/skylake/lockdown.c<br>@@ -17,6 +17,7 @@<br> #include <bootstate.h><br> #include <chip.h><br> #include <console/console.h><br>+#include <intelblocks/fast_spi.h><br> #include <intelblocks/pcr.h><br> #include <soc/lpc.h><br> #include <soc/pci_devs.h><br>@@ -79,6 +80,40 @@<br> pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD);<br> }<br> <br>+static void spi_lockdown_config(void)<br>+{<br>+ static struct soc_intel_skylake_config *config;<br>+ struct device *dev;<br>+<br>+ /* Set FAST_SPI opcode menu */<br>+ fast_spi_set_opcode_menu();<br>+<br>+ /* Discrete Lock Flash PR registers */<br>+ fast_spi_pr_dlock();<br>+<br>+ /* Lock FAST_SPIBAR */<br>+ fast_spi_lock_bar();<br>+<br>+ dev = PCH_DEV_SPI;<br>+ /* Check if SPI is enabled, else return */<br>+ if (dev == NULL || dev->chip_info == NULL)<br>+ return;<br>+<br>+ config = dev->chip_info;<br>+<br>+ /* Bios Interface Lock */<br>+ if (config->LockDownConfigBiosInterface == 0)<br>+ fast_spi_set_bios_interface_lock_down();<br>+<br>+ /* Bios Lock */<br>+ if (config->LockDownConfigBiosLock == 0)<br>+ fast_spi_set_lock_enable();<br>+<br>+ /* SPIEiss */<br>+ if (config->LockDownConfigSpiEiss == 0)<br>+ fast_spi_set_eiss();<br>+}<br>+<br> static void platform_lockdown_config(void *unused)<br> {<br> /* LPC lock down configuration */<br>@@ -89,6 +124,9 @@<br> <br> /* DMI lock down configuration */<br> dmi_lockdown_config();<br>+<br>+ /* SPI lock down configuration */<br>+ spi_lockdown_config();<br> }<br> <br> BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config,<br></pre><p>To view, visit <a href="https://review.coreboot.org/21064">change 21064</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21064"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5 </div>
<div style="display:none"> Gerrit-Change-Number: 21064 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Barnali Sarkar <barnali.sarkar@intel.com> </div>