<p>Martin Roth has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21073">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/amd: Standardize guards on header files<br><br>The guards in the header files were inconsistent. Some had no leading or<br>trailing underscores, some had one, some had both leading and trailing.<br><br>Change all to double leading & trailing underscores.<br><br>BUG=b:62235990<br>Test=Build Kahlee<br><br>Change-Id: I4466df529ab201c922096a31d7438381778b582f<br>Signed-off-by: Martin Roth <martinroth@google.com><br>---<br>M src/soc/amd/common/BiosCallOuts.h<br>M src/soc/amd/common/agesawrapper.h<br>M src/soc/amd/common/agesawrapper_call.h<br>M src/soc/amd/common/amd_defs.h<br>M src/soc/amd/common/amd_pci_util.h<br>M src/soc/amd/common/block/include/amdblocks/psp.h<br>M src/soc/amd/common/dimmSpd.h<br>M src/soc/amd/stoneyridge/chip.h<br>M src/soc/amd/stoneyridge/include/amd_pci_int_defs.h<br>M src/soc/amd/stoneyridge/include/amd_pci_int_types.h<br>M src/soc/amd/stoneyridge/include/soc/acpi.h<br>M src/soc/amd/stoneyridge/include/soc/gpio.h<br>M src/soc/amd/stoneyridge/include/soc/imc.h<br>M src/soc/amd/stoneyridge/include/soc/northbridge.h<br>M src/soc/amd/stoneyridge/include/soc/nvs.h<br>M src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>M src/soc/amd/stoneyridge/include/soc/smbus.h<br>M src/soc/amd/stoneyridge/include/soc/smi.h<br>M src/soc/amd/stoneyridge/include/soc/southbridge.h<br>19 files changed, 54 insertions(+), 54 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/21073/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/amd/common/BiosCallOuts.h b/src/soc/amd/common/BiosCallOuts.h<br>index 50931dc..4456466 100644<br>--- a/src/soc/amd/common/BiosCallOuts.h<br>+++ b/src/soc/amd/common/BiosCallOuts.h<br>@@ -14,8 +14,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef CALLOUTS_AMD_AGESA_H<br>-#define CALLOUTS_AMD_AGESA_H<br>+#ifndef __CALLOUTS_AMD_AGESA_H__<br>+#define __CALLOUTS_AMD_AGESA_H__<br> <br> #include <Porting.h><br> #include <AGESA.h><br>@@ -64,4 +64,4 @@<br> extern const BIOS_CALLOUT_STRUCT BiosCallouts[];<br> extern const int BiosCalloutsLen;<br> <br>-#endif /* CALLOUTS_AMD_AGESA_H */<br>+#endif /* __CALLOUTS_AMD_AGESA_H__ */<br>diff --git a/src/soc/amd/common/agesawrapper.h b/src/soc/amd/common/agesawrapper.h<br>index 97d52f7..b42f531 100644<br>--- a/src/soc/amd/common/agesawrapper.h<br>+++ b/src/soc/amd/common/agesawrapper.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef _AGESAWRAPPER_H_<br>-#define _AGESAWRAPPER_H_<br>+#ifndef __AGESAWRAPPER_H__<br>+#define __AGESAWRAPPER_H__<br> <br> #include <stdint.h><br> #include <Porting.h><br>@@ -56,4 +56,4 @@<br> <br> void OemPostParams(AMD_POST_PARAMS *PostParams);<br> <br>-#endif /* _AGESAWRAPPER_H_ */<br>+#endif /* __AGESAWRAPPER_H__ */<br>diff --git a/src/soc/amd/common/agesawrapper_call.h b/src/soc/amd/common/agesawrapper_call.h<br>index 64c97f6..21a1e23 100644<br>--- a/src/soc/amd/common/agesawrapper_call.h<br>+++ b/src/soc/amd/common/agesawrapper_call.h<br>@@ -11,8 +11,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef _AGESAWRAPPER_CALL_H_<br>-#define _AGESAWRAPPER_CALL_H_<br>+#ifndef __AGESAWRAPPER_CALL_H__<br>+#define __AGESAWRAPPER_CALL_H__<br> <br> #include <stdint.h><br> #include <console/console.h><br>@@ -56,4 +56,4 @@<br> <br> #define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func()<br> <br>-#endif<br>+#endif /* __AGESAWRAPPER_CALL_H__ */<br>diff --git a/src/soc/amd/common/amd_defs.h b/src/soc/amd/common/amd_defs.h<br>index 55db30f..e4ce1db 100644<br>--- a/src/soc/amd/common/amd_defs.h<br>+++ b/src/soc/amd/common/amd_defs.h<br>@@ -14,8 +14,8 @@<br>  */<br> <br> <br>-#ifndef _AMD_SB_DEFS_H_<br>-#define _AMD_SB_DEFS_H_<br>+#ifndef __AMD_SB_DEFS_H__<br>+#define __AMD_SB_DEFS_H__<br> <br> #define AMD_SB_ACPI_MMIO_ADDR 0xfed80000ul<br> <br>diff --git a/src/soc/amd/common/amd_pci_util.h b/src/soc/amd/common/amd_pci_util.h<br>index 4789542..b8d48ef 100644<br>--- a/src/soc/amd/common/amd_pci_util.h<br>+++ b/src/soc/amd/common/amd_pci_util.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef AMD_PCI_UTIL_H<br>-#define AMD_PCI_UTIL_H<br>+#ifndef __AMD_PCI_UTIL_H__<br>+#define __AMD_PCI_UTIL_H__<br> <br> #include <stdint.h><br> #include <amd_pci_int_defs.h><br>@@ -38,4 +38,4 @@<br> void write_pci_cfg_irqs(void);<br> void write_pci_int_table(void);<br> <br>-#endif /* AMD_PCI_UTIL_H */<br>+#endif /* __AMD_PCI_UTIL_H__ */<br>diff --git a/src/soc/amd/common/block/include/amdblocks/psp.h b/src/soc/amd/common/block/include/amdblocks/psp.h<br>index c70c0b1..42b9fb7 100644<br>--- a/src/soc/amd/common/block/include/amdblocks/psp.h<br>+++ b/src/soc/amd/common/block/include/amdblocks/psp.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef AMD_PSP_H<br>-#define AMD_PSP_H<br>+#ifndef __AMD_PSP_H__<br>+#define __AMD_PSP_H__<br> <br> #include <stdint.h><br> #include <compiler.h><br>@@ -94,4 +94,4 @@<br> /* BIOS-to-PSP functions return 0 if successful, else negative value */<br> int psp_notify_dram(void);<br> <br>-#endif /* AMD_PSP_H */<br>+#endif /* __AMD_PSP_H__ */<br>diff --git a/src/soc/amd/common/dimmSpd.h b/src/soc/amd/common/dimmSpd.h<br>index 75a7990..cdcdb73 100644<br>--- a/src/soc/amd/common/dimmSpd.h<br>+++ b/src/soc/amd/common/dimmSpd.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef _DIMMSPD_H_<br>-#define _DIMMSPD_H_<br>+#ifndef __DIMMSPD_H__<br>+#define __DIMMSPD_H__<br> <br> AGESA_STATUS<br> AmdMemoryReadSPD(IN UINT32 Func, IN UINTN Data,<br>diff --git a/src/soc/amd/stoneyridge/chip.h b/src/soc/amd/stoneyridge/chip.h<br>index 747c295..cd3bc74 100644<br>--- a/src/soc/amd/stoneyridge/chip.h<br>+++ b/src/soc/amd/stoneyridge/chip.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef STONEYRIDGE_CHIP_H<br>-#define STONEYRIDGE_CHIP_H<br>+#ifndef __STONEYRIDGE_CHIP_H__<br>+#define __STONEYRIDGE_CHIP_H__<br> <br> #include <stdint.h><br> <br>@@ -32,4 +32,4 @@<br> <br> extern struct device_operations pci_domain_ops;<br> <br>-#endif /* STONEYRIDGE_CHIP_H */<br>+#endif /* __STONEYRIDGE_CHIP_H__ */<br>diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h<br>index f3f60d3..a8e75f63 100644<br>--- a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h<br>+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef AMD_PCI_INT_DEFS_H<br>-#define AMD_PCI_INT_DEFS_H<br>+#ifndef __AMD_PCI_INT_DEFS_H__<br>+#define __AMD_PCI_INT_DEFS_H__<br> <br> /*<br>  * PIRQ and device routing - these define the index<br>@@ -72,4 +72,4 @@<br> #define PIRQ_UART0      0x74<br> #define PIRQ_UART1       0x75<br> <br>-#endif /* AMD_PCI_INT_DEFS_H */<br>+#endif /* __AMD_PCI_INT_DEFS_H__ */<br>diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h<br>index ab1f70b..08bdc10 100644<br>--- a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h<br>+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef AMD_PCI_INT_TYPES_H<br>-#define AMD_PCI_INT_TYPES_H<br>+#ifndef __AMD_PCI_INT_TYPES_H__<br>+#define __AMD_PCI_INT_TYPES_H__<br> <br> const char *intr_types[] = {<br>  [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t",<br>@@ -34,4 +34,4 @@<br>  [0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t",<br> };<br> <br>-#endif /* AMD_PCI_INT_TYPES_H */<br>+#endif /* __AMD_PCI_INT_TYPES_H__ */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/acpi.h b/src/soc/amd/stoneyridge/include/soc/acpi.h<br>index f573b0e..0452567 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/acpi.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/acpi.h<br>@@ -15,8 +15,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef _SOC_STONEYRIDGE_ACPI_H_<br>-#define _SOC_STONEYRIDGE_ACPI_H_<br>+#ifndef __SOC_STONEYRIDGE_ACPI_H__<br>+#define __SOC_STONEYRIDGE_ACPI_H__<br> <br> #include <arch/acpi.h><br> <br>@@ -35,4 +35,4 @@<br> <br> void southbridge_inject_dsdt(device_t device);<br> <br>-#endif     /* _SOC_STONEYRIDGE_ACPI_H_ */<br>+#endif /* __SOC_STONEYRIDGE_ACPI_H__ */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h<br>index c43dd27..278bb34 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/gpio.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef _STONEYRIDGE_GPIO_H_<br>-#define _STONEYRIDGE_GPIO_H_<br>+#ifndef __STONEYRIDGE_GPIO_H__<br>+#define __STONEYRIDGE_GPIO_H__<br> <br> #include <soc/amd/common/amd_defs.h><br> #include <types.h><br>@@ -129,4 +129,4 @@<br> <br> typedef uint32_t gpio_t;<br> <br>-#endif       /* _STONEYRIDGE_GPIO_H_ */<br>+#endif     /* __STONEYRIDGE_GPIO_H__ */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/imc.h b/src/soc/amd/stoneyridge/include/soc/imc.h<br>index 3d0e740..f2aed2e 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/imc.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/imc.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef STONEYRIDGE_IMC_H<br>-#define STONEYRIDGE_IMC_H<br>+#ifndef __STONEYRIDGE_IMC_H__<br>+#define __STONEYRIDGE_IMC_H__<br> <br> #include <Porting.h><br> #include <AGESA.h><br>diff --git a/src/soc/amd/stoneyridge/include/soc/northbridge.h b/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>index e082a9d..13d7d36 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/northbridge.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef PI_STONEYRIDGE_NORTHBRIDGE_H<br>-#define PI_STONEYRIDGE_NORTHBRIDGE_H<br>+#ifndef __PI_STONEYRIDGE_NORTHBRIDGE_H__<br>+#define __PI_STONEYRIDGE_NORTHBRIDGE_H__<br> <br> #include <arch/cpu.h><br> #include <arch/io.h><br>@@ -30,4 +30,4 @@<br> /* todo: remove this when postcar stage is in place */<br> asmlinkage void chipset_teardown_car(void);<br> <br>-#endif /* PI_STONEYRIDGE_NORTHBRIDGE_H */<br>+#endif /* __PI_STONEYRIDGE_NORTHBRIDGE_H__ */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h<br>index b28f386..4219fa3 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/nvs.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h<br>@@ -21,8 +21,8 @@<br>  *<br>  */<br> <br>-#ifndef _SOC_STONEYRIDGE_NVS_H_<br>-#define _SOC_STONEYRIDGE_NVS_H_<br>+#ifndef __SOC_STONEYRIDGE_NVS_H__<br>+#define __SOC_STONEYRIDGE_NVS_H__<br> <br> #include <stdint.h><br> #include <vendorcode/google/chromeos/gnvs.h><br>@@ -48,4 +48,4 @@<br>     chromeos_acpi_t chromeos;<br> } __attribute__((packed)) global_nvs_t;<br> <br>-#endif /* _SOC_STONEYRIDGE_NVS_H_ */<br>+#endif  /* __SOC_STONEYRIDGE_NVS_H__ */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>index 8bea376..5c7f86a 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef _PI_STONEYRIDGE_PCI_DEVS_H_<br>-#define _PI_STONEYRIDGE_PCI_DEVS_H_<br>+#ifndef __PI_STONEYRIDGE_PCI_DEVS_H__<br>+#define __PI_STONEYRIDGE_PCI_DEVS_H__<br> <br> #include <device/pci_def.h><br> #include <rules.h><br>@@ -285,4 +285,4 @@<br> #define SD_DEVID            0x7906<br> #define SD_DEVFN               PCI_DEVFN(SD_DEV, SD_FUNC)<br> <br>-#endif /* _PI_STONEYRIDGE_PCI_DEVS_H_ */<br>+#endif /* __PI_STONEYRIDGE_PCI_DEVS_H__ */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h<br>index c9b19e5..1379e19 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/smbus.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/smbus.h<br>@@ -13,8 +13,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef STONEYRIDGE_SMBUS_H<br>-#define STONEYRIDGE_SMBUS_H<br>+#ifndef __STONEYRIDGE_SMBUS_H__<br>+#define __STONEYRIDGE_SMBUS_H__<br> <br> #include <stdint.h><br> <br>@@ -67,4 +67,4 @@<br> void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);<br> void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val);<br> <br>-#endif    /* STONEYRIDGE_SMBUS_H */<br>+#endif      /* __STONEYRIDGE_SMBUS_H__ */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h<br>index 193fb0c..46004c9 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/smi.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/smi.h<br>@@ -5,8 +5,8 @@<br>  * Subject to the GNU GPL v2, or (at your option) any later version.<br>  */<br> <br>-#ifndef _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H<br>-#define _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H<br>+#ifndef __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__<br>+#define __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__<br> <br> #include <arch/io.h><br> <br>@@ -62,4 +62,4 @@<br> void enable_smi_generation(void);<br> #endif<br> <br>-#endif /* _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H */<br>+#endif /* __SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H__ */<br>diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>index de481f0..20edf5f 100644<br>--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h<br>@@ -14,8 +14,8 @@<br>  * GNU General Public License for more details.<br>  */<br> <br>-#ifndef STONEYRIDGE_H<br>-#define STONEYRIDGE_H<br>+#ifndef __STONEYRIDGE_H__<br>+#define __STONEYRIDGE_H__<br> <br> #include <arch/io.h><br> #include <types.h><br>@@ -204,4 +204,4 @@<br> int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);<br> void bootblock_fch_early_init(void);<br> <br>-#endif /* STONEYRIDGE_H */<br>+#endif /* __STONEYRIDGE_H__ */<br></pre><p>To view, visit <a href="https://review.coreboot.org/21073">change 21073</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21073"/><meta itemprop="name" content="View Change"/></div></div>

<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: I4466df529ab201c922096a31d7438381778b582f </div>
<div style="display:none"> Gerrit-Change-Number: 21073 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Martin Roth <martinroth@google.com> </div>