<p>Lijian Zhao has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21052">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">soc/intel/cannonlake: Add SPI flash controller driver<br><br>Add SPI driver code for the SPI flash controller, including both<br>fast_spi and generic_spi.<br><br>Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd<br>Signed-off-by: Lijian Zhao <lijian.zhao@intel.com><br>---<br>M src/soc/intel/cannonlake/Kconfig<br>M src/soc/intel/cannonlake/Makefile.inc<br>M src/soc/intel/cannonlake/chip.h<br>A src/soc/intel/cannonlake/gspi.c<br>M src/soc/intel/cannonlake/include/soc/pci_devs.h<br>A src/soc/intel/cannonlake/spi.c<br>6 files changed, 163 insertions(+), 0 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/21052/4</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig<br>index 311cfb8..1b6759c 100644<br>--- a/src/soc/intel/cannonlake/Kconfig<br>+++ b/src/soc/intel/cannonlake/Kconfig<br>@@ -11,6 +11,8 @@<br> select ARCH_RAMSTAGE_X86_32<br> select ARCH_ROMSTAGE_X86_32<br> select ARCH_VERSTAGE_X86_32<br>+ select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH<br>+ select BOOT_DEVICE_SUPPORTS_WRITES<br> select C_ENVIRONMENT_BOOTBLOCK<br> select CPU_INTEL_FIRMWARE_INTERFACE_TABLE<br> select HAVE_HARD_RESET<br>@@ -29,6 +31,7 @@<br> select SOC_INTEL_COMMON_BLOCK_CSE<br> select SOC_INTEL_COMMON_BLOCK_FAST_SPI<br> select SOC_INTEL_COMMON_BLOCK_GPIO<br>+ select SOC_INTEL_COMMON_BLOCK_GSPI<br> select SOC_INTEL_COMMON_BLOCK_LPSS<br> select SOC_INTEL_COMMON_BLOCK_PCR<br> select SOC_INTEL_COMMON_BLOCK_RTC<br>@@ -38,6 +41,7 @@<br> select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP<br> select SOC_INTEL_COMMON_BLOCK_TIMER<br> select SOC_INTEL_COMMON_BLOCK_UART<br>+ select SOC_INTEL_COMMON_SPI_FLASH_PROTECT<br> select SOC_INTEL_COMMON_RESET<br> select SUPPORT_CPU_UCODE_IN_CBFS<br> select TSC_CONSTANT_RATE<br>@@ -78,6 +82,11 @@<br> int<br> default 100<br> <br>+<br>+config SOC_INTEL_COMMON_BLOCK_GSPI_MAX<br>+ int<br>+ default 3<br>+<br> # Clock divider parameters for 115200 baud rate<br> config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL<br> hex<br>diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc<br>index 297d34f..8a83eb0 100644<br>--- a/src/soc/intel/cannonlake/Makefile.inc<br>+++ b/src/soc/intel/cannonlake/Makefile.inc<br>@@ -11,20 +11,27 @@<br> bootblock-y += bootblock/pch.c<br> bootblock-y += bootblock/report_platform.c<br> bootblock-y += gpio.c<br>+bootblock-y += gspi.c<br> bootblock-y += memmap.c<br>+bootblock-y += spi.c<br> bootblock-$(CONFIG_UART_DEBUG) += uart.c<br> <br>+romstage-y += gspi.c<br> romstage-y += memmap.c<br> romstage-y += reset.c<br>+romstage-y += spi.c<br> romstage-$(CONFIG_UART_DEBUG) += uart.c<br> <br> ramstage-y += chip.c<br>+ramstage-y += gspi.c<br> ramstage-y += memmap.c<br> ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c<br>+ramstage-y += spi.c<br> ramstage-y += systemagent.c<br> ramstage-$(CONFIG_UART_DEBUG) += uart.c<br> <br> postcar-y += memmap.c<br>+postcar-y += spi.c<br> postcar-$(CONFIG_UART_DEBUG) += uart.c<br> <br> CPPFLAGS_common += -I$(src)/soc/intel/cannonlake/include/fsp20<br>diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h<br>index bbc5880..67be85d 100644<br>--- a/src/soc/intel/cannonlake/chip.h<br>+++ b/src/soc/intel/cannonlake/chip.h<br>@@ -18,9 +18,12 @@<br> #ifndef _SOC_CHIP_H_<br> #define _SOC_CHIP_H_<br> <br>+#include <intelblocks/gspi.h><br> #include <stdint.h><br> <br> struct soc_intel_cannonlake_config {<br>+ /* GSPI */<br>+ struct gspi_cfg gspi[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];<br> };<br> <br> typedef struct soc_intel_cannonlake_config config_t;<br>diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c<br>new file mode 100644<br>index 0000000..a1ebfba<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/gspi.c<br>@@ -0,0 +1,71 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <assert.h><br>+#include <device/device.h><br>+#include <intelblocks/gspi.h><br>+#include <soc/iomap.h><br>+#include <soc/pci_devs.h><br>+#include "chip.h"<br>+<br>+const struct gspi_cfg *gspi_get_soc_cfg(void)<br>+{<br>+ DEVTREE_CONST struct soc_intel_cannonlake_config *config;<br>+ int devfn = SA_DEVFN_ROOT;<br>+ DEVTREE_CONST struct device *dev = dev_find_slot(0, devfn);<br>+<br>+ if (!dev || !dev->chip_info) {<br>+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",<br>+ __func__);<br>+ return NULL;<br>+ }<br>+<br>+ config = dev->chip_info;<br>+<br>+ return &config->gspi[0];<br>+}<br>+<br>+uintptr_t gspi_get_soc_early_base(void)<br>+{<br>+ return EARLY_GSPI_BASE_ADDRESS;<br>+}<br>+<br>+/*<br>+ * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust<br>+ * the bus # accordingly when referring to SPI / GSPI bus numbers.<br>+ */<br>+#define GSPI_TO_SPI_BUS(x) ((x) + 1)<br>+#define SPI_TO_GSPI_BUS(x) ((x) - 1)<br>+<br>+int gspi_soc_spi_to_gspi_bus(unsigned int spi_bus, unsigned int *gspi_bus)<br>+{<br>+ if (spi_bus == 0)<br>+ return -1;<br>+<br>+ *gspi_bus = SPI_TO_GSPI_BUS(spi_bus);<br>+ if (*gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)<br>+ return -1;<br>+<br>+ return 0;<br>+}<br>+<br>+int gspi_soc_bus_to_devfn(unsigned int gspi_bus)<br>+{<br>+ if (gspi_bus >= CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX)<br>+ return -1;<br>+<br>+ return spi_bus_to_devfn(GSPI_TO_SPI_BUS(gspi_bus));<br>+}<br>diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h<br>index f00ea1f..ed6b670 100644<br>--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h<br>+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h<br>@@ -173,6 +173,7 @@<br> case PCH_DEVFN_SPI: return 0;<br> case PCH_DEVFN_GSPI0: return 1;<br> case PCH_DEVFN_GSPI1: return 2;<br>+ case PCH_DEVFN_GSPI2: return 3;<br> }<br> return -1;<br> }<br>@@ -183,6 +184,7 @@<br> case 0: return PCH_DEVFN_SPI;<br> case 1: return PCH_DEVFN_GSPI0;<br> case 2: return PCH_DEVFN_GSPI1;<br>+ case 3: return PCH_DEVFN_GSPI2;<br> }<br> return -1;<br> }<br>diff --git a/src/soc/intel/cannonlake/spi.c b/src/soc/intel/cannonlake/spi.c<br>new file mode 100644<br>index 0000000..1d65dee<br>--- /dev/null<br>+++ b/src/soc/intel/cannonlake/spi.c<br>@@ -0,0 +1,71 @@<br>+/*<br>+ * This file is part of the coreboot project.<br>+ *<br>+ * Copyright 2017 Google Inc.<br>+ *<br>+ * This program is free software; you can redistribute it and/or modify<br>+ * it under the terms of the GNU General Public License as published by<br>+ * the Free Software Foundation; either version 2 of the License, or<br>+ * (at your option) any later version.<br>+ *<br>+ * This program is distributed in the hope that it will be useful,<br>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>+ * GNU General Public License for more details.<br>+ */<br>+<br>+#include <console/console.h><br>+#include <device/device.h><br>+#include <device/pci.h><br>+#include <device/pci_def.h><br>+#include <device/pci_ids.h><br>+#include <device/spi.h><br>+#include <intelblocks/fast_spi.h><br>+#include <intelblocks/gspi.h><br>+#include <soc/ramstage.h><br>+#include <soc/pci_devs.h><br>+#include <spi-generic.h><br>+<br>+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {<br>+ { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 },<br>+#if !ENV_SMM<br>+ { .ctrlr = &gspi_ctrlr, .bus_start = 1,<br>+ .bus_end = 1 + (CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX - 1)},<br>+#endif<br>+};<br>+<br>+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);<br>+<br>+#if ENV_RAMSTAGE<br>+<br>+static int spi_dev_to_bus(struct device *dev)<br>+{<br>+ return spi_devfn_to_bus(dev->path.pci.devfn);<br>+}<br>+<br>+static struct spi_bus_operations spi_bus_ops = {<br>+ .dev_to_bus = &spi_dev_to_bus,<br>+};<br>+<br>+static struct device_operations spi_dev_ops = {<br>+ .read_resources = &pci_dev_read_resources,<br>+ .set_resources = &pci_dev_set_resources,<br>+ .enable_resources = &pci_dev_enable_resources,<br>+ .scan_bus = &scan_generic_bus,<br>+ .ops_spi_bus = &spi_bus_ops,<br>+};<br>+<br>+static const unsigned short pci_device_ids[] = {<br>+ PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI,<br>+ PCI_DEVICE_ID_INTEL_CNL_SPI0,<br>+ PCI_DEVICE_ID_INTEL_CNL_SPI1,<br>+ PCI_DEVICE_ID_INTEL_CNL_SPI2,<br>+ 0<br>+};<br>+<br>+static const struct pci_driver pch_spi __pci_driver = {<br>+ .ops = &spi_dev_ops,<br>+ .vendor = PCI_VENDOR_ID_INTEL,<br>+ .devices = pci_device_ids,<br>+};<br>+#endif<br></pre><p>To view, visit <a href="https://review.coreboot.org/21052">change 21052</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21052"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ie45146721f39d3cec20ff5136adf8925c75da1cd </div>
<div style="display:none"> Gerrit-Change-Number: 21052 </div>
<div style="display:none"> Gerrit-PatchSet: 4 </div>
<div style="display:none"> Gerrit-Owner: Lijian Zhao <lijian.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org> </div>
<div style="display:none"> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar@intel.com> </div>
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<div style="display:none"> Gerrit-Reviewer: Hannah Williams <hannah.williams@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: John Zhao <john.zhao@intel.com> </div>
<div style="display:none"> Gerrit-Reviewer: Lijian Zhao <lijian.zhao@intel.com> </div>
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