<p>Pratikkumar V Prajapati has uploaded this change for <strong>review</strong>.</p><p><a href="https://review.coreboot.org/21010">View Change</a></p><pre style="font-family: monospace,monospace; white-space: pre-wrap;">intel/common/mp_init: Refactor MP Init code to get rid of microcode param<br><br>Refactor MP Init which<br>- removes global variable for microcode<br>- remove passing microcode patch pointer as param<br>- uses device_t data pointer for microcode pointer usage<br><br>Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b<br>Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com><br>---<br>M src/soc/intel/common/block/cpu/mp_init.c<br>M src/soc/intel/common/block/include/intelblocks/mp_init.h<br>M src/soc/intel/skylake/cpu.c<br>3 files changed, 16 insertions(+), 29 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/21010/1</pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c<br>index 7e57b79..a5138eb 100644<br>--- a/src/soc/intel/common/block/cpu/mp_init.c<br>+++ b/src/soc/intel/common/block/cpu/mp_init.c<br>@@ -27,24 +27,21 @@<br> #include <intelblocks/msr.h><br> #include <soc/cpu.h><br> <br>-static const void *microcode_patch;<br>-<br> /* SoC override function */<br>-__attribute__((weak)) void soc_core_init(device_t dev, const void *microcode)<br>+__attribute__((weak)) void soc_core_init(device_t dev)<br> {<br> /* no-op */<br> }<br> <br>-__attribute__((weak)) void soc_init_cpus(struct bus *cpu_bus,<br>- const void *microcode)<br>+__attribute__((weak)) void soc_init_cpus(struct bus *cpu_bus)<br> {<br> /* no-op */<br> }<br> <br>-static void init_one_cpu(device_t dev)<br>+static void init_one_cpu(device_t dev)<br> {<br>- soc_core_init(dev, microcode_patch);<br>- intel_microcode_load_unlocked(microcode_patch);<br>+ soc_core_init(dev);<br>+ intel_microcode_load_unlocked(dev->data);<br> }<br> <br> static struct device_operations cpu_dev_ops = {<br>@@ -102,7 +99,10 @@<br> */<br> void get_microcode_info(const void **microcode, int *parallel)<br> {<br>- *microcode = microcode_patch;<br>+ device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);<br>+ assert(dev != NULL);<br>+<br>+ *microcode = dev->data;<br> *parallel = 1;<br> }<br> <br>@@ -111,23 +111,10 @@<br> device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER);<br> assert(dev != NULL);<br> <br>- microcode_patch = intel_microcode_find();<br>- intel_microcode_load_unlocked(microcode_patch);<br>+ dev->data = intel_microcode_find();<br>+ intel_microcode_load_unlocked(dev->data);<br> <br>- dev->data = microcode_patch;<br>- /*<br>- * TODO: This parameter "microcode_patch" should be removed<br>- * in this function call once the following two cases are resolved -<br>- *<br>- * 1) SGX enabling for the BSP issue gets solved, due to which<br>- * configure_sgx() function is kept inside soc/cpu.c soc_init_cpus().<br>- * 2) uCode loading after SMM relocation is deleted inside<br>- * per_cpu_smm_trigger() mp_ops callback function in soc/cpu.c,<br>- * since as per current BWG, uCode loading can be done after<br>- * all feature programmings are done. There is no specific<br>- * recommendation to do it after SMM Relocation.<br>- */<br>- soc_init_cpus(dev->link_list, microcode_patch);<br>+ soc_init_cpus(dev->link_list);<br> }<br> <br> /* Ensure to re-program all MTRRs based on DRAM resource settings */<br>diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h<br>index 1e5531c..7118d70 100644<br>--- a/src/soc/intel/common/block/include/intelblocks/mp_init.h<br>+++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h<br>@@ -62,7 +62,7 @@<br> * In this function SOC must perform CPU feature programming<br> * during Ramstage phase.<br> */<br>-void soc_core_init(device_t dev, const void *microcode);<br>+void soc_core_init(device_t dev);<br> <br> /*<br> * In this function SOC must fill required mp_ops params, also it<br>@@ -72,6 +72,6 @@<br> * Also, if there is any other SOC specific functionalities to be<br> * implemented before or after MP Init, it can be done here.<br> */<br>-void soc_init_cpus(struct bus *cpu_bus, const void *microcode);<br>+void soc_init_cpus(struct bus *cpu_bus);<br> <br> #endif /* SOC_INTEL_COMMON_BLOCK_MP_INIT_H */<br>diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c<br>index e20e5a0..9ade614 100644<br>--- a/src/soc/intel/skylake/cpu.c<br>+++ b/src/soc/intel/skylake/cpu.c<br>@@ -407,7 +407,7 @@<br> }<br> <br> /* All CPUs including BSP will run the following function. */<br>-void soc_core_init(device_t cpu, const void *microcode)<br>+void soc_core_init(device_t cpu)<br> {<br> /* Clear out pending MCEs */<br> configure_mca();<br>@@ -491,7 +491,7 @@<br> .post_mp_init = post_mp_init,<br> };<br> <br>-void soc_init_cpus(struct bus *cpu_bus, const void *microcode)<br>+void soc_init_cpus(struct bus *cpu_bus)<br> {<br> if (mp_init_with_smm(cpu_bus, &mp_ops))<br> printk(BIOS_ERR, "MP initialization failure.\n");<br></pre><p>To view, visit <a href="https://review.coreboot.org/21010">change 21010</a>. To unsubscribe, visit <a href="https://review.coreboot.org/settings">settings</a>.</p><div itemscope itemtype="http://schema.org/EmailMessage"><div itemscope itemprop="action" itemtype="http://schema.org/ViewAction"><link itemprop="url" href="https://review.coreboot.org/21010"/><meta itemprop="name" content="View Change"/></div></div>
<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: newchange </div>
<div style="display:none"> Gerrit-Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b </div>
<div style="display:none"> Gerrit-Change-Number: 21010 </div>
<div style="display:none"> Gerrit-PatchSet: 1 </div>
<div style="display:none"> Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> </div>