<p>Martin Roth <strong>merged</strong> this change.</p><p><a href="https://review.coreboot.org/20906">View Change</a></p><div style="white-space:pre-wrap">Approvals:
build bot (Jenkins): Verified
Patrick Rudolph: Looks good to me, approved
</div><pre style="font-family: monospace,monospace; white-space: pre-wrap;">sb/intel/i82801jx: Remove dead code<br><br>Setting up default BARs and DMI init code is done in northbridge<br>code.<br><br>Change-Id: I6cfa3018ca7f5ef351415c4ec6e178ade353f7a7<br>Signed-off-by: Arthur Heymans <arthur@aheymans.xyz><br>Reviewed-on: https://review.coreboot.org/20906<br>Tested-by: build bot (Jenkins) <no-reply@coreboot.org><br>Reviewed-by: Patrick Rudolph <siro@das-labor.org><br>---<br>D src/southbridge/intel/i82801jx/dmi_setup.c<br>D src/southbridge/intel/i82801jx/early_init.c<br>M src/southbridge/intel/i82801jx/i82801jx.h<br>3 files changed, 0 insertions(+), 203 deletions(-)<br><br></pre><pre style="font-family: monospace,monospace; white-space: pre-wrap;">diff --git a/src/southbridge/intel/i82801jx/dmi_setup.c b/src/southbridge/intel/i82801jx/dmi_setup.c<br>deleted file mode 100644<br>index 83633a4..0000000<br>--- a/src/southbridge/intel/i82801jx/dmi_setup.c<br>+++ /dev/null<br>@@ -1,141 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2012 secunet Security Networks AG<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include <device/pci_def.h><br>-#include <console/console.h><br>-#include <northbridge/intel/gm45/gm45.h><br>-#include "i82801jx.h"<br>-<br>-/* VC1 Port Arbitration Table */<br>-static const u8 vc1_pat[] = {<br>- 0x0f, 0x00, 0x00, 0x00,<br>- 0x00, 0x00, 0x0f, 0x00,<br>- 0x00, 0x00, 0x00, 0x00,<br>- 0xf0, 0x00, 0x00, 0x00,<br>- 0x00, 0x00, 0x00, 0x0f,<br>- 0x00, 0x00, 0x00, 0x00,<br>- 0x00, 0xf0, 0x00, 0x00,<br>- 0x00, 0x00, 0x00, 0x00,<br>- 0x0f, 0x00, 0x00, 0x00,<br>- 0x00, 0x00, 0x0f, 0x00,<br>- 0x00, 0x00, 0x00, 0x00,<br>- 0xf0, 0x00, 0x00, 0x00,<br>- 0x00, 0x00, 0x00, 0x0f,<br>- 0x00, 0x00, 0x00, 0x00,<br>- 0x00, 0xf0, 0x00, 0x00,<br>- 0x00, 0x00, 0x00, 0x00,<br>-};<br>-void i82801jx_dmi_setup(void)<br>-{<br>- int i;<br>- u32 reg32;<br>-<br>- RCBA32(RCBA_V1CAP) = (RCBA32(RCBA_V1CAP) & ~(0x7f<<16)) | (0x12<<16);<br>-<br>- RCBA32(0x0088) = 0x00109000;<br>- RCBA16(0x01fc) = 0x060b;<br>- RCBA32(0x01f4) = 0x86000040;<br>- RCBA8 (0x0220) = 0x45;<br>- RCBA32(0x2024) &= ~(1 << 7);<br>-<br>-<br>- /* VC1 setup for isochronous transfers: */<br>-<br>- /* Set VC1 virtual channel id to 1. */<br>- RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 24)) | (0x1 << 24);<br>- /* Enable TC7 traffic on VC1. */<br>- RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7f << 1)) | (1 << 7);<br>- /* Disable TC7-TC1 traffic on VC0. */<br>- RCBA32(RCBA_V0CTL) &= ~(0x7f << 1);<br>- /* TC7-TC1 traffic on PCIe root ports will be disabled in pci driver. */<br>-<br>- /* Set table type to time-based WRR. */<br>- RCBA32(RCBA_V1CTL) = (RCBA32(RCBA_V1CTL) & ~(0x7 << 17)) | (0x4 << 17);<br>- /* Program port arbitration table. */<br>- for (i = 0; i < sizeof(vc1_pat); ++i)<br>- RCBA8(RCBA_PAT + i) = vc1_pat[i];<br>- /* Load port arbitration table. */<br>- RCBA32(RCBA_V1CTL) |= (1 << 16);<br>-<br>- /* Enable VC1. */<br>- RCBA32(RCBA_V1CTL) |= (1 << 31);<br>-<br>-<br>- /* Setup RCRB: */<br>-<br>- /* Set component id to 2 for southbridge, northbridge has id 1. */<br>- RCBA8(RCBA_ESD + 2) = 2;<br>- /* Set target port number and target component id of the northbridge. */<br>- RCBA8(RCBA_ULD + 3) = 1;<br>- RCBA8(RCBA_ULD + 2) = 1;<br>- /* Set target rcrb base address, i.e. DMIBAR. */<br>- RCBA32(RCBA_ULBA) = (uintptr_t)DEFAULT_DMIBAR;<br>-<br>- /* Enable ASPM. */<br>- if (LPC_IS_MOBILE(PCI_DEV(0, 0x1f, 0))) {<br>- reg32 = RCBA32(RCBA_DMC);<br>- /* Enable mobile specific power saving (set this first). */<br>- reg32 = (reg32 & ~(3 << 10)) | (1 << 10);<br>- RCBA32(RCBA_DMC) = reg32;<br>- /* Enable DMI power savings. */<br>- reg32 |= (1 << 19);<br>- RCBA32(RCBA_DMC) = reg32;<br>- /* Advertise L0s and L1. */<br>- RCBA32(RCBA_LCAP) |= (3 << 10);<br>- /* Enable L0s and L1. */<br>- RCBA32(RCBA_LCTL) |= (3 << 0);<br>- } else {<br>- /* Enable DMI power savings. */<br>- RCBA32(RCBA_DMC) |= (1 << 19);<br>- /* Advertise L0s only. */<br>- RCBA32(RCBA_LCAP) = (RCBA32(RCBA_LCAP) & ~(3<<10)) | (1<<10);<br>- /* Enable L0s only. */<br>- RCBA32(RCBA_LCTL) = (RCBA32(RCBA_LCTL) & ~(3<< 0)) | (1<< 0);<br>- }<br>-}<br>-<br>-/* Should be called after VC1 has been enabled on both sides. */<br>-void i82801jx_dmi_poll_vc1(void)<br>-{<br>- int timeout;<br>-<br>- timeout = 0x7ffff;<br>- printk(BIOS_DEBUG, "ICH10 waits for VC1 negotiation... ");<br>- while ((RCBA32(RCBA_V1STS) & (1 << 1)) && --timeout) {}<br>- if (!timeout)<br>- printk(BIOS_DEBUG, "timeout!\n");<br>- else<br>- printk(BIOS_DEBUG, "done.\n");<br>-<br>- /* Check for x2 DMI link. */<br>- if (((RCBA16(RCBA_LSTS) >> 4) & 0x3f) == 2) {<br>- printk(BIOS_DEBUG, "x2 DMI link detected.\n");<br>- RCBA32(0x2024) = (RCBA32(0x2024) & ~(7 << 21)) | (3 << 21);<br>- RCBA16(0x20c4) |= (1 << 15);<br>- RCBA16(0x20e4) |= (1 << 15);<br>- /* TODO: Maybe we have to save and<br>- restore these settings across S3. */<br>- }<br>-<br>- timeout = 0x7ffff;<br>- printk(BIOS_DEBUG, "ICH10 waits for port arbitration table update... ");<br>- while ((RCBA32(RCBA_V1STS) & (1 << 0)) && --timeout) {}<br>- if (!timeout)<br>- printk(BIOS_DEBUG, "timeout!\n");<br>- else<br>- printk(BIOS_DEBUG, "done.\n");<br>-}<br>diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c<br>deleted file mode 100644<br>index e2ac852..0000000<br>--- a/src/southbridge/intel/i82801jx/early_init.c<br>+++ /dev/null<br>@@ -1,59 +0,0 @@<br>-/*<br>- * This file is part of the coreboot project.<br>- *<br>- * Copyright (C) 2012 secunet Security Networks AG<br>- *<br>- * This program is free software; you can redistribute it and/or<br>- * modify it under the terms of the GNU General Public License as<br>- * published by the Free Software Foundation; version 2 of<br>- * the License.<br>- *<br>- * This program is distributed in the hope that it will be useful,<br>- * but WITHOUT ANY WARRANTY; without even the implied warranty of<br>- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the<br>- * GNU General Public License for more details.<br>- */<br>-<br>-#include <arch/io.h><br>-#include "i82801jx.h"<br>-<br>-void i82801jx_early_init(void)<br>-{<br>- const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);<br>-<br>- /* Set up RCBA. */<br>- pci_write_config32(d31f0, D31F0_RCBA, (uintptr_t)DEFAULT_RCBA | 1);<br>-<br>- /* Set up PMBASE. */<br>- pci_write_config32(d31f0, D31F0_PMBASE, DEFAULT_PMBASE | 1);<br>- /* Enable PMBASE. */<br>- pci_write_config8(d31f0, D31F0_ACPI_CNTL, 0x80);<br>-<br>- /* Set up GPIOBASE. */<br>- pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE);<br>- /* Enable GPIO. */<br>- pci_write_config8(d31f0, D31F0_GPIO_CNTL,<br>- pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10);<br>-<br>- /* Reset watchdog. */<br>- outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */<br>- outw(0x0002, DEFAULT_TCOBASE + 0x06); /* R/WC, clear second timeout. */<br>-<br>- /* Enable upper 128bytes of CMOS. */<br>- RCBA32(0x3400) = (1 << 2);<br>-<br>- /* Initialize power management initialization<br>- register early as it affects reboot behavior. */<br>- /* Bit 20 activates global reset of host and ME on cf9 writes of 0x6<br>- and 0xe (required if ME is disabled but present), bit 31 locks it.<br>- The other bits are 'must write'. */<br>- u8 reg8 = pci_read_config8(d31f0, 0xac);<br>- reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8);<br>- pci_write_config8(d31f0, 0xac, reg8);<br>-<br>- /* TODO: If RTC power failed, reset RTC state machine<br>- (set, then reset RTC 0x0b bit7) */<br>-<br>- /* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2)<br>- before they get cleared. */<br>-}<br>diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h<br>index fe55157..9b0f955 100644<br>--- a/src/southbridge/intel/i82801jx/i82801jx.h<br>+++ b/src/southbridge/intel/i82801jx/i82801jx.h<br>@@ -229,9 +229,6 @@<br> int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf);<br> int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes,<br> const u8 *buf);<br>-void i82801jx_early_init(void);<br>-void i82801jx_dmi_setup(void);<br>-void i82801jx_dmi_poll_vc1(void);<br> int southbridge_detect_s3_resume(void);<br> #endif<br> <br></pre><p>To view, visit <a href="https://review.coreboot.org/20906">change 20906</a>. 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<div style="display:none"> Gerrit-Project: coreboot </div>
<div style="display:none"> Gerrit-Branch: master </div>
<div style="display:none"> Gerrit-MessageType: merged </div>
<div style="display:none"> Gerrit-Change-Id: I6cfa3018ca7f5ef351415c4ec6e178ade353f7a7 </div>
<div style="display:none"> Gerrit-Change-Number: 20906 </div>
<div style="display:none"> Gerrit-PatchSet: 2 </div>
<div style="display:none"> Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz> </div>
<div style="display:none"> Gerrit-Reviewer: Martin Roth <martinroth@google.com> </div>
<div style="display:none"> Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org> </div>
<div style="display:none"> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> </div>